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[8.43.85.97]) by mx.google.com with ESMTPS id k4-20020a50cb84000000b00453688643fasi14905089edi.260.2022.10.20.02.34.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 02:34:16 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=vCw6y1AM; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D5A7E38207D3 for ; Thu, 20 Oct 2022 09:30:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D5A7E38207D3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666258212; bh=m/rtH/VKkbVKFMtdSHn0eho7NdrXEF175jcMkuXR46w=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=vCw6y1AMxFvewj05UJnhxsE6oqsLKaFcpQPa1Nq48JROGkmujTe8Rxa2tw3isyiOa 8ZsgtiZxxuHySoO4K6+dFMp1vBpNiu7GMee5IiObb2yUXYXj3JkY5frPzJmABwN/nr Xl28i39f149t+F22ld37JwpQxM0E+AH5/Bp3IKOo= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 4B195385021A for ; Thu, 20 Oct 2022 09:27:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4B195385021A Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 9741E300089; Thu, 20 Oct 2022 09:27:50 +0000 (UTC) To: Tsukasa OI , Andrew Burgess , Mike Frysinger , Nick Clifton Subject: [PATCH 07/40] sim/cris: Regenerate with CGEN Date: Thu, 20 Oct 2022 09:25:53 +0000 Message-Id: <69ef2d7dd519ed572511890a215a0f6d74e53384.1666257885.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747198627771109446?= X-GMAIL-MSGID: =?utf-8?q?1747198627771109446?= All CRIS-related files are regenerated by custom CGEN that is modified by the author (CGEN change will be separately upstreamed). --- sim/cris/arch.c | 5 +++-- sim/cris/arch.h | 21 +++++++++++++++------ sim/cris/cpuall.h | 5 +++-- sim/cris/cpuv10.c | 6 ++++-- sim/cris/cpuv10.h | 5 +++-- sim/cris/cpuv32.c | 6 ++++-- sim/cris/cpuv32.h | 5 +++-- sim/cris/decodev10.c | 21 +++++++++++---------- sim/cris/decodev10.h | 6 +++--- sim/cris/decodev32.c | 21 +++++++++++---------- sim/cris/decodev32.h | 8 ++++---- sim/cris/modelv10.c | 5 +++-- sim/cris/modelv32.c | 5 +++-- sim/cris/semcrisv10f-switch.c | 20 +++++++++++++------- sim/cris/semcrisv32f-switch.c | 20 +++++++++++++------- 15 files changed, 96 insertions(+), 63 deletions(-) diff --git a/sim/cris/arch.c b/sim/cris/arch.c index 1d50838f0a1..b502c239fca 100644 --- a/sim/cris/arch.c +++ b/sim/cris/arch.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ diff --git a/sim/cris/arch.h b/sim/cris/arch.h index 037b463438d..57d51236c03 100644 --- a/sim/cris/arch.h +++ b/sim/cris/arch.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,13 +17,22 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ #ifndef CRIS_ARCH_H #define CRIS_ARCH_H +#define TARGET_BIG_ENDIAN 1 + +#define WI SI +#define UWI USI +#define AI USI + +#define IAI USI + /* Enum declaration for model types. */ typedef enum model_type { MODEL_CRISV10, MODEL_CRISV32, MODEL_MAX @@ -36,10 +45,10 @@ typedef enum unit_type { UNIT_NONE, UNIT_CRISV10_U_MOVEM, UNIT_CRISV10_U_MULTIPLY, UNIT_CRISV10_U_SKIP4 , UNIT_CRISV10_U_STALL, UNIT_CRISV10_U_CONST32, UNIT_CRISV10_U_CONST16, UNIT_CRISV10_U_MEM , UNIT_CRISV10_U_EXEC, UNIT_CRISV32_U_EXEC_TO_SR, UNIT_CRISV32_U_EXEC_MOVEM, UNIT_CRISV32_U_EXEC - , UNIT_CRISV32_U_SKIP4, UNIT_CRISV32_U_CONST32, UNIT_CRISV32_U_CONST16, UNIT_CRISV32_U_JUMP - , UNIT_CRISV32_U_JUMP_SR, UNIT_CRISV32_U_JUMP_R, UNIT_CRISV32_U_BRANCH, UNIT_CRISV32_U_MULTIPLY - , UNIT_CRISV32_U_MOVEM_MTOR, UNIT_CRISV32_U_MOVEM_RTOM, UNIT_CRISV32_U_MEM_W, UNIT_CRISV32_U_MEM_R - , UNIT_CRISV32_U_MEM, UNIT_MAX + , UNIT_CRISV32_U_STALL, UNIT_CRISV32_U_SKIP4, UNIT_CRISV32_U_CONST32, UNIT_CRISV32_U_CONST16 + , UNIT_CRISV32_U_JUMP, UNIT_CRISV32_U_JUMP_SR, UNIT_CRISV32_U_JUMP_R, UNIT_CRISV32_U_BRANCH + , UNIT_CRISV32_U_MULTIPLY, UNIT_CRISV32_U_MOVEM_MTOR, UNIT_CRISV32_U_MOVEM_RTOM, UNIT_CRISV32_U_MEM_W + , UNIT_CRISV32_U_MEM_R, UNIT_CRISV32_U_MEM, UNIT_MAX } UNIT_TYPE; #define MAX_UNITS (4) diff --git a/sim/cris/cpuall.h b/sim/cris/cpuall.h index 145646f4ed0..c600f5d3a31 100644 --- a/sim/cris/cpuall.h +++ b/sim/cris/cpuall.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ diff --git a/sim/cris/cpuv10.c b/sim/cris/cpuv10.c index d53aa556e73..d188590e486 100644 --- a/sim/cris/cpuv10.c +++ b/sim/cris/cpuv10.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -490,3 +491,4 @@ crisv10f_h_prefixreg_pre_v32_set (SIM_CPU *current_cpu, SI newval) { CPU (h_prefixreg_pre_v32) = newval; } + diff --git a/sim/cris/cpuv10.h b/sim/cris/cpuv10.h index 30555c8244e..296279ff918 100644 --- a/sim/cris/cpuv10.h +++ b/sim/cris/cpuv10.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ diff --git a/sim/cris/cpuv32.c b/sim/cris/cpuv32.c index ad9af980aa1..997ef2c7533 100644 --- a/sim/cris/cpuv32.c +++ b/sim/cris/cpuv32.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -586,3 +587,4 @@ crisv32f_h_prefixreg_v32_set (SIM_CPU *current_cpu, SI newval) { SET_H_PREFIXREG_V32 (newval); } + diff --git a/sim/cris/cpuv32.h b/sim/cris/cpuv32.h index b23eff4f52a..affb72f99b8 100644 --- a/sim/cris/cpuv32.h +++ b/sim/cris/cpuv32.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ diff --git a/sim/cris/decodev10.c b/sim/cris/decodev10.c index 257961ae160..ebf511c1a2d 100644 --- a/sim/cris/decodev10.c +++ b/sim/cris/decodev10.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -41,12 +42,12 @@ static IDESC crisv10f_insn_data[CRISV10F_INSN__MAX]; static const struct insn_sem crisv10f_insn_sem[] = { - { VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_AFTER, CRISV10F_INSN_X_AFTER, CRISV10F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_BEFORE, CRISV10F_INSN_X_BEFORE, CRISV10F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_CTI_CHAIN, CRISV10F_INSN_X_CTI_CHAIN, CRISV10F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_CHAIN, CRISV10F_INSN_X_CHAIN, CRISV10F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_BEGIN, CRISV10F_INSN_X_BEGIN, CRISV10F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, CRISV10F_INSN_X_AFTER, CRISV10F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, CRISV10F_INSN_X_BEFORE, CRISV10F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, CRISV10F_INSN_X_CTI_CHAIN, CRISV10F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, CRISV10F_INSN_X_CHAIN, CRISV10F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, CRISV10F_INSN_X_BEGIN, CRISV10F_SFMT_EMPTY }, { CRIS_INSN_NOP, CRISV10F_INSN_NOP, CRISV10F_SFMT_NOP }, { CRIS_INSN_MOVE_B_R, CRISV10F_INSN_MOVE_B_R, CRISV10F_SFMT_MOVE_B_R }, { CRIS_INSN_MOVE_W_R, CRISV10F_INSN_MOVE_W_R, CRISV10F_SFMT_MOVE_B_R }, @@ -254,7 +255,7 @@ static const struct insn_sem crisv10f_insn_sem[] = static const struct insn_sem crisv10f_insn_sem_invalid = { - VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY + (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV10F_INSN_X_INVALID, CRISV10F_SFMT_EMPTY }; /* Initialize an IDESC from the compile-time computable parts. */ @@ -303,7 +304,7 @@ crisv10f_init_idesc_table (SIM_CPU *cpu) init_idesc (cpu, id, t); /* Now fill in the values for the chosen cpu. */ - for (t = crisv10f_insn_sem, tend = t + ARRAY_SIZE (crisv10f_insn_sem); + for (t = crisv10f_insn_sem, tend = t + sizeof (crisv10f_insn_sem) / sizeof (*t); t != tend; ++t) { init_idesc (cpu, & table[t->index], t); diff --git a/sim/cris/decodev10.h b/sim/cris/decodev10.h index c742c2fe9c6..a3307ad8d21 100644 --- a/sim/cris/decodev10.h +++ b/sim/cris/decodev10.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -30,7 +31,6 @@ extern const IDESC *crisv10f_decode (SIM_CPU *, IADDR, extern void crisv10f_init_idesc_table (SIM_CPU *); extern void crisv10f_sem_init_idesc_table (SIM_CPU *); extern void crisv10f_semf_init_idesc_table (SIM_CPU *); -extern void crisv10f_specific_init (SIM_CPU *); /* Enum declaration for instructions in cpu family crisv10f. */ typedef enum crisv10f_insn_type { diff --git a/sim/cris/decodev32.c b/sim/cris/decodev32.c index d6afafa377f..c382f9f6b2f 100644 --- a/sim/cris/decodev32.c +++ b/sim/cris/decodev32.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -41,12 +42,12 @@ static IDESC crisv32f_insn_data[CRISV32F_INSN__MAX]; static const struct insn_sem crisv32f_insn_sem[] = { - { VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_AFTER, CRISV32F_INSN_X_AFTER, CRISV32F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_BEFORE, CRISV32F_INSN_X_BEFORE, CRISV32F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_CTI_CHAIN, CRISV32F_INSN_X_CTI_CHAIN, CRISV32F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_CHAIN, CRISV32F_INSN_X_CHAIN, CRISV32F_SFMT_EMPTY }, - { VIRTUAL_INSN_X_BEGIN, CRISV32F_INSN_X_BEGIN, CRISV32F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, CRISV32F_INSN_X_AFTER, CRISV32F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, CRISV32F_INSN_X_BEFORE, CRISV32F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, CRISV32F_INSN_X_CTI_CHAIN, CRISV32F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, CRISV32F_INSN_X_CHAIN, CRISV32F_SFMT_EMPTY }, + { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, CRISV32F_INSN_X_BEGIN, CRISV32F_SFMT_EMPTY }, { CRIS_INSN_MOVE_B_R, CRISV32F_INSN_MOVE_B_R, CRISV32F_SFMT_MOVE_B_R }, { CRIS_INSN_MOVE_W_R, CRISV32F_INSN_MOVE_W_R, CRISV32F_SFMT_MOVE_B_R }, { CRIS_INSN_MOVE_D_R, CRISV32F_INSN_MOVE_D_R, CRISV32F_SFMT_MOVE_D_R }, @@ -258,7 +259,7 @@ static const struct insn_sem crisv32f_insn_sem[] = static const struct insn_sem crisv32f_insn_sem_invalid = { - VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY + (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, CRISV32F_INSN_X_INVALID, CRISV32F_SFMT_EMPTY }; /* Initialize an IDESC from the compile-time computable parts. */ @@ -307,7 +308,7 @@ crisv32f_init_idesc_table (SIM_CPU *cpu) init_idesc (cpu, id, t); /* Now fill in the values for the chosen cpu. */ - for (t = crisv32f_insn_sem, tend = t + ARRAY_SIZE (crisv32f_insn_sem); + for (t = crisv32f_insn_sem, tend = t + sizeof (crisv32f_insn_sem) / sizeof (*t); t != tend; ++t) { init_idesc (cpu, & table[t->index], t); diff --git a/sim/cris/decodev32.h b/sim/cris/decodev32.h index aae993b7881..94c483b03a1 100644 --- a/sim/cris/decodev32.h +++ b/sim/cris/decodev32.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -30,7 +31,6 @@ extern const IDESC *crisv32f_decode (SIM_CPU *, IADDR, extern void crisv32f_init_idesc_table (SIM_CPU *); extern void crisv32f_sem_init_idesc_table (SIM_CPU *); extern void crisv32f_semf_init_idesc_table (SIM_CPU *); -extern void crisv32f_specific_init (SIM_CPU *); /* Enum declaration for instructions in cpu family crisv32f. */ typedef enum crisv32f_insn_type { @@ -126,8 +126,8 @@ typedef enum crisv32f_sfmt_type { extern int crisv32f_model_crisv32_u_exec_to_sr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Pd*/); extern int crisv32f_model_crisv32_u_exec_movem (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rs*/, INT /*Rd*/); extern int crisv32f_model_crisv32_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rd*/, INT /*Rs*/, INT /*Rd*/); -extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); extern int crisv32f_model_crisv32_u_stall (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); +extern int crisv32f_model_crisv32_u_skip4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); extern int crisv32f_model_crisv32_u_const32 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); extern int crisv32f_model_crisv32_u_const16 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/); extern int crisv32f_model_crisv32_u_jump (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Pd*/); diff --git a/sim/cris/modelv10.c b/sim/cris/modelv10.c index 2ff4f5262b2..1f0d5fa367d 100644 --- a/sim/cris/modelv10.c +++ b/sim/cris/modelv10.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ diff --git a/sim/cris/modelv32.c b/sim/cris/modelv32.c index 86087f99ff4..f056fd41c26 100644 --- a/sim/cris/modelv32.c +++ b/sim/cris/modelv32.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ diff --git a/sim/cris/semcrisv10f-switch.c b/sim/cris/semcrisv10f-switch.c index f31b29442fd..a2f1505405e 100644 --- a/sim/cris/semcrisv10f-switch.c +++ b/sim/cris/semcrisv10f-switch.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -260,7 +261,7 @@ This file is part of the GNU simulators. /* If hyper-fast [well not unnecessarily slow] execution is selected, turn off frills like tracing and profiling. */ -/* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something +/* FIXME: A better way would be to have TRACE_RESULT check for something that can cause it to be optimized out. Another way would be to emit special handlers into the instruction "stream". */ @@ -3379,6 +3380,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register"); SI tmp_rno; SI tmp_newval; tmp_rno = FLD (f_operand2); + tmp_newval = 0; if (EQSI (tmp_rno, 5)) { tmp_newval = EXTHISI (({ SI tmp_addr; HI tmp_tmp_mem; @@ -10993,7 +10995,8 @@ SET_H_VBIT_MOVE (0); tmp_tmpd = ({ SI tmp_tmpcode; SI tmp_tmpval; SI tmp_tmpres; - tmp_tmpcode = FLD (f_operand2); + tmp_tmpres = 0; +; tmp_tmpcode = FLD (f_operand2); ; tmp_tmpval = tmp_tmps; ; if (EQSI (tmp_tmpcode, 0)) { tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0); @@ -12060,7 +12063,8 @@ if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) { BI tmp_truthval; tmp_truthval = ({ SI tmp_tmpcond; BI tmp_condres; - tmp_tmpcond = FLD (f_operand2); + tmp_condres = 0; +; tmp_tmpcond = FLD (f_operand2); ; if (EQSI (tmp_tmpcond, 0)) { tmp_condres = NOTBI (CPU (h_cbit)); } @@ -12192,7 +12196,8 @@ if (tmp_truthval) { BI tmp_truthval; tmp_truthval = ({ SI tmp_tmpcond; BI tmp_condres; - tmp_tmpcond = FLD (f_operand2); + tmp_condres = 0; +; tmp_tmpcond = FLD (f_operand2); ; if (EQSI (tmp_tmpcond, 0)) { tmp_condres = NOTBI (CPU (h_cbit)); } @@ -13065,7 +13070,8 @@ SET_H_VBIT_MOVE (0); BI tmp_truthval; tmp_truthval = ({ SI tmp_tmpcond; BI tmp_condres; - tmp_tmpcond = FLD (f_operand2); + tmp_condres = 0; +; tmp_tmpcond = FLD (f_operand2); ; if (EQSI (tmp_tmpcond, 0)) { tmp_condres = NOTBI (CPU (h_cbit)); } diff --git a/sim/cris/semcrisv32f-switch.c b/sim/cris/semcrisv32f-switch.c index ab15d6ee36c..bf06e8aa6ca 100644 --- a/sim/cris/semcrisv32f-switch.c +++ b/sim/cris/semcrisv32f-switch.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2022 Free Software Foundation, Inc. +Copyright (C) 1996-2022 Free Software Foundation, Inc. This file is part of the GNU simulators. @@ -17,7 +17,8 @@ This file is part of the GNU simulators. License for more details. You should have received a copy of the GNU General Public License along - with this program; if not, see . + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ @@ -264,7 +265,7 @@ This file is part of the GNU simulators. /* If hyper-fast [well not unnecessarily slow] execution is selected, turn off frills like tracing and profiling. */ -/* FIXME: A better way would be to have CGEN_TRACE_RESULT check for something +/* FIXME: A better way would be to have TRACE_RESULT check for something that can cause it to be optimized out. Another way would be to emit special handlers into the instruction "stream". */ @@ -3291,6 +3292,7 @@ cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register"); SI tmp_rno; SI tmp_newval; tmp_rno = FLD (f_operand2); + tmp_newval = 0; if (EQSI (tmp_rno, 2)) { tmp_newval = ({ SI tmp_addr; SI tmp_tmp_mem; @@ -11263,7 +11265,8 @@ SET_H_VBIT_MOVE (0); tmp_tmpd = ({ SI tmp_tmpcode; SI tmp_tmpval; SI tmp_tmpres; - tmp_tmpcode = FLD (f_operand2); + tmp_tmpres = 0; +; tmp_tmpcode = FLD (f_operand2); ; tmp_tmpval = tmp_tmps; ; if (EQSI (tmp_tmpcode, 0)) { tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0); @@ -12460,7 +12463,8 @@ crisv32f_rfg_handler (current_cpu, pc); BI tmp_truthval; tmp_truthval = ({ SI tmp_tmpcond; BI tmp_condres; - tmp_tmpcond = FLD (f_operand2); + tmp_condres = 0; +; tmp_tmpcond = FLD (f_operand2); ; if (EQSI (tmp_tmpcond, 0)) { tmp_condres = NOTBI (CPU (h_cbit)); } @@ -12592,7 +12596,8 @@ if (tmp_truthval) { BI tmp_truthval; tmp_truthval = ({ SI tmp_tmpcond; BI tmp_condres; - tmp_tmpcond = FLD (f_operand2); + tmp_condres = 0; +; tmp_tmpcond = FLD (f_operand2); ; if (EQSI (tmp_tmpcond, 0)) { tmp_condres = NOTBI (CPU (h_cbit)); } @@ -13380,7 +13385,8 @@ SET_H_VBIT_MOVE (0); BI tmp_truthval; tmp_truthval = ({ SI tmp_tmpcond; BI tmp_condres; - tmp_tmpcond = FLD (f_operand2); + tmp_condres = 0; +; tmp_tmpcond = FLD (f_operand2); ; if (EQSI (tmp_tmpcond, 0)) { tmp_condres = NOTBI (CPU (h_cbit)); }