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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ay10-20020a056402202a00b0046a6960c990si2029975edb.431.2022.11.24.18.17.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Nov 2022 18:17:57 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=rMnYKxYF; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F0A4F3889E0F for ; Fri, 25 Nov 2022 02:17:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F0A4F3889E0F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669342675; bh=gOsIfNNC+9ioZW0e64w7HHq97eij6EIv+myTakNVVMM=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=rMnYKxYFk4rxEYzjRdjmo7n6lXLidyElLXxNo3asMUkIc0xJqF2gitv1H8EPu0NQ0 TatCD06XJNzLLUpcHaQXznaSS7XL1ND6dyaabrLrgU3QMD0ITay8NVjDeXdhFK/TaV 3pLM8yO9uHqIpCwSEsCxFoPrj5W2Ze4O1U1bisfQ= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 62CA23889E1E for ; Fri, 25 Nov 2022 02:17:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 62CA23889E1E Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C2114300089; Fri, 25 Nov 2022 02:17:43 +0000 (UTC) To: Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v3 1/2] RISC-V: Better support for long instructions (disassembler) Date: Fri, 25 Nov 2022 02:17:23 +0000 Message-Id: <66ca80358f78d66d66bbf390fc0be8bec8183e93.1669342633.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750432667094790247?= X-GMAIL-MSGID: =?utf-8?q?1750432667094790247?= From: Tsukasa OI Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. 1. On the disassembler, disassembler dump was limited up to 64-bit. For long (unknown) instructions, instruction bits are incorrectly zeroed out. To solve these problems, this commit adds packet argument to support dumping instructions longer than 64-bits. This commit will be tested on the next commit "RISC-V: Better support for long instructions (assembler)". opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print unknown instruction using the new argument packet. (riscv_disassemble_data): Add unused argument packet. (print_insn_riscv): Pass packet to the disassemble function. --- opcodes/riscv-dis.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 3a31647a2f80..59ebbaf13417 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -641,7 +641,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info this is little-endian code. */ static int -riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) +riscv_disassemble_insn (bfd_vma memaddr, + insn_t word, + const bfd_byte *packet, + disassemble_info *info) { const struct riscv_opcode *op; static bool init = false; @@ -806,8 +809,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) ", "); (*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x%02x", - (unsigned int) (word & 0xff)); - word >>= 8; + (unsigned int) (*packet++)); } } break; @@ -983,6 +985,7 @@ riscv_data_length (bfd_vma memaddr, static int riscv_disassemble_data (bfd_vma memaddr ATTRIBUTE_UNUSED, insn_t data, + const bfd_byte *packet ATTRIBUTE_UNUSED, disassemble_info *info) { info->display_endian = info->endian; @@ -1037,7 +1040,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) bfd_vma dump_size; int status; enum riscv_seg_mstate mstate; - int (*riscv_disassembler) (bfd_vma, insn_t, struct disassemble_info *); + int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte*, struct disassemble_info *); if (info->disassembler_options != NULL) { @@ -1081,7 +1084,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) } insn = (insn_t) bfd_get_bits (packet, dump_size * 8, false); - return (*riscv_disassembler) (memaddr, insn, info); + return (*riscv_disassembler) (memaddr, insn, packet, info); } disassembler_ftype