From patchwork Fri Nov 18 02:07:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 22055 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:adf:f944:0:0:0:0:0 with SMTP id q4csp733761wrr; Thu, 17 Nov 2022 18:10:51 -0800 (PST) X-Google-Smtp-Source: AA0mqf7HizRxwb8SGdaGmTnUgzQfVJ2a5o4XoZTh4yRLOyQiQrAg96Jx4n5+SUBkoRM7B8Y4uQP3 X-Received: by 2002:a17:906:c18c:b0:7b2:8a6e:c569 with SMTP id g12-20020a170906c18c00b007b28a6ec569mr4296527ejz.582.1668737451733; Thu, 17 Nov 2022 18:10:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668737451; cv=none; d=google.com; s=arc-20160816; b=PaGId9GP+CwD5Ecq2fe9WD7Fkl7cNjJpOlcIaoXIt7pT6f582mqWECqWowzrNxqHTI /yyCF2Ff9+SeyD9hGK07RI9cjZ9P88iMMoQbD1dd4GXygWDCpX67EnszqtEiW2eirT/y ihgXstLen96fQpYsPNtU6SY9XqjNzbR66svLNQKNuh7xyEdRE8WjmwhAFj0ctSU4ugz+ S78EyJFyDdxSKUy6ifaw+sktDmzyJzR1wh2oQWurqnRt1heFVoawQR9UKy55ma1/f11O nIt+Xdxmql3LYQVjZxx9iSjcEcBI4KctmZqXjzr4qNhgv8gsuBamai8E5TO5JJiRXtiY F6Cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=yGNaGUZ7tJchF2jYucvCzGI7vqFvJiau11NrPoVG+MA=; b=uBqiVkTBc6kivMfxJPOVPxTMC/tcGVbzPZfsuUaM88DodBbYUk4JTyFAUzES0kwX51 ARxK+38v47CJ8a2LrrEwnSMWXfEiaPcPtaPBOUdpQ/19xbxQvLmRDB9z8Wg45Q///Sb2 pDQtFA4Z1ZYYmuhfSDuLQcc13Ja2y0J39DdACivQjdJ2F/SPAvF7yxnNRQaS9SlnaKI8 TtqAtImqMUC+vZc91G+DXUDtir+taY30nm8C698oa59V+dgiPL/3rQEqLYTE3e/P2/Ty vuOavTMSVy2VO8zNg324oKJ+6YncSIA/H24ybSLUscjviGumEdb2pvHQQM+F/1abE+92 HB9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ZlpliBfP; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id qc8-20020a170906d8a800b007ae86742c3bsi1530094ejb.1009.2022.11.17.18.10.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 18:10:51 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ZlpliBfP; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B815C3839D83 for ; Fri, 18 Nov 2022 02:09:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B815C3839D83 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668737382; bh=yGNaGUZ7tJchF2jYucvCzGI7vqFvJiau11NrPoVG+MA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ZlpliBfPvpQuHf6lWq/BCAhVqmlZ1BDVFulFfVwyPdSgRpQsHPdWXOPYQBgRfvFXz QMDeB+xwUr5lsoFu6VBOJvtcL4nr+L26u3hnZ9yTihFMT1D0tdGgVy5YrFfdpWHS8A v4FiB3rQdtjqz69wfzGH/Y2RVH4ff566sh76HmQE= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 5D26B384F6E1 for ; Fri, 18 Nov 2022 02:08:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5D26B384F6E1 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 393F8300089; Fri, 18 Nov 2022 02:08:39 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH v4 4/8] RISC-V: Remove unused instruction macros Date: Fri, 18 Nov 2022 02:07:51 +0000 Message-Id: <5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747121969336214375?= X-GMAIL-MSGID: =?utf-8?q?1749798042230969057?= This commit removes unused instruction macros. include/ChangeLog: * opcode/riscv-opc.h (MATCH_SLLI_RV32, MASK_SLLI_RV32, MATCH_SRLI_RV32, MASK_SRLI_RV32, MATCH_SRAI_RV32, MASK_SRAI_RV32, MATCH_VQMACCUVV, MASK_VQMACCUVV, MATCH_VQMACCUVX, MASK_VQMACCUVX, MATCH_VQMACCVV, MASK_VQMACCVV, MATCH_VQMACCVX, MASK_VQMACCVX, MATCH_VQMACCSUVV, MASK_VQMACCSUVV, MATCH_VQMACCSUVX, MASK_VQMACCSUVX, MATCH_VQMACCUSVX, MASK_VQMACCUSVX, MATCH_VDOTVV, MASK_VDOTVV, MATCH_VDOTUVV, MASK_VDOTUVV, MATCH_VFDOTVV, MASK_VFDOTVV): Removed as no longer used. --- include/opcode/riscv-opc.h | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index f36b06dcd6bd..c6b1ca35afcb 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -21,12 +21,6 @@ #ifndef RISCV_ENCODING_H #define RISCV_ENCODING_H /* Instruction opcode macros. */ -#define MATCH_SLLI_RV32 0x1013 -#define MASK_SLLI_RV32 0xfe00707f -#define MATCH_SRLI_RV32 0x5013 -#define MASK_SRLI_RV32 0xfe00707f -#define MATCH_SRAI_RV32 0x40005013 -#define MASK_SRAI_RV32 0xfe00707f #define MATCH_FRFLAGS 0x102073 #define MASK_FRFLAGS 0xfffff07f #define MATCH_FSFLAGS 0x101073 @@ -1657,20 +1651,6 @@ #define MASK_VWMACCSUVX 0xfc00707f #define MATCH_VWMACCUSVX 0xf8006057 #define MASK_VWMACCUSVX 0xfc00707f -#define MATCH_VQMACCUVV 0xf0000057 -#define MASK_VQMACCUVV 0xfc00707f -#define MATCH_VQMACCUVX 0xf0004057 -#define MASK_VQMACCUVX 0xfc00707f -#define MATCH_VQMACCVV 0xf4000057 -#define MASK_VQMACCVV 0xfc00707f -#define MATCH_VQMACCVX 0xf4004057 -#define MASK_VQMACCVX 0xfc00707f -#define MATCH_VQMACCSUVV 0xfc000057 -#define MASK_VQMACCSUVV 0xfc00707f -#define MATCH_VQMACCSUVX 0xfc004057 -#define MASK_VQMACCSUVX 0xfc00707f -#define MATCH_VQMACCUSVX 0xf8004057 -#define MASK_VQMACCUSVX 0xfc00707f #define MATCH_VDIVVV 0x84002057 #define MASK_VDIVVV 0xfc00707f #define MATCH_VDIVVX 0x84006057 @@ -2049,12 +2029,6 @@ #define MASK_VMV4RV 0xfe0ff07f #define MATCH_VMV8RV 0x9e03b057 #define MASK_VMV8RV 0xfe0ff07f -#define MATCH_VDOTVV 0xe4000057 -#define MASK_VDOTVV 0xfc00707f -#define MATCH_VDOTUVV 0xe0000057 -#define MASK_VDOTUVV 0xfc00707f -#define MATCH_VFDOTVV 0xe4001057 -#define MASK_VFDOTVV 0xfc00707f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -2749,9 +2723,6 @@ #define CSR_VLENB 0xc22 #endif /* RISCV_ENCODING_H */ #ifdef DECLARE_INSN -DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32) -DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32) -DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32) DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS) DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS) DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)