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[v4,4/8] RISC-V: Remove unused instruction macros

Message ID 5d675a4132e2f6160d3294563e16f5093b5b1e20.1668737241.git.research_trasio@irq.a4lg.com
State Accepted
Headers
Series RISC-V: Various opcode tidying (batch 1) |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Tsukasa OI Nov. 18, 2022, 2:07 a.m. UTC 
  This commit removes unused instruction macros.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_SLLI_RV32, MASK_SLLI_RV32,
	MATCH_SRLI_RV32, MASK_SRLI_RV32, MATCH_SRAI_RV32,
	MASK_SRAI_RV32, MATCH_VQMACCUVV, MASK_VQMACCUVV,
	MATCH_VQMACCUVX, MASK_VQMACCUVX, MATCH_VQMACCVV, MASK_VQMACCVV,
	MATCH_VQMACCVX, MASK_VQMACCVX, MATCH_VQMACCSUVV,
	MASK_VQMACCSUVV, MATCH_VQMACCSUVX, MASK_VQMACCSUVX,
	MATCH_VQMACCUSVX, MASK_VQMACCUSVX, MATCH_VDOTVV, MASK_VDOTVV,
	MATCH_VDOTUVV, MASK_VDOTUVV, MATCH_VFDOTVV, MASK_VFDOTVV):
	Removed as no longer used.
---
 include/opcode/riscv-opc.h | 29 -----------------------------
 1 file changed, 29 deletions(-)
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Patch

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index f36b06dcd6bd..c6b1ca35afcb 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -21,12 +21,6 @@ 
 #ifndef RISCV_ENCODING_H
 #define RISCV_ENCODING_H
 /* Instruction opcode macros.  */
-#define MATCH_SLLI_RV32 0x1013
-#define MASK_SLLI_RV32  0xfe00707f
-#define MATCH_SRLI_RV32 0x5013
-#define MASK_SRLI_RV32  0xfe00707f
-#define MATCH_SRAI_RV32 0x40005013
-#define MASK_SRAI_RV32  0xfe00707f
 #define MATCH_FRFLAGS 0x102073
 #define MASK_FRFLAGS  0xfffff07f
 #define MATCH_FSFLAGS 0x101073
@@ -1657,20 +1651,6 @@ 
 #define MASK_VWMACCSUVX  0xfc00707f
 #define MATCH_VWMACCUSVX 0xf8006057
 #define MASK_VWMACCUSVX  0xfc00707f
-#define MATCH_VQMACCUVV  0xf0000057
-#define MASK_VQMACCUVV  0xfc00707f
-#define MATCH_VQMACCUVX  0xf0004057
-#define MASK_VQMACCUVX  0xfc00707f
-#define MATCH_VQMACCVV  0xf4000057
-#define MASK_VQMACCVV  0xfc00707f
-#define MATCH_VQMACCVX  0xf4004057
-#define MASK_VQMACCVX  0xfc00707f
-#define MATCH_VQMACCSUVV 0xfc000057
-#define MASK_VQMACCSUVV  0xfc00707f
-#define MATCH_VQMACCSUVX 0xfc004057
-#define MASK_VQMACCSUVX  0xfc00707f
-#define MATCH_VQMACCUSVX 0xf8004057
-#define MASK_VQMACCUSVX  0xfc00707f
 #define MATCH_VDIVVV  0x84002057
 #define MASK_VDIVVV  0xfc00707f
 #define MATCH_VDIVVX  0x84006057
@@ -2049,12 +2029,6 @@ 
 #define MASK_VMV4RV  0xfe0ff07f
 #define MATCH_VMV8RV  0x9e03b057
 #define MASK_VMV8RV  0xfe0ff07f
-#define MATCH_VDOTVV  0xe4000057
-#define MASK_VDOTVV  0xfc00707f
-#define MATCH_VDOTUVV  0xe0000057
-#define MASK_VDOTUVV  0xfc00707f
-#define MATCH_VFDOTVV  0xe4001057
-#define MASK_VFDOTVV  0xfc00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -2749,9 +2723,6 @@ 
 #define CSR_VLENB 0xc22
 #endif /* RISCV_ENCODING_H */
 #ifdef DECLARE_INSN
-DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
-DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
-DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
 DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
 DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
 DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)