RISC-V: Add actual 'Zvkt' extension support

Message ID 5d4af03c5b86d0bed09aab64740d6d908e86252f.1690336242.git.research_trasio@irq.a4lg.com
State Unresolved
Headers
Series RISC-V: Add actual 'Zvkt' extension support |

Checks

Context Check Description
snail/binutils-gdb-check warning Git am fail log

Commit Message

Tsukasa OI July 26, 2023, 1:51 a.m. UTC
  From: Tsukasa OI <research_trasio@irq.a4lg.com>

The 'Zvkt' extension is listed on the added extensions in the GNU Binutils
version 2.41 (see binutils/NEWS).  However, the support of this extension
was actually missing.

This commit adds actual support of this extension and adds implications
from 'Zvkn' and 'Zvks' superset extensions.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets) Add implications from
	'Zvkn' and 'Zvks'.  (riscv_supported_std_z_ext): Add 'Zvkt' to
	the supported extension list.
---
 bfd/elfxx-riscv.c | 3 +++
 1 file changed, 3 insertions(+)


base-commit: 477c9f2ba26ccd77016f2c97941fc8b35e332e35
  

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b43d2cfa0fab..ba5165766b2b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1162,6 +1162,7 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvkn", "zvknha",	check_implicit_always},
   {"zvkn", "zvknhb",	check_implicit_always},
   {"zvkn", "zvbb",	check_implicit_always},
+  {"zvkn", "zvkt",	check_implicit_always},
   {"zvkng", "zvkn",	check_implicit_always},
   {"zvkng", "zvkg",	check_implicit_always},
   {"zvknc", "zvkn",	check_implicit_always},
@@ -1169,6 +1170,7 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvks", "zvksed",	check_implicit_always},
   {"zvks", "zvksh",	check_implicit_always},
   {"zvks", "zvbb",	check_implicit_always},
+  {"zvks", "zvkt",	check_implicit_always},
   {"zvksg", "zvks",	check_implicit_always},
   {"zvksg", "zvkg",	check_implicit_always},
   {"zvksc", "zvks",	check_implicit_always},
@@ -1296,6 +1298,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvks",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkt",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },