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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id u2-20020a50eac2000000b004513a465ec6si15201992edp.94.2022.10.20.02.36.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 02:36:50 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=tb0yX1pV; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C3822395C078 for ; Thu, 20 Oct 2022 09:31:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C3822395C078 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666258275; bh=cqjVfRw22ZK50iTwDmJFzzfAC5M71DRek8GtIBTQibQ=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=tb0yX1pV6UkXGyOeVOG3fFy1xj6z1Op60P2hOtU309GC8a53wG2zGYFgpB19QS284 +Egqo7dfeUZr0NHEwrj6Jf6amMYlouhd6qt2AZeHHWvhtb4MBtuMGX4ul4kK+e33mf l+llmKZaId/bU2m9hLXfSnzKxp+609j7t6w/9XQM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 6F065384F021 for ; Thu, 20 Oct 2022 09:29:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6F065384F021 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C1382300089; Thu, 20 Oct 2022 09:29:14 +0000 (UTC) To: Tsukasa OI , Andrew Burgess , Mike Frysinger , Nick Clifton Subject: [PATCH 15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments Date: Thu, 20 Oct 2022 09:26:01 +0000 Message-Id: <5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747198788818442644?= X-GMAIL-MSGID: =?utf-8?q?1747198788818442644?= Clang generates a warning if there is a redundant self-assignment ("-Wself-assign"). On the default configuration, it causes a build failure (unless "--disable-werror" is specified). However, removing self-assignments in step_once function makes the code less readable. Instead, this commit inserts dummy addition to match the comments "Value added == 0". This is redundant but will suppress warnings and matches with other branches better. It will be also optimized away so we can ignore performance impact on this. --- sim/h8300/compile.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index 9be7dd565a9..f7d8d590b69 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -4141,7 +4141,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) res = GET_B_REG (code->src.reg); /* FIXME fetch? */ if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) && !h && (0 <= (res & 0xf) && (res & 0xf) <= 9)) - res = res; /* Value added == 0. */ + res = res + 0x0; /* Value added == 0. */ else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) && !h && (10 <= (res & 0xf) && (res & 0xf) <= 15)) res = res + 0x6; /* Value added == 6. */ @@ -4174,7 +4174,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */ if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) && !h && (0 <= (res & 0xf) && (res & 0xf) <= 9)) - res = res; /* Value added == 0. */ + res = res + 0x0; /* Value added == 0. */ else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) && h && (6 <= (res & 0xf) && (res & 0xf) <= 15)) res = res + 0xfa; /* Value added == 0xfa. */