aarch64: Add support for Common Short Sequence Compression extension

Message ID 4f1aac95-fea5-2279-cb18-dfcdb51a2589@arm.com
State Accepted
Headers
Series aarch64: Add support for Common Short Sequence Compression extension |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Andre Vieira (lists) Oct. 31, 2022, 11:14 a.m. UTC
  Hi,

This patch adds support for the CSSC extension and its corresponding
instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.

Is this OK for trunk?

gas/ChangeLog:

         * config/tc-aarch64.c (parse_operands): Handle new operand types.
         * doc/c-aarch64.texi: Document new extension.
         * testsuite/gas/aarch64/cssc.d: New test.
         * testsuite/gas/aarch64/cssc.s: New test.

include/ChangeLog:

         * opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro.
         (enum aarch64_opnd): New operand types.
         (enum aarch64_insn_class): New instruction class.

opcodes/ChangeLog:

     * aarch64-asm-2.c: Regenerate.
     * aarch64-dis-2.c: Regenerate.
     * aarch64-opc-2.c: Regenerate.
     * aarch64-opc.c (operand_general_constraint_met_p): Update for new
     operand types.
     (aarch64_print_operand): Likewise.
     * aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field.
     * aarch64-tbl.h (aarch64_feature_cssc): Define new feature set.
     (CSSC): Define new feature set Macro.
     (CSSC_INSN): Define new instruction type.
     (aarch64_opcode_table): Add new instructions.
  

Comments

Jan Beulich Oct. 31, 2022, 11:29 a.m. UTC | #1
On 31.10.2022 12:14, Andre Vieira (lists) via Binutils wrote:
> This patch adds support for the CSSC extension and its corresponding
> instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.

Any chance you could also provide a reference to the spec thereof?

Thanks, Jan
  
Andre Vieira (lists) Oct. 31, 2022, 11:45 a.m. UTC | #2
Hi Jan,

They are in the Arm A-profile A64 Instruction Set document on 
developer.arm.com. I don't know if this link is a permanent one, but for 
now 
https://documentation-service.arm.com/static/633d9270da191e7fe057eb97 
should work.
If you look for FEAT_CSSC in that document you will find the relevant 
instructions and their encoding.

Kind Regards,
Andre

On 31/10/2022 11:29, Jan Beulich wrote:
> On 31.10.2022 12:14, Andre Vieira (lists) via Binutils wrote:
>> This patch adds support for the CSSC extension and its corresponding
>> instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.
> Any chance you could also provide a reference to the spec thereof?
>
> Thanks, Jan
  
Jan Beulich Oct. 31, 2022, 1:40 p.m. UTC | #3
On 31.10.2022 12:45, Andre Vieira (lists) wrote:
> They are in the Arm A-profile A64 Instruction Set document on 
> developer.arm.com. I don't know if this link is a permanent one, but for 
> now 
> https://documentation-service.arm.com/static/633d9270da191e7fe057eb97 
> should work.
> If you look for FEAT_CSSC in that document you will find the relevant 
> instructions and their encoding.

Thanks. One minor remark on the patch itself as I was looking over it:
All new aarch64_opcode_table[] entries look to have their 2nd commas
slightly misplaced.

Jan
  
Andre Vieira (lists) Oct. 31, 2022, 4:33 p.m. UTC | #4
On 31/10/2022 13:40, Jan Beulich wrote:
> On 31.10.2022 12:45, Andre Vieira (lists) wrote:
>> They are in the Arm A-profile A64 Instruction Set document on
>> developer.arm.com. I don't know if this link is a permanent one, but for
>> now
>> https://documentation-service.arm.com/static/633d9270da191e7fe057eb97
>> should work.
>> If you look for FEAT_CSSC in that document you will find the relevant
>> instructions and their encoding.
> Thanks. One minor remark on the patch itself as I was looking over it:
> All new aarch64_opcode_table[] entries look to have their 2nd commas
> slightly misplaced.
>
> Jan
Yeah you are right, I'll fix that before committing, if it gets accepted 
without any other comments that is.

Thanks,
Andre
  
Andre Vieira (lists) Nov. 7, 2022, 9:47 a.m. UTC | #5
Fixed the whitespace typo.

On 31/10/2022 16:33, Andre Vieira (lists) via Binutils wrote:
>
> On 31/10/2022 13:40, Jan Beulich wrote:
>> On 31.10.2022 12:45, Andre Vieira (lists) wrote:
>>> They are in the Arm A-profile A64 Instruction Set document on
>>> developer.arm.com. I don't know if this link is a permanent one, but 
>>> for
>>> now
>>> https://documentation-service.arm.com/static/633d9270da191e7fe057eb97
>>> should work.
>>> If you look for FEAT_CSSC in that document you will find the relevant
>>> instructions and their encoding.
>> Thanks. One minor remark on the patch itself as I was looking over it:
>> All new aarch64_opcode_table[] entries look to have their 2nd commas
>> slightly misplaced.
>>
>> Jan
> Yeah you are right, I'll fix that before committing, if it gets 
> accepted without any other comments that is.
>
> Thanks,
> Andre
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f6fa15858325954ec9c3b86fb948b939b9227c29..165d9278ce78fae3cc7357c0ad88378a9f494470 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6636,6 +6636,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_IMM_ROT1:
 	case AARCH64_OPND_SVE_IMM_ROT2:
 	case AARCH64_OPND_SVE_IMM_ROT3:
+	case AARCH64_OPND_CSSC_SIMM8:
+	case AARCH64_OPND_CSSC_UIMM8:
 	  po_imm_nc_or_fail ();
 	  info->imm.value = val;
 	  break;
@@ -10041,6 +10043,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_ARCH_NONE},
   {"hbc",		AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0),
 			AARCH64_ARCH_NONE},
+  {"cssc",		AARCH64_FEATURE (AARCH64_FEATURE_CSSC, 0),
+			AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 0809310a9a3b3c1776bc62417865e691080bd251..eee3a4bd95bd8d06ec9297e5b0111b8e9107d7cc 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -186,6 +186,8 @@ automatically cause those extensions to be disabled.
  @tab Enable floating-point extensions.
 @item @code{hbc} @tab @tab Armv8.8-A or later
  @tab Enable Armv8.8-A hinted conditional branch instructions
+@item @code{cssc} @tab @tab Armv8.7-A or later
+ @tab Enable Armv8.9-A Common Short Sequence Compression instructions.
 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
  @tab Enable Int8 Matrix Multiply extension.
 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
diff --git a/gas/testsuite/gas/aarch64/cssc.d b/gas/testsuite/gas/aarch64/cssc.d
new file mode 100644
index 0000000000000000000000000000000000000000..4741b6584f658b0cd2dfa5f9256f94e4d14455c6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cssc.d
@@ -0,0 +1,174 @@
+#name: CSSC extension
+#as: -march=armv8-a+cssc
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+
+a.out:     file format elf64-littleaarch64
+
+
+Disassembly of section .text:
+
+0000000000000000 <.text>:
+   0:	5ac02000 	abs	w0, w0
+   4:	5ac02001 	abs	w1, w0
+   8:	5ac02100 	abs	w0, w8
+   c:	5ac020be 	abs	w30, w5
+  10:	5ac023c4 	abs	w4, w30
+  14:	dac02000 	abs	x0, x0
+  18:	dac02001 	abs	x1, x0
+  1c:	dac02100 	abs	x0, x8
+  20:	dac020be 	abs	x30, x5
+  24:	dac023c4 	abs	x4, x30
+  28:	5ac01c00 	cnt	w0, w0
+  2c:	5ac01c01 	cnt	w1, w0
+  30:	5ac01d00 	cnt	w0, w8
+  34:	5ac01cbe 	cnt	w30, w5
+  38:	5ac01fc4 	cnt	w4, w30
+  3c:	dac01c00 	cnt	x0, x0
+  40:	dac01c01 	cnt	x1, x0
+  44:	dac01d00 	cnt	x0, x8
+  48:	dac01cbe 	cnt	x30, x5
+  4c:	dac01fc4 	cnt	x4, x30
+  50:	5ac01800 	ctz	w0, w0
+  54:	5ac01801 	ctz	w1, w0
+  58:	5ac01900 	ctz	w0, w8
+  5c:	5ac018be 	ctz	w30, w5
+  60:	5ac01bc4 	ctz	w4, w30
+  64:	dac01800 	ctz	x0, x0
+  68:	dac01801 	ctz	x1, x0
+  6c:	dac01900 	ctz	x0, x8
+  70:	dac018be 	ctz	x30, x5
+  74:	dac01bc4 	ctz	x4, x30
+  78:	1ac06000 	smax	w0, w0, w0
+  7c:	1ac06001 	smax	w1, w0, w0
+  80:	1ac06020 	smax	w0, w1, w0
+  84:	1ac16000 	smax	w0, w0, w1
+  88:	1ac46043 	smax	w3, w2, w4
+  8c:	1ac0601e 	smax	w30, w0, w0
+  90:	1ac063c0 	smax	w0, w30, w0
+  94:	1ade6000 	smax	w0, w0, w30
+  98:	1adc60ee 	smax	w14, w7, w28
+  9c:	9ac06000 	smax	x0, x0, x0
+  a0:	9ac06001 	smax	x1, x0, x0
+  a4:	9ac06020 	smax	x0, x1, x0
+  a8:	9ac16000 	smax	x0, x0, x1
+  ac:	9ac46043 	smax	x3, x2, x4
+  b0:	9ac0601e 	smax	x30, x0, x0
+  b4:	9ac063c0 	smax	x0, x30, x0
+  b8:	9ade6000 	smax	x0, x0, x30
+  bc:	9adc60ee 	smax	x14, x7, x28
+  c0:	1ac06400 	umax	w0, w0, w0
+  c4:	1ac06401 	umax	w1, w0, w0
+  c8:	1ac06420 	umax	w0, w1, w0
+  cc:	1ac16400 	umax	w0, w0, w1
+  d0:	1ac46443 	umax	w3, w2, w4
+  d4:	1ac0641e 	umax	w30, w0, w0
+  d8:	1ac067c0 	umax	w0, w30, w0
+  dc:	1ade6400 	umax	w0, w0, w30
+  e0:	1adc64ee 	umax	w14, w7, w28
+  e4:	9ac06400 	umax	x0, x0, x0
+  e8:	9ac06401 	umax	x1, x0, x0
+  ec:	9ac06420 	umax	x0, x1, x0
+  f0:	9ac16400 	umax	x0, x0, x1
+  f4:	9ac46443 	umax	x3, x2, x4
+  f8:	9ac0641e 	umax	x30, x0, x0
+  fc:	9ac067c0 	umax	x0, x30, x0
+ 100:	9ade6400 	umax	x0, x0, x30
+ 104:	9adc64ee 	umax	x14, x7, x28
+ 108:	1ac06800 	smin	w0, w0, w0
+ 10c:	1ac06801 	smin	w1, w0, w0
+ 110:	1ac06820 	smin	w0, w1, w0
+ 114:	1ac16800 	smin	w0, w0, w1
+ 118:	1ac46843 	smin	w3, w2, w4
+ 11c:	1ac0681e 	smin	w30, w0, w0
+ 120:	1ac06bc0 	smin	w0, w30, w0
+ 124:	1ade6800 	smin	w0, w0, w30
+ 128:	1adc68ee 	smin	w14, w7, w28
+ 12c:	9ac06800 	smin	x0, x0, x0
+ 130:	9ac06801 	smin	x1, x0, x0
+ 134:	9ac06820 	smin	x0, x1, x0
+ 138:	9ac16800 	smin	x0, x0, x1
+ 13c:	9ac46843 	smin	x3, x2, x4
+ 140:	9ac0681e 	smin	x30, x0, x0
+ 144:	9ac06bc0 	smin	x0, x30, x0
+ 148:	9ade6800 	smin	x0, x0, x30
+ 14c:	9adc68ee 	smin	x14, x7, x28
+ 150:	1ac06c00 	umin	w0, w0, w0
+ 154:	1ac06c01 	umin	w1, w0, w0
+ 158:	1ac06c20 	umin	w0, w1, w0
+ 15c:	1ac16c00 	umin	w0, w0, w1
+ 160:	1ac46c43 	umin	w3, w2, w4
+ 164:	1ac06c1e 	umin	w30, w0, w0
+ 168:	1ac06fc0 	umin	w0, w30, w0
+ 16c:	1ade6c00 	umin	w0, w0, w30
+ 170:	1adc6cee 	umin	w14, w7, w28
+ 174:	9ac06c00 	umin	x0, x0, x0
+ 178:	9ac06c01 	umin	x1, x0, x0
+ 17c:	9ac06c20 	umin	x0, x1, x0
+ 180:	9ac16c00 	umin	x0, x0, x1
+ 184:	9ac46c43 	umin	x3, x2, x4
+ 188:	9ac06c1e 	umin	x30, x0, x0
+ 18c:	9ac06fc0 	umin	x0, x30, x0
+ 190:	9ade6c00 	umin	x0, x0, x30
+ 194:	9adc6cee 	umin	x14, x7, x28
+ 198:	11c00000 	smax	w0, w0, #0
+ 19c:	11c00001 	smax	w1, w0, #0
+ 1a0:	11c00020 	smax	w0, w1, #0
+ 1a4:	11c00400 	smax	w0, w0, #1
+ 1a8:	11c38102 	smax	w2, w8, #-32
+ 1ac:	11c2034d 	smax	w13, w26, #-128
+ 1b0:	11c1fd31 	smax	w17, w9, #127
+ 1b4:	91c00000 	smax	x0, x0, #0
+ 1b8:	91c00001 	smax	x1, x0, #0
+ 1bc:	91c00020 	smax	x0, x1, #0
+ 1c0:	91c00400 	smax	x0, x0, #1
+ 1c4:	91c38102 	smax	x2, x8, #-32
+ 1c8:	91c2034d 	smax	x13, x26, #-128
+ 1cc:	91c1fd31 	smax	x17, x9, #127
+ 1d0:	11c40000 	umax	w0, w0, #0
+ 1d4:	11c40001 	umax	w1, w0, #0
+ 1d8:	11c40020 	umax	w0, w1, #0
+ 1dc:	11c40400 	umax	w0, w0, #1
+ 1e0:	11c48902 	umax	w2, w8, #34
+ 1e4:	11c6034d 	umax	w13, w26, #128
+ 1e8:	11c7fd31 	umax	w17, w9, #255
+ 1ec:	91c40000 	umax	x0, x0, #0
+ 1f0:	91c40001 	umax	x1, x0, #0
+ 1f4:	91c40020 	umax	x0, x1, #0
+ 1f8:	91c40400 	umax	x0, x0, #1
+ 1fc:	91c48902 	umax	x2, x8, #34
+ 200:	91c6034d 	umax	x13, x26, #128
+ 204:	91c7fd31 	umax	x17, x9, #255
+ 208:	11c80000 	smin	w0, w0, #0
+ 20c:	11c80001 	smin	w1, w0, #0
+ 210:	11c80020 	smin	w0, w1, #0
+ 214:	11c80400 	smin	w0, w0, #1
+ 218:	11cb8102 	smin	w2, w8, #-32
+ 21c:	11ca034d 	smin	w13, w26, #-128
+ 220:	11c9fd31 	smin	w17, w9, #127
+ 224:	91c80000 	smin	x0, x0, #0
+ 228:	91c80001 	smin	x1, x0, #0
+ 22c:	91c80020 	smin	x0, x1, #0
+ 230:	91c80400 	smin	x0, x0, #1
+ 234:	91cb8102 	smin	x2, x8, #-32
+ 238:	91ca034d 	smin	x13, x26, #-128
+ 23c:	91c9fd31 	smin	x17, x9, #127
+ 240:	11cc0000 	umin	w0, w0, #0
+ 244:	11cc0001 	umin	w1, w0, #0
+ 248:	11cc0020 	umin	w0, w1, #0
+ 24c:	11cc0400 	umin	w0, w0, #1
+ 250:	11cc8902 	umin	w2, w8, #34
+ 254:	11ce034d 	umin	w13, w26, #128
+ 258:	11cffd31 	umin	w17, w9, #255
+ 25c:	91cc0000 	umin	x0, x0, #0
+ 260:	91cc0001 	umin	x1, x0, #0
+ 264:	91cc0020 	umin	x0, x1, #0
+ 268:	91cc0400 	umin	x0, x0, #1
+ 26c:	91cc8902 	umin	x2, x8, #34
+ 270:	91ce034d 	umin	x13, x26, #128
+ 274:	91cffd31 	umin	x17, x9, #255
diff --git a/gas/testsuite/gas/aarch64/cssc.s b/gas/testsuite/gas/aarch64/cssc.s
new file mode 100644
index 0000000000000000000000000000000000000000..6ba6b57c4023c050f1e2cc407c357e215f89edca
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cssc.s
@@ -0,0 +1,160 @@
+/* Common Short Sequence Compression instructions.  */
+abs w0, w0
+abs w1, w0
+abs w0, w8
+abs w30, w5
+abs w4, w30
+abs x0, x0
+abs x1, x0
+abs x0, x8
+abs x30, x5
+abs x4, x30
+cnt w0, w0
+cnt w1, w0
+cnt w0, w8
+cnt w30, w5
+cnt w4, w30
+cnt x0, x0
+cnt x1, x0
+cnt x0, x8
+cnt x30, x5
+cnt x4, x30
+ctz w0, w0
+ctz w1, w0
+ctz w0, w8
+ctz w30, w5
+ctz w4, w30
+ctz x0, x0
+ctz x1, x0
+ctz x0, x8
+ctz x30, x5
+ctz x4, x30
+smax w0, w0, w0
+smax w1, w0, w0
+smax w0, w1, w0
+smax w0, w0, w1
+smax w3, w2, w4
+smax w30, w0, w0
+smax w0, w30, w0
+smax w0, w0, w30
+smax w14, w7, w28
+smax x0, x0, x0
+smax x1, x0, x0
+smax x0, x1, x0
+smax x0, x0, x1
+smax x3, x2, x4
+smax x30, x0, x0
+smax x0, x30, x0
+smax x0, x0, x30
+smax x14, x7, x28
+umax w0, w0, w0
+umax w1, w0, w0
+umax w0, w1, w0
+umax w0, w0, w1
+umax w3, w2, w4
+umax w30, w0, w0
+umax w0, w30, w0
+umax w0, w0, w30
+umax w14, w7, w28
+umax x0, x0, x0
+umax x1, x0, x0
+umax x0, x1, x0
+umax x0, x0, x1
+umax x3, x2, x4
+umax x30, x0, x0
+umax x0, x30, x0
+umax x0, x0, x30
+umax x14, x7, x28
+smin w0, w0, w0
+smin w1, w0, w0
+smin w0, w1, w0
+smin w0, w0, w1
+smin w3, w2, w4
+smin w30, w0, w0
+smin w0, w30, w0
+smin w0, w0, w30
+smin w14, w7, w28
+smin x0, x0, x0
+smin x1, x0, x0
+smin x0, x1, x0
+smin x0, x0, x1
+smin x3, x2, x4
+smin x30, x0, x0
+smin x0, x30, x0
+smin x0, x0, x30
+smin x14, x7, x28
+umin w0, w0, w0
+umin w1, w0, w0
+umin w0, w1, w0
+umin w0, w0, w1
+umin w3, w2, w4
+umin w30, w0, w0
+umin w0, w30, w0
+umin w0, w0, w30
+umin w14, w7, w28
+umin x0, x0, x0
+umin x1, x0, x0
+umin x0, x1, x0
+umin x0, x0, x1
+umin x3, x2, x4
+umin x30, x0, x0
+umin x0, x30, x0
+umin x0, x0, x30
+umin x14, x7, x28
+smax w0, w0, #0
+smax w1, w0, #0
+smax w0, w1, #0
+smax w0, w0, #1
+smax w2, w8, #-32
+smax w13, w26, #-128
+smax w17, w9, #127
+smax x0, x0, #0
+smax x1, x0, #0
+smax x0, x1, #0
+smax x0, x0, #1
+smax x2, x8, #-32
+smax x13, x26, #-128
+smax x17, x9, #127
+umax w0, w0, #0
+umax w1, w0, #0
+umax w0, w1, #0
+umax w0, w0, #1
+umax w2, w8, #34
+umax w13, w26, #128
+umax w17, w9, #255
+umax x0, x0, #0
+umax x1, x0, #0
+umax x0, x1, #0
+umax x0, x0, #1
+umax x2, x8, #34
+umax x13, x26, #128
+umax x17, x9, #255
+smin w0, w0, #0
+smin w1, w0, #0
+smin w0, w1, #0
+smin w0, w0, #1
+smin w2, w8, #-32
+smin w13, w26, #-128
+smin w17, w9, #127
+smin x0, x0, #0
+smin x1, x0, #0
+smin x0, x1, #0
+smin x0, x0, #1
+smin x2, x8, #-32
+smin x13, x26, #-128
+smin x17, x9, #127
+umin w0, w0, #0
+umin w1, w0, #0
+umin w0, w1, #0
+umin w0, w0, #1
+umin w2, w8, #34
+umin w13, w26, #128
+umin w17, w9, #255
+umin x0, x0, #0
+umin x1, x0, #0
+umin x0, x1, #0
+umin x0, x0, #1
+umin x2, x8, #34
+umin x13, x26, #128
+umin x17, x9, #255
+
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9477ac98f3b5208f24ec2fde7cb2e3a56c56b618..838d4239741ea4df2775c05f58165684387957d2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -99,6 +99,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_SME_F64	     (1ULL << 57) /* SME F64.  */
 #define AARCH64_FEATURE_SME_I64	     (1ULL << 58) /* SME I64.  */
 #define AARCH64_FEATURE_V8_8	     (1ULL << 59) /* Armv8.8 processors.  */
+#define AARCH64_FEATURE_CSSC	     (1ULL << 60) /* Common Short Sequence Compression instructions.  */
 
 /* Crypto instructions are the combination of AES and SHA2.  */
 #define AARCH64_FEATURE_CRYPTO	(AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
@@ -492,7 +493,9 @@ enum aarch64_opnd
   AARCH64_OPND_SM3_IMM2,	/* SM3 encodes lane in bits [13, 14].  */
   AARCH64_OPND_MOPS_ADDR_Rd,	/* [Rd]!, in bits [0, 4].  */
   AARCH64_OPND_MOPS_ADDR_Rs,	/* [Rs]!, in bits [16, 20].  */
-  AARCH64_OPND_MOPS_WB_Rn	/* Rn!, in bits [5, 9].  */
+  AARCH64_OPND_MOPS_WB_Rn,	/* Rn!, in bits [5, 9].  */
+  AARCH64_OPND_CSSC_SIMM8,	/* CSSC signed 8-bit immediate.  */
+  AARCH64_OPND_CSSC_UIMM8,	/* CSSC unsigned 8-bit immediate.  */
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an
@@ -684,6 +687,7 @@ enum aarch64_insn_class
   cryptosm4,
   dotproduct,
   bfloat16,
+  cssc,
 };
 
 /* Opcode enumerators.  */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 38bc5d7cfa6be6c60c96ef58e355527b3d372400..23c4e81736843cfe3e5266ba79b41a1cd10718cb 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -723,6 +723,8 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 190:
     case 215:
     case 221:
+    case 226:
+    case 227:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 44:
     case 45:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 69a157899473978b459afce84dd925e7465a8d4b..318b0717c39faf3e78f3ad470143b36ac257ecee 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -4201,21 +4201,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                                 }
                                               else
                                                 {
-                                                  if (((word >> 30) & 0x1) == 0)
+                                                  if (((word >> 14) & 0x1) == 0)
                                                     {
-                                                      /* 33222222222211111111110000000000
-                                                         10987654321098765432109876543210
-                                                         x0x11010110xxxxxxx1000xxxxxxxxxx
-                                                         lslv.  */
-                                                      return 713;
+                                                      if (((word >> 30) & 0x1) == 0)
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             x0x11010110xxxxxx01000xxxxxxxxxx
+                                                             lslv.  */
+                                                          return 713;
+                                                        }
+                                                      else
+                                                        {
+                                                          if (((word >> 16) & 0x1) == 0)
+                                                            {
+                                                              /* 33222222222211111111110000000000
+                                                                 10987654321098765432109876543210
+                                                                 x1x11010110xxxx0x01000xxxxxxxxxx
+                                                                 abs.  */
+                                                              return 2640;
+                                                            }
+                                                          else
+                                                            {
+                                                              /* 33222222222211111111110000000000
+                                                                 10987654321098765432109876543210
+                                                                 x1x11010110xxxx1x01000xxxxxxxxxx
+                                                                 paciza.  */
+                                                              return 701;
+                                                            }
+                                                        }
                                                     }
                                                   else
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x1x11010110xxxxxxx1000xxxxxxxxxx
-                                                         paciza.  */
-                                                      return 701;
+                                                         xxx11010110xxxxxx11000xxxxxxxxxx
+                                                         smax.  */
+                                                      return 2643;
                                                     }
                                                 }
                                             }
@@ -4385,21 +4407,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                                 }
                                               else
                                                 {
-                                                  if (((word >> 30) & 0x1) == 0)
+                                                  if (((word >> 14) & 0x1) == 0)
                                                     {
-                                                      /* 33222222222211111111110000000000
-                                                         10987654321098765432109876543210
-                                                         x0x11010110xxxxxxx1010xxxxxxxxxx
-                                                         asrv.  */
-                                                      return 717;
+                                                      if (((word >> 30) & 0x1) == 0)
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             x0x11010110xxxxxx01010xxxxxxxxxx
+                                                             asrv.  */
+                                                          return 717;
+                                                        }
+                                                      else
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             x1x11010110xxxxxx01010xxxxxxxxxx
+                                                             pacdza.  */
+                                                          return 703;
+                                                        }
                                                     }
                                                   else
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x1x11010110xxxxxxx1010xxxxxxxxxx
-                                                         pacdza.  */
-                                                      return 703;
+                                                         xxx11010110xxxxxx11010xxxxxxxxxx
+                                                         smin.  */
+                                                      return 2645;
                                                     }
                                                 }
                                             }
@@ -4409,11 +4442,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                                 {
                                                   if (((word >> 14) & 0x1) == 0)
                                                     {
-                                                      /* 33222222222211111111110000000000
-                                                         10987654321098765432109876543210
-                                                         xxx11010110xxxxxx00110xxxxxxxxxx
-                                                         autda.  */
-                                                      return 699;
+                                                      if (((word >> 16) & 0x1) == 0)
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             xxx11010110xxxx0x00110xxxxxxxxxx
+                                                             ctz.  */
+                                                          return 2642;
+                                                        }
+                                                      else
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             xxx11010110xxxx1x00110xxxxxxxxxx
+                                                             autda.  */
+                                                          return 699;
+                                                        }
                                                     }
                                                   else
                                                     {
@@ -4518,21 +4562,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                             }
                                           else
                                             {
-                                              if (((word >> 30) & 0x1) == 0)
+                                              if (((word >> 14) & 0x1) == 0)
                                                 {
-                                                  /* 33222222222211111111110000000000
-                                                     10987654321098765432109876543210
-                                                     x0x11010x10xxxxxxx1001xxxxxxxxxx
-                                                     lsrv.  */
-                                                  return 715;
+                                                  if (((word >> 30) & 0x1) == 0)
+                                                    {
+                                                      /* 33222222222211111111110000000000
+                                                         10987654321098765432109876543210
+                                                         x0x11010x10xxxxxx01001xxxxxxxxxx
+                                                         lsrv.  */
+                                                      return 715;
+                                                    }
+                                                  else
+                                                    {
+                                                      /* 33222222222211111111110000000000
+                                                         10987654321098765432109876543210
+                                                         x1x11010x10xxxxxx01001xxxxxxxxxx
+                                                         pacizb.  */
+                                                      return 702;
+                                                    }
                                                 }
                                               else
                                                 {
                                                   /* 33222222222211111111110000000000
                                                      10987654321098765432109876543210
-                                                     x1x11010x10xxxxxxx1001xxxxxxxxxx
-                                                     pacizb.  */
-                                                  return 702;
+                                                     xxx11010x10xxxxxx11001xxxxxxxxxx
+                                                     umax.  */
+                                                  return 2644;
                                                 }
                                             }
                                         }
@@ -4637,21 +4692,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                         }
                                       else
                                         {
-                                          if (((word >> 30) & 0x1) == 0)
+                                          if (((word >> 14) & 0x1) == 0)
                                             {
-                                              /* 33222222222211111111110000000000
-                                                 10987654321098765432109876543210
-                                                 x0x11010xx0xxxxxxx1011xxxxxxxxxx
-                                                 rorv.  */
-                                              return 719;
+                                              if (((word >> 30) & 0x1) == 0)
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     x0x11010xx0xxxxxx01011xxxxxxxxxx
+                                                     rorv.  */
+                                                  return 719;
+                                                }
+                                              else
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     x1x11010xx0xxxxxx01011xxxxxxxxxx
+                                                     pacdzb.  */
+                                                  return 704;
+                                                }
                                             }
                                           else
                                             {
                                               /* 33222222222211111111110000000000
                                                  10987654321098765432109876543210
-                                                 x1x11010xx0xxxxxxx1011xxxxxxxxxx
-                                                 pacdzb.  */
-                                              return 704;
+                                                 xxx11010xx0xxxxxx11011xxxxxxxxxx
+                                                 umin.  */
+                                              return 2646;
                                             }
                                         }
                                     }
@@ -4661,11 +4727,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                         {
                                           if (((word >> 14) & 0x1) == 0)
                                             {
-                                              /* 33222222222211111111110000000000
-                                                 10987654321098765432109876543210
-                                                 xxx11010xx0xxxxxx00111xxxxxxxxxx
-                                                 autdb.  */
-                                              return 700;
+                                              if (((word >> 16) & 0x1) == 0)
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     xxx11010xx0xxxx0x00111xxxxxxxxxx
+                                                     cnt.  */
+                                                  return 2641;
+                                                }
+                                              else
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     xxx11010xx0xxxx1x00111xxxxxxxxxx
+                                                     autdb.  */
+                                                  return 700;
+                                                }
                                             }
                                           else
                                             {
@@ -25111,7 +25188,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
     case 2403: value = 2408; break;	/* st1q --> st1q.  */
     case 2408: return NULL;		/* st1q --> NULL.  */
     case 12: value = 19; break;	/* add --> addg.  */
-    case 19: return NULL;		/* addg --> NULL.  */
+    case 19: value = 2636; break;	/* addg --> smax.  */
+    case 2636: value = 2637; break;	/* smax --> umax.  */
+    case 2637: value = 2638; break;	/* umax --> smin.  */
+    case 2638: value = 2639; break;	/* smin --> umin.  */
+    case 2639: return NULL;		/* umin --> NULL.  */
     case 16: value = 20; break;	/* sub --> subg.  */
     case 20: return NULL;		/* subg --> NULL.  */
     case 971: value = 975; break;	/* stnp --> stp.  */
@@ -25830,6 +25911,8 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 190:
     case 215:
     case 221:
+    case 226:
+    case 227:
       return aarch64_ext_imm (self, info, code, inst, errors);
     case 44:
     case 45:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index a6ef7097a67f11b44a4d6eea777c80de51993b2c..b680225917efb408afd2c8f7f18ada3048900e6f 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -250,6 +250,8 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
 };
 
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 126565dca14080b3f1370de7dd42cbc1de90c926..b61e8eb96a8a2d8524a69527553d66c0aef69d15 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -168,7 +168,8 @@ enum aarch64_field_kind
   FLD_rotate3,
   FLD_SM3_imm2,
   FLD_sz,
-  FLD_CRm_dsb_nxs
+  FLD_CRm_dsb_nxs,
+  FLD_CSSC_imm8
 };
 
 /* Field description.  */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a2882bdfaba43d2b6beacf75f9f1a76d01fbe934..dd888b332c9665ecf654c0e81d495a89fa57dca6 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -342,6 +342,7 @@ const aarch64_field fields[] =
     { 12,  2 }, /* SM3: Indexed element SM3 2 bits index immediate.  */
     { 22,  1 }, /* sz: 1-bit element size select.  */
     { 10,  2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>.  */
+    { 10,  8 }, /* CSSC_imm8.  */
 };
 
 enum aarch64_operand_class
@@ -2176,6 +2177,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	case AARCH64_OPND_SVE_UIMM7:
 	case AARCH64_OPND_SVE_UIMM8:
 	case AARCH64_OPND_SVE_UIMM8_53:
+	case AARCH64_OPND_CSSC_UIMM8:
 	  size = get_operand_fields_width (get_operand_from_code (type));
 	  assert (size < 32);
 	  if (!value_fit_unsigned_field_p (opnd->imm.value, size))
@@ -2206,6 +2208,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	case AARCH64_OPND_SVE_SIMM5B:
 	case AARCH64_OPND_SVE_SIMM6:
 	case AARCH64_OPND_SVE_SIMM8:
+	case AARCH64_OPND_CSSC_SIMM8:
 	  size = get_operand_fields_width (get_operand_from_code (type));
 	  assert (size < 32);
 	  if (!value_fit_signed_field_p (opnd->imm.value, size))
@@ -3620,6 +3623,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SVE_IMM_ROT1:
     case AARCH64_OPND_SVE_IMM_ROT2:
     case AARCH64_OPND_SVE_IMM_ROT3:
+    case AARCH64_OPND_CSSC_SIMM8:
+    case AARCH64_OPND_CSSC_UIMM8:
       snprintf (buf, size, "%s",
 		style_imm (styler, "#%" PRIi64, opnd->imm.value));
       break;
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index adcc2fe00916263b7c867af001420122fb51f11a..541fdc2d41e148edb7378f019d81fe6fad9fbb1d 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2508,6 +2508,8 @@ static const aarch64_feature_set aarch64_feature_mops_memtag =
   AARCH64_FEATURE (AARCH64_FEATURE_MOPS | AARCH64_FEATURE_MEMTAG, 0);
 static const aarch64_feature_set aarch64_feature_hbc =
   AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0);
+static const aarch64_feature_set aarch64_feature_cssc =
+  AARCH64_FEATURE (AARCH64_FEATURE_CSSC, 0);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -2562,6 +2564,7 @@ static const aarch64_feature_set aarch64_feature_hbc =
 #define MOPS	  &aarch64_feature_mops
 #define MOPS_MEMTAG &aarch64_feature_mops_memtag
 #define HBC	  &aarch64_feature_hbc
+#define CSSC	  &aarch64_feature_cssc
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2695,6 +2698,8 @@ static const aarch64_feature_set aarch64_feature_hbc =
     CONSTRAINTS, 0, VERIFIER }
 #define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL }
 
 #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
   MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -5437,6 +5442,21 @@ const struct aarch64_opcode aarch64_opcode_table[] =
 
   HBC_INSN ("bc.c", 0x54000010, 0xff000010, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND),
 
+/* CSSC with immediates.  */
+  CSSC_INSN ("smax", 0x11c00000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_SIMM8), QL_R2NIL, F_SF),
+  CSSC_INSN ("umax", 0x11c40000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_UIMM8), QL_R2NIL, F_SF),
+  CSSC_INSN ("smin", 0x11c80000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_SIMM8), QL_R2NIL, F_SF),
+  CSSC_INSN ("umin", 0x11cc0000, 0x7ffc0000, OP3 (Rd, Rn, CSSC_UIMM8), QL_R2NIL, F_SF),
+
+/* CSSC with registers only.  */
+  CSSC_INSN ("abs",  0x5ac02000, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+  CSSC_INSN ("cnt",  0x5ac01c00, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+  CSSC_INSN ("ctz",  0x5ac01800, 0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+  CSSC_INSN ("smax", 0x1ac06000, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+  CSSC_INSN ("umax", 0x1ac06400, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+  CSSC_INSN ("smin", 0x1ac06800, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+  CSSC_INSN ("umin", 0x1ac06c00, 0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };
 
@@ -5928,4 +5948,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
     Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD_Rs),			\
       "a register source address with writeback")			\
     Y(INT_REG, x0_to_x30, "MOPS_WB_Rd", 0, F(FLD_Rn),			\
-      "an integer register with writeback")
+      "an integer register with writeback")				\
+    Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8),	\
+      "an 8-bit signed immediate")					\
+    Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8),		\
+      "an 8-bit unsigned immediate")
  
Andre Vieira (lists) Nov. 11, 2022, 9:02 a.m. UTC | #6
Ping
On 07/11/2022 09:47, Andre Vieira (lists) via Binutils wrote:
> Fixed the whitespace typo.
>
> On 31/10/2022 16:33, Andre Vieira (lists) via Binutils wrote:
>>
>> On 31/10/2022 13:40, Jan Beulich wrote:
>>> On 31.10.2022 12:45, Andre Vieira (lists) wrote:
>>>> They are in the Arm A-profile A64 Instruction Set document on
>>>> developer.arm.com. I don't know if this link is a permanent one, 
>>>> but for
>>>> now
>>>> https://documentation-service.arm.com/static/633d9270da191e7fe057eb97
>>>> should work.
>>>> If you look for FEAT_CSSC in that document you will find the relevant
>>>> instructions and their encoding.
>>> Thanks. One minor remark on the patch itself as I was looking over it:
>>> All new aarch64_opcode_table[] entries look to have their 2nd commas
>>> slightly misplaced.
>>>
>>> Jan
>> Yeah you are right, I'll fix that before committing, if it gets 
>> accepted without any other comments that is.
>>
>> Thanks,
>> Andre
  
Nick Clifton Nov. 14, 2022, 1:44 p.m. UTC | #7
Hi Andre,

> Ping

Oops, sorry...

>> Fixed the whitespace typo.

Patch approved - please apply.

Cheers
   Nick
  

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index f6fa15858325954ec9c3b86fb948b939b9227c29..165d9278ce78fae3cc7357c0ad88378a9f494470 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6636,6 +6636,8 @@  parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_IMM_ROT1:
 	case AARCH64_OPND_SVE_IMM_ROT2:
 	case AARCH64_OPND_SVE_IMM_ROT3:
+	case AARCH64_OPND_CSSC_SIMM8:
+	case AARCH64_OPND_CSSC_UIMM8:
 	  po_imm_nc_or_fail ();
 	  info->imm.value = val;
 	  break;
@@ -10041,6 +10043,8 @@  static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_ARCH_NONE},
   {"hbc",		AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0),
 			AARCH64_ARCH_NONE},
+  {"cssc",		AARCH64_FEATURE (AARCH64_FEATURE_CSSC, 0),
+			AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 0809310a9a3b3c1776bc62417865e691080bd251..eee3a4bd95bd8d06ec9297e5b0111b8e9107d7cc 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -186,6 +186,8 @@  automatically cause those extensions to be disabled.
  @tab Enable floating-point extensions.
 @item @code{hbc} @tab @tab Armv8.8-A or later
  @tab Enable Armv8.8-A hinted conditional branch instructions
+@item @code{cssc} @tab @tab Armv8.7-A or later
+ @tab Enable Armv8.9-A Common Short Sequence Compression instructions.
 @item @code{i8mm} @tab ARMv8.2-A @tab ARMv8.6-A or later
  @tab Enable Int8 Matrix Multiply extension.
 @item @code{lor} @tab ARMv8-A @tab ARMv8.1-A or later
diff --git a/gas/testsuite/gas/aarch64/cssc.d b/gas/testsuite/gas/aarch64/cssc.d
new file mode 100644
index 0000000000000000000000000000000000000000..4741b6584f658b0cd2dfa5f9256f94e4d14455c6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cssc.d
@@ -0,0 +1,174 @@ 
+#name: CSSC extension
+#as: -march=armv8-a+cssc
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+
+a.out:     file format elf64-littleaarch64
+
+
+Disassembly of section .text:
+
+0000000000000000 <.text>:
+   0:	5ac02000 	abs	w0, w0
+   4:	5ac02001 	abs	w1, w0
+   8:	5ac02100 	abs	w0, w8
+   c:	5ac020be 	abs	w30, w5
+  10:	5ac023c4 	abs	w4, w30
+  14:	dac02000 	abs	x0, x0
+  18:	dac02001 	abs	x1, x0
+  1c:	dac02100 	abs	x0, x8
+  20:	dac020be 	abs	x30, x5
+  24:	dac023c4 	abs	x4, x30
+  28:	5ac01c00 	cnt	w0, w0
+  2c:	5ac01c01 	cnt	w1, w0
+  30:	5ac01d00 	cnt	w0, w8
+  34:	5ac01cbe 	cnt	w30, w5
+  38:	5ac01fc4 	cnt	w4, w30
+  3c:	dac01c00 	cnt	x0, x0
+  40:	dac01c01 	cnt	x1, x0
+  44:	dac01d00 	cnt	x0, x8
+  48:	dac01cbe 	cnt	x30, x5
+  4c:	dac01fc4 	cnt	x4, x30
+  50:	5ac01800 	ctz	w0, w0
+  54:	5ac01801 	ctz	w1, w0
+  58:	5ac01900 	ctz	w0, w8
+  5c:	5ac018be 	ctz	w30, w5
+  60:	5ac01bc4 	ctz	w4, w30
+  64:	dac01800 	ctz	x0, x0
+  68:	dac01801 	ctz	x1, x0
+  6c:	dac01900 	ctz	x0, x8
+  70:	dac018be 	ctz	x30, x5
+  74:	dac01bc4 	ctz	x4, x30
+  78:	1ac06000 	smax	w0, w0, w0
+  7c:	1ac06001 	smax	w1, w0, w0
+  80:	1ac06020 	smax	w0, w1, w0
+  84:	1ac16000 	smax	w0, w0, w1
+  88:	1ac46043 	smax	w3, w2, w4
+  8c:	1ac0601e 	smax	w30, w0, w0
+  90:	1ac063c0 	smax	w0, w30, w0
+  94:	1ade6000 	smax	w0, w0, w30
+  98:	1adc60ee 	smax	w14, w7, w28
+  9c:	9ac06000 	smax	x0, x0, x0
+  a0:	9ac06001 	smax	x1, x0, x0
+  a4:	9ac06020 	smax	x0, x1, x0
+  a8:	9ac16000 	smax	x0, x0, x1
+  ac:	9ac46043 	smax	x3, x2, x4
+  b0:	9ac0601e 	smax	x30, x0, x0
+  b4:	9ac063c0 	smax	x0, x30, x0
+  b8:	9ade6000 	smax	x0, x0, x30
+  bc:	9adc60ee 	smax	x14, x7, x28
+  c0:	1ac06400 	umax	w0, w0, w0
+  c4:	1ac06401 	umax	w1, w0, w0
+  c8:	1ac06420 	umax	w0, w1, w0
+  cc:	1ac16400 	umax	w0, w0, w1
+  d0:	1ac46443 	umax	w3, w2, w4
+  d4:	1ac0641e 	umax	w30, w0, w0
+  d8:	1ac067c0 	umax	w0, w30, w0
+  dc:	1ade6400 	umax	w0, w0, w30
+  e0:	1adc64ee 	umax	w14, w7, w28
+  e4:	9ac06400 	umax	x0, x0, x0
+  e8:	9ac06401 	umax	x1, x0, x0
+  ec:	9ac06420 	umax	x0, x1, x0
+  f0:	9ac16400 	umax	x0, x0, x1
+  f4:	9ac46443 	umax	x3, x2, x4
+  f8:	9ac0641e 	umax	x30, x0, x0
+  fc:	9ac067c0 	umax	x0, x30, x0
+ 100:	9ade6400 	umax	x0, x0, x30
+ 104:	9adc64ee 	umax	x14, x7, x28
+ 108:	1ac06800 	smin	w0, w0, w0
+ 10c:	1ac06801 	smin	w1, w0, w0
+ 110:	1ac06820 	smin	w0, w1, w0
+ 114:	1ac16800 	smin	w0, w0, w1
+ 118:	1ac46843 	smin	w3, w2, w4
+ 11c:	1ac0681e 	smin	w30, w0, w0
+ 120:	1ac06bc0 	smin	w0, w30, w0
+ 124:	1ade6800 	smin	w0, w0, w30
+ 128:	1adc68ee 	smin	w14, w7, w28
+ 12c:	9ac06800 	smin	x0, x0, x0
+ 130:	9ac06801 	smin	x1, x0, x0
+ 134:	9ac06820 	smin	x0, x1, x0
+ 138:	9ac16800 	smin	x0, x0, x1
+ 13c:	9ac46843 	smin	x3, x2, x4
+ 140:	9ac0681e 	smin	x30, x0, x0
+ 144:	9ac06bc0 	smin	x0, x30, x0
+ 148:	9ade6800 	smin	x0, x0, x30
+ 14c:	9adc68ee 	smin	x14, x7, x28
+ 150:	1ac06c00 	umin	w0, w0, w0
+ 154:	1ac06c01 	umin	w1, w0, w0
+ 158:	1ac06c20 	umin	w0, w1, w0
+ 15c:	1ac16c00 	umin	w0, w0, w1
+ 160:	1ac46c43 	umin	w3, w2, w4
+ 164:	1ac06c1e 	umin	w30, w0, w0
+ 168:	1ac06fc0 	umin	w0, w30, w0
+ 16c:	1ade6c00 	umin	w0, w0, w30
+ 170:	1adc6cee 	umin	w14, w7, w28
+ 174:	9ac06c00 	umin	x0, x0, x0
+ 178:	9ac06c01 	umin	x1, x0, x0
+ 17c:	9ac06c20 	umin	x0, x1, x0
+ 180:	9ac16c00 	umin	x0, x0, x1
+ 184:	9ac46c43 	umin	x3, x2, x4
+ 188:	9ac06c1e 	umin	x30, x0, x0
+ 18c:	9ac06fc0 	umin	x0, x30, x0
+ 190:	9ade6c00 	umin	x0, x0, x30
+ 194:	9adc6cee 	umin	x14, x7, x28
+ 198:	11c00000 	smax	w0, w0, #0
+ 19c:	11c00001 	smax	w1, w0, #0
+ 1a0:	11c00020 	smax	w0, w1, #0
+ 1a4:	11c00400 	smax	w0, w0, #1
+ 1a8:	11c38102 	smax	w2, w8, #-32
+ 1ac:	11c2034d 	smax	w13, w26, #-128
+ 1b0:	11c1fd31 	smax	w17, w9, #127
+ 1b4:	91c00000 	smax	x0, x0, #0
+ 1b8:	91c00001 	smax	x1, x0, #0
+ 1bc:	91c00020 	smax	x0, x1, #0
+ 1c0:	91c00400 	smax	x0, x0, #1
+ 1c4:	91c38102 	smax	x2, x8, #-32
+ 1c8:	91c2034d 	smax	x13, x26, #-128
+ 1cc:	91c1fd31 	smax	x17, x9, #127
+ 1d0:	11c40000 	umax	w0, w0, #0
+ 1d4:	11c40001 	umax	w1, w0, #0
+ 1d8:	11c40020 	umax	w0, w1, #0
+ 1dc:	11c40400 	umax	w0, w0, #1
+ 1e0:	11c48902 	umax	w2, w8, #34
+ 1e4:	11c6034d 	umax	w13, w26, #128
+ 1e8:	11c7fd31 	umax	w17, w9, #255
+ 1ec:	91c40000 	umax	x0, x0, #0
+ 1f0:	91c40001 	umax	x1, x0, #0
+ 1f4:	91c40020 	umax	x0, x1, #0
+ 1f8:	91c40400 	umax	x0, x0, #1
+ 1fc:	91c48902 	umax	x2, x8, #34
+ 200:	91c6034d 	umax	x13, x26, #128
+ 204:	91c7fd31 	umax	x17, x9, #255
+ 208:	11c80000 	smin	w0, w0, #0
+ 20c:	11c80001 	smin	w1, w0, #0
+ 210:	11c80020 	smin	w0, w1, #0
+ 214:	11c80400 	smin	w0, w0, #1
+ 218:	11cb8102 	smin	w2, w8, #-32
+ 21c:	11ca034d 	smin	w13, w26, #-128
+ 220:	11c9fd31 	smin	w17, w9, #127
+ 224:	91c80000 	smin	x0, x0, #0
+ 228:	91c80001 	smin	x1, x0, #0
+ 22c:	91c80020 	smin	x0, x1, #0
+ 230:	91c80400 	smin	x0, x0, #1
+ 234:	91cb8102 	smin	x2, x8, #-32
+ 238:	91ca034d 	smin	x13, x26, #-128
+ 23c:	91c9fd31 	smin	x17, x9, #127
+ 240:	11cc0000 	umin	w0, w0, #0
+ 244:	11cc0001 	umin	w1, w0, #0
+ 248:	11cc0020 	umin	w0, w1, #0
+ 24c:	11cc0400 	umin	w0, w0, #1
+ 250:	11cc8902 	umin	w2, w8, #34
+ 254:	11ce034d 	umin	w13, w26, #128
+ 258:	11cffd31 	umin	w17, w9, #255
+ 25c:	91cc0000 	umin	x0, x0, #0
+ 260:	91cc0001 	umin	x1, x0, #0
+ 264:	91cc0020 	umin	x0, x1, #0
+ 268:	91cc0400 	umin	x0, x0, #1
+ 26c:	91cc8902 	umin	x2, x8, #34
+ 270:	91ce034d 	umin	x13, x26, #128
+ 274:	91cffd31 	umin	x17, x9, #255
diff --git a/gas/testsuite/gas/aarch64/cssc.s b/gas/testsuite/gas/aarch64/cssc.s
new file mode 100644
index 0000000000000000000000000000000000000000..6ba6b57c4023c050f1e2cc407c357e215f89edca
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/cssc.s
@@ -0,0 +1,160 @@ 
+/* Common Short Sequence Compression instructions.  */
+abs w0, w0
+abs w1, w0
+abs w0, w8
+abs w30, w5
+abs w4, w30
+abs x0, x0
+abs x1, x0
+abs x0, x8
+abs x30, x5
+abs x4, x30
+cnt w0, w0
+cnt w1, w0
+cnt w0, w8
+cnt w30, w5
+cnt w4, w30
+cnt x0, x0
+cnt x1, x0
+cnt x0, x8
+cnt x30, x5
+cnt x4, x30
+ctz w0, w0
+ctz w1, w0
+ctz w0, w8
+ctz w30, w5
+ctz w4, w30
+ctz x0, x0
+ctz x1, x0
+ctz x0, x8
+ctz x30, x5
+ctz x4, x30
+smax w0, w0, w0
+smax w1, w0, w0
+smax w0, w1, w0
+smax w0, w0, w1
+smax w3, w2, w4
+smax w30, w0, w0
+smax w0, w30, w0
+smax w0, w0, w30
+smax w14, w7, w28
+smax x0, x0, x0
+smax x1, x0, x0
+smax x0, x1, x0
+smax x0, x0, x1
+smax x3, x2, x4
+smax x30, x0, x0
+smax x0, x30, x0
+smax x0, x0, x30
+smax x14, x7, x28
+umax w0, w0, w0
+umax w1, w0, w0
+umax w0, w1, w0
+umax w0, w0, w1
+umax w3, w2, w4
+umax w30, w0, w0
+umax w0, w30, w0
+umax w0, w0, w30
+umax w14, w7, w28
+umax x0, x0, x0
+umax x1, x0, x0
+umax x0, x1, x0
+umax x0, x0, x1
+umax x3, x2, x4
+umax x30, x0, x0
+umax x0, x30, x0
+umax x0, x0, x30
+umax x14, x7, x28
+smin w0, w0, w0
+smin w1, w0, w0
+smin w0, w1, w0
+smin w0, w0, w1
+smin w3, w2, w4
+smin w30, w0, w0
+smin w0, w30, w0
+smin w0, w0, w30
+smin w14, w7, w28
+smin x0, x0, x0
+smin x1, x0, x0
+smin x0, x1, x0
+smin x0, x0, x1
+smin x3, x2, x4
+smin x30, x0, x0
+smin x0, x30, x0
+smin x0, x0, x30
+smin x14, x7, x28
+umin w0, w0, w0
+umin w1, w0, w0
+umin w0, w1, w0
+umin w0, w0, w1
+umin w3, w2, w4
+umin w30, w0, w0
+umin w0, w30, w0
+umin w0, w0, w30
+umin w14, w7, w28
+umin x0, x0, x0
+umin x1, x0, x0
+umin x0, x1, x0
+umin x0, x0, x1
+umin x3, x2, x4
+umin x30, x0, x0
+umin x0, x30, x0
+umin x0, x0, x30
+umin x14, x7, x28
+smax w0, w0, #0
+smax w1, w0, #0
+smax w0, w1, #0
+smax w0, w0, #1
+smax w2, w8, #-32
+smax w13, w26, #-128
+smax w17, w9, #127
+smax x0, x0, #0
+smax x1, x0, #0
+smax x0, x1, #0
+smax x0, x0, #1
+smax x2, x8, #-32
+smax x13, x26, #-128
+smax x17, x9, #127
+umax w0, w0, #0
+umax w1, w0, #0
+umax w0, w1, #0
+umax w0, w0, #1
+umax w2, w8, #34
+umax w13, w26, #128
+umax w17, w9, #255
+umax x0, x0, #0
+umax x1, x0, #0
+umax x0, x1, #0
+umax x0, x0, #1
+umax x2, x8, #34
+umax x13, x26, #128
+umax x17, x9, #255
+smin w0, w0, #0
+smin w1, w0, #0
+smin w0, w1, #0
+smin w0, w0, #1
+smin w2, w8, #-32
+smin w13, w26, #-128
+smin w17, w9, #127
+smin x0, x0, #0
+smin x1, x0, #0
+smin x0, x1, #0
+smin x0, x0, #1
+smin x2, x8, #-32
+smin x13, x26, #-128
+smin x17, x9, #127
+umin w0, w0, #0
+umin w1, w0, #0
+umin w0, w1, #0
+umin w0, w0, #1
+umin w2, w8, #34
+umin w13, w26, #128
+umin w17, w9, #255
+umin x0, x0, #0
+umin x1, x0, #0
+umin x0, x1, #0
+umin x0, x0, #1
+umin x2, x8, #34
+umin x13, x26, #128
+umin x17, x9, #255
+
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 9477ac98f3b5208f24ec2fde7cb2e3a56c56b618..838d4239741ea4df2775c05f58165684387957d2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -99,6 +99,7 @@  typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_SME_F64	     (1ULL << 57) /* SME F64.  */
 #define AARCH64_FEATURE_SME_I64	     (1ULL << 58) /* SME I64.  */
 #define AARCH64_FEATURE_V8_8	     (1ULL << 59) /* Armv8.8 processors.  */
+#define AARCH64_FEATURE_CSSC	     (1ULL << 60) /* Common Short Sequence Compression instructions.  */
 
 /* Crypto instructions are the combination of AES and SHA2.  */
 #define AARCH64_FEATURE_CRYPTO	(AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
@@ -492,7 +493,9 @@  enum aarch64_opnd
   AARCH64_OPND_SM3_IMM2,	/* SM3 encodes lane in bits [13, 14].  */
   AARCH64_OPND_MOPS_ADDR_Rd,	/* [Rd]!, in bits [0, 4].  */
   AARCH64_OPND_MOPS_ADDR_Rs,	/* [Rs]!, in bits [16, 20].  */
-  AARCH64_OPND_MOPS_WB_Rn	/* Rn!, in bits [5, 9].  */
+  AARCH64_OPND_MOPS_WB_Rn,	/* Rn!, in bits [5, 9].  */
+  AARCH64_OPND_CSSC_SIMM8,	/* CSSC signed 8-bit immediate.  */
+  AARCH64_OPND_CSSC_UIMM8,	/* CSSC unsigned 8-bit immediate.  */
 };
 
 /* Qualifier constrains an operand.  It either specifies a variant of an
@@ -684,6 +687,7 @@  enum aarch64_insn_class
   cryptosm4,
   dotproduct,
   bfloat16,
+  cssc,
 };
 
 /* Opcode enumerators.  */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 38bc5d7cfa6be6c60c96ef58e355527b3d372400..23c4e81736843cfe3e5266ba79b41a1cd10718cb 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -723,6 +723,8 @@  aarch64_insert_operand (const aarch64_operand *self,
     case 190:
     case 215:
     case 221:
+    case 226:
+    case 227:
       return aarch64_ins_imm (self, info, code, inst, errors);
     case 44:
     case 45:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 69a157899473978b459afce84dd925e7465a8d4b..318b0717c39faf3e78f3ad470143b36ac257ecee 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -4201,21 +4201,43 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                                 }
                                               else
                                                 {
-                                                  if (((word >> 30) & 0x1) == 0)
+                                                  if (((word >> 14) & 0x1) == 0)
                                                     {
-                                                      /* 33222222222211111111110000000000
-                                                         10987654321098765432109876543210
-                                                         x0x11010110xxxxxxx1000xxxxxxxxxx
-                                                         lslv.  */
-                                                      return 713;
+                                                      if (((word >> 30) & 0x1) == 0)
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             x0x11010110xxxxxx01000xxxxxxxxxx
+                                                             lslv.  */
+                                                          return 713;
+                                                        }
+                                                      else
+                                                        {
+                                                          if (((word >> 16) & 0x1) == 0)
+                                                            {
+                                                              /* 33222222222211111111110000000000
+                                                                 10987654321098765432109876543210
+                                                                 x1x11010110xxxx0x01000xxxxxxxxxx
+                                                                 abs.  */
+                                                              return 2640;
+                                                            }
+                                                          else
+                                                            {
+                                                              /* 33222222222211111111110000000000
+                                                                 10987654321098765432109876543210
+                                                                 x1x11010110xxxx1x01000xxxxxxxxxx
+                                                                 paciza.  */
+                                                              return 701;
+                                                            }
+                                                        }
                                                     }
                                                   else
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x1x11010110xxxxxxx1000xxxxxxxxxx
-                                                         paciza.  */
-                                                      return 701;
+                                                         xxx11010110xxxxxx11000xxxxxxxxxx
+                                                         smax.  */
+                                                      return 2643;
                                                     }
                                                 }
                                             }
@@ -4385,21 +4407,32 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                                 }
                                               else
                                                 {
-                                                  if (((word >> 30) & 0x1) == 0)
+                                                  if (((word >> 14) & 0x1) == 0)
                                                     {
-                                                      /* 33222222222211111111110000000000
-                                                         10987654321098765432109876543210
-                                                         x0x11010110xxxxxxx1010xxxxxxxxxx
-                                                         asrv.  */
-                                                      return 717;
+                                                      if (((word >> 30) & 0x1) == 0)
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             x0x11010110xxxxxx01010xxxxxxxxxx
+                                                             asrv.  */
+                                                          return 717;
+                                                        }
+                                                      else
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             x1x11010110xxxxxx01010xxxxxxxxxx
+                                                             pacdza.  */
+                                                          return 703;
+                                                        }
                                                     }
                                                   else
                                                     {
                                                       /* 33222222222211111111110000000000
                                                          10987654321098765432109876543210
-                                                         x1x11010110xxxxxxx1010xxxxxxxxxx
-                                                         pacdza.  */
-                                                      return 703;
+                                                         xxx11010110xxxxxx11010xxxxxxxxxx
+                                                         smin.  */
+                                                      return 2645;
                                                     }
                                                 }
                                             }
@@ -4409,11 +4442,22 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                                 {
                                                   if (((word >> 14) & 0x1) == 0)
                                                     {
-                                                      /* 33222222222211111111110000000000
-                                                         10987654321098765432109876543210
-                                                         xxx11010110xxxxxx00110xxxxxxxxxx
-                                                         autda.  */
-                                                      return 699;
+                                                      if (((word >> 16) & 0x1) == 0)
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             xxx11010110xxxx0x00110xxxxxxxxxx
+                                                             ctz.  */
+                                                          return 2642;
+                                                        }
+                                                      else
+                                                        {
+                                                          /* 33222222222211111111110000000000
+                                                             10987654321098765432109876543210
+                                                             xxx11010110xxxx1x00110xxxxxxxxxx
+                                                             autda.  */
+                                                          return 699;
+                                                        }
                                                     }
                                                   else
                                                     {
@@ -4518,21 +4562,32 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                             }
                                           else
                                             {
-                                              if (((word >> 30) & 0x1) == 0)
+                                              if (((word >> 14) & 0x1) == 0)
                                                 {
-                                                  /* 33222222222211111111110000000000
-                                                     10987654321098765432109876543210
-                                                     x0x11010x10xxxxxxx1001xxxxxxxxxx
-                                                     lsrv.  */
-                                                  return 715;
+                                                  if (((word >> 30) & 0x1) == 0)
+                                                    {
+                                                      /* 33222222222211111111110000000000
+                                                         10987654321098765432109876543210
+                                                         x0x11010x10xxxxxx01001xxxxxxxxxx
+                                                         lsrv.  */
+                                                      return 715;
+                                                    }
+                                                  else
+                                                    {
+                                                      /* 33222222222211111111110000000000
+                                                         10987654321098765432109876543210
+                                                         x1x11010x10xxxxxx01001xxxxxxxxxx
+                                                         pacizb.  */
+                                                      return 702;
+                                                    }
                                                 }
                                               else
                                                 {
                                                   /* 33222222222211111111110000000000
                                                      10987654321098765432109876543210
-                                                     x1x11010x10xxxxxxx1001xxxxxxxxxx
-                                                     pacizb.  */
-                                                  return 702;
+                                                     xxx11010x10xxxxxx11001xxxxxxxxxx
+                                                     umax.  */
+                                                  return 2644;
                                                 }
                                             }
                                         }
@@ -4637,21 +4692,32 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                         }
                                       else
                                         {
-                                          if (((word >> 30) & 0x1) == 0)
+                                          if (((word >> 14) & 0x1) == 0)
                                             {
-                                              /* 33222222222211111111110000000000
-                                                 10987654321098765432109876543210
-                                                 x0x11010xx0xxxxxxx1011xxxxxxxxxx
-                                                 rorv.  */
-                                              return 719;
+                                              if (((word >> 30) & 0x1) == 0)
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     x0x11010xx0xxxxxx01011xxxxxxxxxx
+                                                     rorv.  */
+                                                  return 719;
+                                                }
+                                              else
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     x1x11010xx0xxxxxx01011xxxxxxxxxx
+                                                     pacdzb.  */
+                                                  return 704;
+                                                }
                                             }
                                           else
                                             {
                                               /* 33222222222211111111110000000000
                                                  10987654321098765432109876543210
-                                                 x1x11010xx0xxxxxxx1011xxxxxxxxxx
-                                                 pacdzb.  */
-                                              return 704;
+                                                 xxx11010xx0xxxxxx11011xxxxxxxxxx
+                                                 umin.  */
+                                              return 2646;
                                             }
                                         }
                                     }
@@ -4661,11 +4727,22 @@  aarch64_opcode_lookup_1 (uint32_t word)
                                         {
                                           if (((word >> 14) & 0x1) == 0)
                                             {
-                                              /* 33222222222211111111110000000000
-                                                 10987654321098765432109876543210
-                                                 xxx11010xx0xxxxxx00111xxxxxxxxxx
-                                                 autdb.  */
-                                              return 700;
+                                              if (((word >> 16) & 0x1) == 0)
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     xxx11010xx0xxxx0x00111xxxxxxxxxx
+                                                     cnt.  */
+                                                  return 2641;
+                                                }
+                                              else
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     xxx11010xx0xxxx1x00111xxxxxxxxxx
+                                                     autdb.  */
+                                                  return 700;
+                                                }
                                             }
                                           else
                                             {
@@ -25111,7 +25188,11 @@  aarch64_find_next_opcode (const aarch64_opcode *opcode)
     case 2403: value = 2408; break;	/* st1q --> st1q.  */
     case 2408: return NULL;		/* st1q --> NULL.  */
     case 12: value = 19; break;	/* add --> addg.  */
-    case 19: return NULL;		/* addg --> NULL.  */
+    case 19: value = 2636; break;	/* addg --> smax.  */
+    case 2636: value = 2637; break;	/* smax --> umax.  */
+    case 2637: value = 2638; break;	/* umax --> smin.  */
+    case 2638: value = 2639; break;	/* smin --> umin.  */
+    case 2639: return NULL;		/* umin --> NULL.  */
     case 16: value = 20; break;	/* sub --> subg.  */
     case 20: return NULL;		/* subg --> NULL.  */
     case 971: value = 975; break;	/* stnp --> stp.  */
@@ -25830,6 +25911,8 @@  aarch64_extract_operand (const aarch64_operand *self,
     case 190:
     case 215:
     case 221:
+    case 226:
+    case 227:
       return aarch64_ext_imm (self, info, code, inst, errors);
     case 44:
     case 45:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index a6ef7097a67f11b44a4d6eea777c80de51993b2c..b680225917efb408afd2c8f7f18ada3048900e6f 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -250,6 +250,8 @@  const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"},
   {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
 };
 
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 126565dca14080b3f1370de7dd42cbc1de90c926..b61e8eb96a8a2d8524a69527553d66c0aef69d15 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -168,7 +168,8 @@  enum aarch64_field_kind
   FLD_rotate3,
   FLD_SM3_imm2,
   FLD_sz,
-  FLD_CRm_dsb_nxs
+  FLD_CRm_dsb_nxs,
+  FLD_CSSC_imm8
 };
 
 /* Field description.  */
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index a2882bdfaba43d2b6beacf75f9f1a76d01fbe934..dd888b332c9665ecf654c0e81d495a89fa57dca6 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -342,6 +342,7 @@  const aarch64_field fields[] =
     { 12,  2 }, /* SM3: Indexed element SM3 2 bits index immediate.  */
     { 22,  1 }, /* sz: 1-bit element size select.  */
     { 10,  2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>.  */
+    { 10,  8 }, /* CSSC_imm8.  */
 };
 
 enum aarch64_operand_class
@@ -2176,6 +2177,7 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	case AARCH64_OPND_SVE_UIMM7:
 	case AARCH64_OPND_SVE_UIMM8:
 	case AARCH64_OPND_SVE_UIMM8_53:
+	case AARCH64_OPND_CSSC_UIMM8:
 	  size = get_operand_fields_width (get_operand_from_code (type));
 	  assert (size < 32);
 	  if (!value_fit_unsigned_field_p (opnd->imm.value, size))
@@ -2206,6 +2208,7 @@  operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
 	case AARCH64_OPND_SVE_SIMM5B:
 	case AARCH64_OPND_SVE_SIMM6:
 	case AARCH64_OPND_SVE_SIMM8:
+	case AARCH64_OPND_CSSC_SIMM8:
 	  size = get_operand_fields_width (get_operand_from_code (type));
 	  assert (size < 32);
 	  if (!value_fit_signed_field_p (opnd->imm.value, size))
@@ -3620,6 +3623,8 @@  aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SVE_IMM_ROT1:
     case AARCH64_OPND_SVE_IMM_ROT2:
     case AARCH64_OPND_SVE_IMM_ROT3:
+    case AARCH64_OPND_CSSC_SIMM8:
+    case AARCH64_OPND_CSSC_UIMM8:
       snprintf (buf, size, "%s",
 		style_imm (styler, "#%" PRIi64, opnd->imm.value));
       break;
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index adcc2fe00916263b7c867af001420122fb51f11a..51cc7b94889c381de848ad5236f8566f16361afb 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2508,6 +2508,8 @@  static const aarch64_feature_set aarch64_feature_mops_memtag =
   AARCH64_FEATURE (AARCH64_FEATURE_MOPS | AARCH64_FEATURE_MEMTAG, 0);
 static const aarch64_feature_set aarch64_feature_hbc =
   AARCH64_FEATURE (AARCH64_FEATURE_HBC, 0);
+static const aarch64_feature_set aarch64_feature_cssc =
+  AARCH64_FEATURE (AARCH64_FEATURE_CSSC, 0);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -2562,6 +2564,7 @@  static const aarch64_feature_set aarch64_feature_hbc =
 #define MOPS	  &aarch64_feature_mops
 #define MOPS_MEMTAG &aarch64_feature_mops_memtag
 #define HBC	  &aarch64_feature_hbc
+#define CSSC	  &aarch64_feature_cssc
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@@ -2695,6 +2698,8 @@  static const aarch64_feature_set aarch64_feature_hbc =
     CONSTRAINTS, 0, VERIFIER }
 #define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL }
 
 #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
   MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -5437,6 +5442,21 @@  const struct aarch64_opcode aarch64_opcode_table[] =
 
   HBC_INSN ("bc.c", 0x54000010, 0xff000010, condbranch, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_COND),
 
+/* CSSC with immediates.  */
+  CSSC_INSN ("smax", 0x11c00000 ,0x7ffc0000, OP3 (Rd, Rn, CSSC_SIMM8), QL_R2NIL, F_SF),
+  CSSC_INSN ("umax", 0x11c40000 ,0x7ffc0000, OP3 (Rd, Rn, CSSC_UIMM8), QL_R2NIL, F_SF),
+  CSSC_INSN ("smin", 0x11c80000 ,0x7ffc0000, OP3 (Rd, Rn, CSSC_SIMM8), QL_R2NIL, F_SF),
+  CSSC_INSN ("umin", 0x11cc0000 ,0x7ffc0000, OP3 (Rd, Rn, CSSC_UIMM8), QL_R2NIL, F_SF),
+
+/* CSSC with registers only.  */
+  CSSC_INSN ("abs",  0x5ac02000 ,0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+  CSSC_INSN ("cnt",  0x5ac01c00 ,0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+  CSSC_INSN ("ctz",  0x5ac01800 ,0x7ffffc00, OP2 (Rd, Rn), QL_I2SAME, F_SF),
+  CSSC_INSN ("smax", 0x1ac06000 ,0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+  CSSC_INSN ("umax", 0x1ac06400 ,0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+  CSSC_INSN ("smin", 0x1ac06800 ,0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+  CSSC_INSN ("umin", 0x1ac06c00 ,0x7fe0fc00, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
+
   {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
 };
 
@@ -5928,4 +5948,8 @@  const struct aarch64_opcode aarch64_opcode_table[] =
     Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rs", 0, F(FLD_Rs),			\
       "a register source address with writeback")			\
     Y(INT_REG, x0_to_x30, "MOPS_WB_Rd", 0, F(FLD_Rn),			\
-      "an integer register with writeback")
+      "an integer register with writeback")				\
+    Y(IMMEDIATE, imm, "CSSC_SIMM8", OPD_F_SEXT, F(FLD_CSSC_imm8),	\
+      "an 8-bit signed immediate")					\
+    Y(IMMEDIATE, imm, "CSSC_UIMM8", 0, F(FLD_CSSC_imm8),		\
+      "an 8-bit unsigned immediate")