diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 19391d94e305..19aa9f9ef74f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1051,7 +1051,6 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"g", "zicsr",	check_implicit_always},
   {"g", "zifencei",	check_implicit_always},
   {"m", "zmmul",	check_implicit_always},
-  {"h", "zicsr",	check_implicit_always},
   {"q", "d",		check_implicit_always},
   {"v", "d",		check_implicit_always},
   {"v", "zve64d",	check_implicit_always},
@@ -1087,6 +1086,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zhinx", "zhinxmin",	check_implicit_always},
   {"zhinxmin", "zfinx",	check_implicit_always},
   {"zfinx", "zicsr",	check_implicit_always},
+  {"za64rs", "za128rs",	check_implicit_always},
   {"zk", "zkn",		check_implicit_always},
   {"zk", "zkr",		check_implicit_always},
   {"zk", "zkt",		check_implicit_always},
@@ -1104,10 +1104,23 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
+  {"shcounterenw", "h",		check_implicit_always},
+  {"shgatpa", "h",		check_implicit_always},
+  {"shtvala", "h",		check_implicit_always},
+  {"shvsatpa", "h",		check_implicit_always},
+  {"shvstvala", "h",		check_implicit_always},
+  {"shvstvecd", "h",		check_implicit_always},
+  {"h", "zicsr",		check_implicit_always},
   {"ssaia", "zicsr",		check_implicit_always},
   {"sscofpmf", "zicsr",		check_implicit_always},
+  {"sscounterenw", "zicsr",	check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
+  {"sstvala", "zicsr",		check_implicit_always},
+  {"sstvecd", "zicsr",		check_implicit_always},
+  {"ssu64xl", "zicsr",		check_implicit_always},
+  {"svade", "zicsr",		check_implicit_always},
+  {"svbare", "zicsr",		check_implicit_always},
   {NULL, NULL, NULL}
 };
 
@@ -1165,6 +1178,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] =
 
 static struct riscv_supported_ext riscv_supported_std_z_ext[] =
 {
+  {"zic64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"ziccamoa",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"ziccif",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zicclsm",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"ziccrse",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbom",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicbop",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zicboz",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -1174,6 +1192,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zifencei",		ISA_SPEC_CLASS_20190608,	2, 0,  0 },
   {"zihintpause",	ISA_SPEC_CLASS_DRAFT,		2, 0,  0 },
   {"zmmul",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"za64rs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"za128rs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -1226,12 +1246,27 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"shcounterenw",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"shgatpa",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"shtvala",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"shvsatpa",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"shvstvala",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"shvstvecd",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"ssccptr",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"sscounterenw",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"sstvala",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"sstvecd",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"ssu64xl",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"svbare",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svinval",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svnapot",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"svade",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svpbmt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {NULL, 0, 0, 0, 0}
 };
