@@ -10323,6 +10323,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"flagm", AARCH64_FEATURE (FLAGM), AARCH64_NO_FEATURES},
{"flagm2", AARCH64_FEATURE (FLAGMANIP), AARCH64_FEATURE (FLAGM)},
{"pauth", AARCH64_FEATURE (PAC), AARCH64_NO_FEATURES},
+ {"wfxt", AARCH64_FEATURE (WFXT), AARCH64_NO_FEATURES},
{"mops", AARCH64_FEATURE (MOPS), AARCH64_NO_FEATURES},
{"hbc", AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES},
{"cssc", AARCH64_FEATURE (CSSC), AARCH64_NO_FEATURES},
@@ -68,3 +68,65 @@ Disassembly of section \.text:
.*: d503103c wfit x28
.*: d503103d wfit x29
.*: d503103e wfit x30
+.*: d5031000 wfet x0
+.*: d5031001 wfet x1
+.*: d5031002 wfet x2
+.*: d5031003 wfet x3
+.*: d5031004 wfet x4
+.*: d5031005 wfet x5
+.*: d5031006 wfet x6
+.*: d5031007 wfet x7
+.*: d5031008 wfet x8
+.*: d5031009 wfet x9
+.*: d503100a wfet x10
+.*: d503100b wfet x11
+.*: d503100c wfet x12
+.*: d503100d wfet x13
+.*: d503100e wfet x14
+.*: d503100f wfet x15
+.*: d5031010 wfet x16
+.*: d5031011 wfet x17
+.*: d5031012 wfet x18
+.*: d5031013 wfet x19
+.*: d5031014 wfet x20
+.*: d5031015 wfet x21
+.*: d5031016 wfet x22
+.*: d5031017 wfet x23
+.*: d5031018 wfet x24
+.*: d5031019 wfet x25
+.*: d503101a wfet x26
+.*: d503101b wfet x27
+.*: d503101c wfet x28
+.*: d503101d wfet x29
+.*: d503101e wfet x30
+.*: d5031020 wfit x0
+.*: d5031021 wfit x1
+.*: d5031022 wfit x2
+.*: d5031023 wfit x3
+.*: d5031024 wfit x4
+.*: d5031025 wfit x5
+.*: d5031026 wfit x6
+.*: d5031027 wfit x7
+.*: d5031028 wfit x8
+.*: d5031029 wfit x9
+.*: d503102a wfit x10
+.*: d503102b wfit x11
+.*: d503102c wfit x12
+.*: d503102d wfit x13
+.*: d503102e wfit x14
+.*: d503102f wfit x15
+.*: d5031030 wfit x16
+.*: d5031031 wfit x17
+.*: d5031032 wfit x18
+.*: d5031033 wfit x19
+.*: d5031034 wfit x20
+.*: d5031035 wfit x21
+.*: d5031036 wfit x22
+.*: d5031037 wfit x23
+.*: d5031038 wfit x24
+.*: d5031039 wfit x25
+.*: d503103a wfit x26
+.*: d503103b wfit x27
+.*: d503103c wfit x28
+.*: d503103d wfit x29
+.*: d503103e wfit x30
@@ -66,3 +66,73 @@
wfit x28
wfit x29
wfit x30
+
+
+/* Wait For Event with Timeout is also available with +wfxt. */
+.arch armv8-a+wfxt
+
+ wfet x0
+ wfet x1
+ wfet x2
+ wfet x3
+ wfet x4
+ wfet x5
+ wfet x6
+ wfet x7
+ wfet x8
+ wfet x9
+ wfet x10
+ wfet x11
+ wfet x12
+ wfet x13
+ wfet x14
+ wfet x15
+ wfet x16
+ wfet x17
+ wfet x18
+ wfet x19
+ wfet x20
+ wfet x21
+ wfet x22
+ wfet x23
+ wfet x24
+ wfet x25
+ wfet x26
+ wfet x27
+ wfet x28
+ wfet x29
+ wfet x30
+
+/* Wait For Interrupt with Timeout. */
+
+ wfit x0
+ wfit x1
+ wfit x2
+ wfit x3
+ wfit x4
+ wfit x5
+ wfit x6
+ wfit x7
+ wfit x8
+ wfit x9
+ wfit x10
+ wfit x11
+ wfit x12
+ wfit x13
+ wfit x14
+ wfit x15
+ wfit x16
+ wfit x17
+ wfit x18
+ wfit x19
+ wfit x20
+ wfit x21
+ wfit x22
+ wfit x23
+ wfit x24
+ wfit x25
+ wfit x26
+ wfit x27
+ wfit x28
+ wfit x29
+ wfit x30
@@ -141,6 +141,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_MEMTAG,
/* Transactional Memory Extension. */
AARCH64_FEATURE_TME,
+ /* WFx instructions with timeout. */
+ AARCH64_FEATURE_WFXT,
/* Standardization of memory operations. */
AARCH64_FEATURE_MOPS,
/* Hinted conditional branches. */
@@ -271,6 +273,7 @@ enum aarch64_feature_bit {
| AARCH64_FEATBIT (X, BFLOAT16) \
| AARCH64_FEATBIT (X, I8MM))
#define AARCH64_ARCH_V8_7A_FEATURES(X) (AARCH64_FEATBIT (X, V8_7A) \
+ | AARCH64_FEATBIT (X, WFXT) \
| AARCH64_FEATBIT (X, LS64))
#define AARCH64_ARCH_V8_8A_FEATURES(X) (AARCH64_FEATBIT (X, V8_8A) \
| AARCH64_FEATBIT (X, MOPS) \
@@ -2598,6 +2598,8 @@ static const aarch64_feature_set aarch64_feature_ls64 =
AARCH64_FEATURE (LS64);
static const aarch64_feature_set aarch64_feature_flagm =
AARCH64_FEATURE (FLAGM);
+static const aarch64_feature_set aarch64_feature_wfxt =
+ AARCH64_FEATURE (WFXT);
static const aarch64_feature_set aarch64_feature_mops =
AARCH64_FEATURE (MOPS);
static const aarch64_feature_set aarch64_feature_mops_memtag =
@@ -2676,6 +2678,7 @@ static const aarch64_feature_set aarch64_feature_d128_the =
#define ARMV8_7A &aarch64_feature_v8_7a
#define LS64 &aarch64_feature_ls64
#define FLAGM &aarch64_feature_flagm
+#define WFXT &aarch64_feature_wfxt
#define MOPS &aarch64_feature_mops
#define MOPS_MEMTAG &aarch64_feature_mops_memtag
#define HBC &aarch64_feature_hbc
@@ -2825,6 +2828,8 @@ static const aarch64_feature_set aarch64_feature_d128_the =
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL }
#define V8_7A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, ARMV8_7A, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL }
#define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL }
#define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
@@ -4245,8 +4250,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
D128_INSN ("tlbip",0xd5480000, 0xfff80000, OP3 (SYSREG_TLBIP, Rt_SYS, PAIRREG_OR_XZR), QL_SRC_X2, F_ALIAS| F_OPD1_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),
- V8_7A_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
- V8_7A_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
+ WFXT_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
+ WFXT_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),