diff mbox series

[Binutils] AArch64: Enable Debug (FEAT_DEBUGv8p9) extension

Message ID 2eed4bf8-2c7e-42ce-8ac4-498858d3b8d7@arm.com
State Unresolved
Headers
Series [Binutils] AArch64: Enable Debug (FEAT_DEBUGv8p9) extension |

Checks

Context Check Description
snail/binutils-gdb-check warning Git am fail log

Commit Message

Saurabh Jha Nov. 24, 2023, 12:39 p.m. UTC 
  Hey,


This patch enables FEAT_DEBUGv8p9 extension for AArch64 and adds its 
system registers. FEAT_DEBUGv8p9 is default from Armv8.9-A Architecture.


Did regression testing for aarch64-none-elf target and found no regressions.


Ok for master? I don't have commit access so I need someone to commit on 
my behalf.


Regards,

Saurabh
From 5600438d1fb31cc9d0135b92dfe792906e9fac73 Mon Sep 17 00:00:00 2001
From: Saurabh Jha <saujha01@e130340.arm.com>
Date: Tue, 21 Nov 2023 09:50:35 +0000
Subject: [PATCH] Enable Debug (DEBUGv8p9) extension for AArch64

---
 gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l | 2 ++
 gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d     | 2 ++
 gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s     | 3 +++
 include/opcode/aarch64.h                          | 3 +++
 opcodes/aarch64-sys-regs.def                      | 1 +
 5 files changed, 11 insertions(+)

Comments

Saurabh Jha Dec. 7, 2023, 9:10 a.m. UTC | #1 
Ping

On 11/24/2023 12:39 PM, Saurabh Jha wrote:
> Hey,
>
>
> This patch enables FEAT_DEBUGv8p9 extension for AArch64 and adds its 
> system registers. FEAT_DEBUGv8p9 is default from Armv8.9-A Architecture.
>
>
> Did regression testing for aarch64-none-elf target and found no 
> regressions.
>
>
> Ok for master? I don't have commit access so I need someone to commit 
> on my behalf.
>
>
> Regards,
>
> Saurabh
Saurabh Jha Dec. 7, 2023, 1:08 p.m. UTC | #2 
Please ignore this patch. I will send an updated one later.

Regards,

Saurabh

On 12/7/2023 9:10 AM, Saurabh Jha wrote:
> Ping
>
> On 11/24/2023 12:39 PM, Saurabh Jha wrote:
>> Hey,
>>
>>
>> This patch enables FEAT_DEBUGv8p9 extension for AArch64 and adds its 
>> system registers. FEAT_DEBUGv8p9 is default from Armv8.9-A Architecture.
>>
>>
>> Did regression testing for aarch64-none-elf target and found no 
>> regressions.
>>
>>
>> Ok for master? I don't have commit access so I need someone to commit 
>> on my behalf.
>>
>>
>> Regards,
>>
>> Saurabh
diff mbox series

Patch

diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
index 71ec06e3cb4..7fa3ca1d08f 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -77,3 +77,5 @@ 
 .*: Error: selected processor does not support system register name 'tcr2_el1'
 .*: Error: selected processor does not support system register name 'tcr2_el12'
 .*: Error: selected processor does not support system register name 'tcr2_el2'
+.*: Error: selected processor does not support system register name 'mdselr_el1'
+.*: Error: selected processor does not support system register name 'mdselr_el1'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
index ea4cc867ec3..5fc9d807569 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -84,3 +84,5 @@  Disassembly of section \.text:
 .*:	d5182060 	msr	tcr2_el1, x0
 .*:	d51d2060 	msr	tcr2_el12, x0
 .*:	d51c2060 	msr	tcr2_el2, x0
+.*:	d5300440 	mrs	x0, mdselr_el1
+.*:	d5100440 	msr	mdselr_el1, x0
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
index 2768c268690..ffd86bced83 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -98,3 +98,6 @@ 
 	msr tcr2_el1, x0
 	msr tcr2_el12, x0
 	msr tcr2_el2, x0
+
+	mrs x0, MDSELR_EL1
+	msr MDSELR_EL1, x0
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 632338318b6..49d9682b02b 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -197,6 +197,8 @@  enum aarch64_feature_bit {
   AARCH64_FEATURE_S2POE,
   /* Extension to Translation Control Registers.  */
   AARCH64_FEATURE_TCR2,
+  /* Armv8.9-A/Armv9.4-A architecture Debug extension.  */
+  AARCH64_FEATURE_DEBUGv8p9,
   AARCH64_NUM_FEATURES
 };
 
@@ -267,6 +269,7 @@  enum aarch64_feature_bit {
 					 | AARCH64_FEATBIT (X, S1POE)	\
 					 | AARCH64_FEATBIT (X, S2POE)	\
 					 | AARCH64_FEATBIT (X, TCR2)	\
+					 | AARCH64_FEATBIT (X, DEBUGv8p9) \
 					)
 
 #define AARCH64_ARCH_V9A_FEATURES(X)	(AARCH64_FEATBIT (X, V9A)	\
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 0f647efca7e..f7ad09b8ad8 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -570,6 +570,7 @@ 
   SYSREG ("mdcr_el3",		CPENC (3,6,1,3,1),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mdrar_el1",		CPENC (2,0,1,0,0),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("mdscr_el1",		CPENC (2,0,0,2,2),	0,			AARCH64_NO_FEATURES)
+  SYSREG ("mdselr_el1",		CPENC (2,0,0,4,2),	F_ARCHEXT,		AARCH64_FEATURE (DEBUGv8p9))
   SYSREG ("mecid_a0_el2",	CPENC (3,4,10,8,1),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mecid_a1_el2",	CPENC (3,4,10,8,3),	0,			AARCH64_NO_FEATURES)
   SYSREG ("mecid_p0_el2",	CPENC (3,4,10,8,0),	0,			AARCH64_NO_FEATURES)