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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id cm18-20020a0564020c9200b0044ee4ec8915si2815476edb.39.2022.11.25.03.42.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:42:13 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ixxj0s6k; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 91C14384EF5B for ; Fri, 25 Nov 2022 11:42:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 91C14384EF5B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669376528; bh=SixdbpPU9QjqdR1hLfMZEqE2UlxzSRIQKVUHM5rhJCI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ixxj0s6klwn+vom1AyA6Ng6+59Lsfxsv7QpD5lxdnRXTexzxP7HxDOz1TJPzhgKJh NC2/aXDoiDdIQkX94yfKF2O7lM883aCJ+VFBKhw9+5B7n8WpzAYaO2HuRo9I53hL4n 13HXpwsgZDF4Bh0r0zefP8CgP0qr+yM9jjED6zYU= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 4DC44384F8BA for ; Fri, 25 Nov 2022 11:42:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 4DC44384F8BA Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 6B217300089; Fri, 25 Nov 2022 11:41:58 +0000 (UTC) To: Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v3 1/3] RISC-V: Better support for long instructions (disassembler) Date: Fri, 25 Nov 2022 11:41:40 +0000 Message-Id: <2c04525e48f5fc135b6dcb35ca6f1fec4e9b122b.1669376496.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750432667094790247?= X-GMAIL-MSGID: =?utf-8?q?1750468167621890389?= From: Tsukasa OI Commit bb996692bd96 ("RISC-V/gas: allow generating up to 176-bit instructions with .insn") tried to start supporting long instructions but it was insufficient. On the disassembler, correct ".byte" output was limited to the first 64-bits of an instruction. After that, zeroes are incorrectly printed. Note that, it only happens on ".byte" output (instruction part) and not on hexdump (data) part. For example, before this commit, hexdump and ".byte" produces different values: Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (before the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc Note that, after 0xcd (after first 64-bits of the target instruction), all ".byte" values are incorrectly printed as zero while hexdump prints correct instruction bits. To resolve this, this commit adds "packet" argument to support dumping instructions longer than 64-bits (to print correct instruction bits on ".byte"). This commit will be tested on the separate commit. Assembly: .insn 22, 0xfedcba98765432100123456789abcdef55aa33cc607f objdump output example (after the fix): 10: 607f 33cc 55aa cdef .byte 0x7f, 0x60, 0xcc, 0x33, 0xaa, 0x55, 0xef, 0xcd, 0xab, 0x89, 0x67, 0x45, 0x23, 0x01, 0x10, 0x32, 0x54, 0x76, 0x98, 0xba, 0xdc, 0xfe 18: 89ab 4567 0123 3210 20: 7654 ba98 fedc opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Print unknown instruction using the new argument packet. (riscv_disassemble_data): Add unused argument packet. (print_insn_riscv): Pass packet to the disassemble function. --- opcodes/riscv-dis.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 3a31647a2f80..0e1f3b4610aa 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -641,7 +641,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info this is little-endian code. */ static int -riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) +riscv_disassemble_insn (bfd_vma memaddr, + insn_t word, + const bfd_byte *packet, + disassemble_info *info) { const struct riscv_opcode *op; static bool init = false; @@ -806,8 +809,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) ", "); (*info->fprintf_styled_func) (info->stream, dis_style_immediate, "0x%02x", - (unsigned int) (word & 0xff)); - word >>= 8; + (unsigned int) (*packet++)); } } break; @@ -983,6 +985,7 @@ riscv_data_length (bfd_vma memaddr, static int riscv_disassemble_data (bfd_vma memaddr ATTRIBUTE_UNUSED, insn_t data, + const bfd_byte *packet ATTRIBUTE_UNUSED, disassemble_info *info) { info->display_endian = info->endian; @@ -1037,7 +1040,8 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) bfd_vma dump_size; int status; enum riscv_seg_mstate mstate; - int (*riscv_disassembler) (bfd_vma, insn_t, struct disassemble_info *); + int (*riscv_disassembler) (bfd_vma, insn_t, const bfd_byte *, + struct disassemble_info *); if (info->disassembler_options != NULL) { @@ -1081,7 +1085,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) } insn = (insn_t) bfd_get_bits (packet, dump_size * 8, false); - return (*riscv_disassembler) (memaddr, insn, info); + return (*riscv_disassembler) (memaddr, insn, packet, info); } disassembler_ftype