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[REVIEW,ONLY,1/1] UNRATIFIED RISC-V: Add 'Svadu' extension

Message ID 29f89ef04335561879d14d9cdb8e1e9a550bc811.1669684692.git.research_trasio@irq.a4lg.com
State Accepted
Headers
Series UNRATIFIED RISC-V: Add 'Svadu' extension |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Tsukasa OI Nov. 29, 2022, 1:18 a.m. UTC 
  From: Tsukasa OI <research_trasio@irq.a4lg.com>

[DO NOT MERGE]
Until 'Svadu' extension is frozen/ratified and final version number is
determined, this patch should not be merged upstream.  This commit uses
unratified version 0.1 as in the documentation (instead of possible 1.0
after ratification).

This commit implements support for 'Svadu' extension.  Because it does not
add any instructions or CSRs (but adds bits to existing CSRs), this commit
adds extension name support and implication to the 'Zicsr' extension.

This is based on "Hardware Updating of PTE A/D Bits (Svadu)" version 0.1,
stable <https://github.com/riscv/riscv-svadu/releases/tag/vv0.1>.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add implication from
	'Svadu' to 'Zicsr'.  (riscv_supported_std_s_ext) Add 'Svadu'.
---
 bfd/elfxx-riscv.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Palmer Dabbelt Nov. 29, 2022, 1:57 a.m. UTC | #1 
On Mon, 28 Nov 2022 17:18:15 PST (-0800), binutils@sourceware.org wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> [DO NOT MERGE]
> Until 'Svadu' extension is frozen/ratified and final version number is
> determined, this patch should not be merged upstream.  This commit uses
> unratified version 0.1 as in the documentation (instead of possible 1.0
> after ratification).
>
> This commit implements support for 'Svadu' extension.  Because it does not
> add any instructions or CSRs (but adds bits to existing CSRs), this commit
> adds extension name support and implication to the 'Zicsr' extension.
>
> This is based on "Hardware Updating of PTE A/D Bits (Svadu)" version 0.1,
> stable <https://github.com/riscv/riscv-svadu/releases/tag/vv0.1>.
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_implicit_subsets): Add implication from
> 	'Svadu' to 'Zicsr'.  (riscv_supported_std_s_ext) Add 'Svadu'.
> ---
>  bfd/elfxx-riscv.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 0bcf2fdcfa34..826f248f88c4 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1108,6 +1108,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
>    {"sscofpmf", "zicsr",		check_implicit_always},
>    {"ssstateen", "zicsr",	check_implicit_always},
>    {"sstc", "zicsr",		check_implicit_always},
> +  {"svadu", "zicsr",		check_implicit_always},
>    {NULL, NULL, NULL}
>  };
>
> @@ -1230,6 +1231,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
>    {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
>    {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
>    {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
> +  {"svadu",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
>    {"svinval",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
>    {"svnapot",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
>    {"svpbmt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> # pending freeze
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0bcf2fdcfa34..826f248f88c4 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1108,6 +1108,7 @@  static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
+  {"svadu", "zicsr",		check_implicit_always},
   {NULL, NULL, NULL}
 };
 
@@ -1230,6 +1231,7 @@  static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sstc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"svadu",		ISA_SPEC_CLASS_DRAFT,		0, 1, 0 },
   {"svinval",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svnapot",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"svpbmt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },