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[37.24.206.209]) by smtp.gmail.com with ESMTPSA id jv14-20020a05600c570e00b0040fe3147babsm1820618wmb.0.2024.02.16.01.59.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 16 Feb 2024 01:59:25 -0800 (PST) Message-ID: <263f41dd-b7bf-42a5-92a4-3732c53e276e@suse.com> Date: Fri, 16 Feb 2024 10:59:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: [PATCH 4/4] x86/APX: optimize certain XOR and SUB forms Content-Language: en-US From: Jan Beulich To: Binutils Cc: "H.J. Lu" , Lili Cui References: <3098e797-3749-40ee-802c-ea8a6f63914c@suse.com> Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: <3098e797-3749-40ee-802c-ea8a6f63914c@suse.com> X-Spam-Status: No, score=-3023.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, PERCENT_RANDOM, RCVD_IN_DNSWL_NONE, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1791049158198506366 X-GMAIL-MSGID: 1791049158198506366 While most logic in optimize_encoding() is already covering APX by way of the earlier NDD->REX2 conversion, there's a remaining set of cases which wants handling separately. --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -4693,6 +4693,34 @@ optimize_encoding (void) } } } + else if (i.reg_operands == 3 + && i.op[0].regs == i.op[1].regs + && i.encoding != encoding_evex + && (i.tm.mnem_off == MN_xor + || i.tm.mnem_off == MN_sub)) + { + /* Optimize: -O: + xorb %rNb, %rNb, %rMb -> xorl %rMd, %rMd + xorw %rNw, %rNw, %rMw -> xorl %rMd, %rMd + xorl %rNd, %rNd, %rMd -> xorl %rMd, %rMd + xorq %rN, %rN, %rM -> xorl %rMd, %rMd + subb %rNb, %rNb, %rMb -> subl %rMd, %rMd + subw %rNw, %rNw, %rMw -> subl %rMd, %rMd + subl %rNd, %rNd, %rMd -> subl %rMd, %rMd + subq %rN, %rN, %rM -> subl %rMd, %rMd + */ + i.tm.opcode_space = SPACE_BASE; + i.tm.opcode_modifier.evex = 0; + i.tm.opcode_modifier.size = SIZE32; + i.types[0].bitfield.byte = 0; + i.types[0].bitfield.word = 0; + i.types[0].bitfield.dword = 1; + i.types[0].bitfield.qword = 0; + i.op[0].regs = i.op[2].regs; + i.types[1] = i.types[0]; + i.op[1].regs = i.op[2].regs; + i.reg_operands = 2; + } else if (optimize > 1 && !optimize_for_space && i.reg_operands == 2 --- a/gas/testsuite/gas/i386/x86-64-optimize-1.d +++ b/gas/testsuite/gas/i386/x86-64-optimize-1.d @@ -71,4 +71,28 @@ Disassembly of section .text: +[a-f0-9]+: 48 0f ba f0 1f btr \$0x1f,%rax +[a-f0-9]+: 66 0f ba e8 0f bts \$0xf,%ax +[a-f0-9]+: 48 0f ba e8 1f bts \$0x1f,%rax + +[a-f0-9]+: 31 c9 xor %ecx,%ecx + +[a-f0-9]+: 48 31 d1 xor %rdx,%rcx + +[a-f0-9]+: 31 c9 xor %ecx,%ecx + +[a-f0-9]+: 29 c9 sub %ecx,%ecx + +[a-f0-9]+: 48 29 d1 sub %rdx,%rcx + +[a-f0-9]+: 29 c9 sub %ecx,%ecx + +[a-f0-9]+: d5 50 31 c9 xor %r17d,%r17d + +[a-f0-9]+: d5 58 31 d1 xor %r18,%r17 + +[a-f0-9]+: d5 50 31 c9 xor %r17d,%r17d + +[a-f0-9]+: d5 50 29 c9 sub %r17d,%r17d + +[a-f0-9]+: d5 58 29 d1 sub %r18,%r17 + +[a-f0-9]+: d5 50 29 c9 sub %r17d,%r17d + +[a-f0-9]+: 31 c9 xor %ecx,%ecx + +[a-f0-9]+: 62 f4 75 18 31 d1 xor %dx,%cx,%cx + +[a-f0-9]+: 31 c9 xor %ecx,%ecx + +[a-f0-9]+: 29 c9 sub %ecx,%ecx + +[a-f0-9]+: 62 f4 75 18 29 d1 sub %dx,%cx,%cx + +[a-f0-9]+: 29 c9 sub %ecx,%ecx + +[a-f0-9]+: d5 50 31 c9 xor %r17d,%r17d + +[a-f0-9]+: 62 ec 74 10 30 d1 xor %r18b,%r17b,%r17b + +[a-f0-9]+: d5 50 31 c9 xor %r17d,%r17d + +[a-f0-9]+: d5 50 29 c9 sub %r17d,%r17d + +[a-f0-9]+: 62 ec 74 10 28 d1 sub %r18b,%r17b,%r17b + +[a-f0-9]+: d5 50 29 c9 sub %r17d,%r17d #pass --- a/gas/testsuite/gas/i386/x86-64-optimize-1.s +++ b/gas/testsuite/gas/i386/x86-64-optimize-1.s @@ -65,3 +65,27 @@ _start: btr $31, %rax bts $15, %ax bts $31, %rax + xor %rcx, %rcx, %rcx + xor %rdx, %rcx, %rcx + xor %rdx, %rdx, %rcx + sub %rcx, %rcx, %rcx + sub %rdx, %rcx, %rcx + sub %rdx, %rdx, %rcx + xor %r17, %r17, %r17 + xor %r18, %r17, %r17 + xor %r18, %r18, %r17 + sub %r17, %r17, %r17 + sub %r18, %r17, %r17 + sub %r18, %r18, %r17 + xor %cx, %cx, %cx + xor %dx, %cx, %cx + xor %dx, %dx, %cx + sub %cx, %cx, %cx + sub %dx, %cx, %cx + sub %dx, %dx, %cx + xor %r17b, %r17b, %r17b + xor %r18b, %r17b, %r17b + xor %r18b, %r18b, %r17b + sub %r17b, %r17b, %r17b + sub %r18b, %r17b, %r17b + sub %r18b, %r18b, %r17b --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -320,7 +320,7 @@ inc, 0x40, No64, No_bSuf|No_sSuf|No_qSuf inc, 0xfe/0, APX_F, W|Modrm|No_sSuf|CheckOperandSize|DstVVVV|EVexMap4|NF, {Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64} inc, 0xfe/0, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -sub, 0x28, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, } +sub, 0x28, APX_F, D|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64, } sub, 0x28, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } sub, 0x83/5, APX_F, Modrm|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } sub, 0x83/5, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex } @@ -366,7 +366,7 @@ or, 0xc, 0, W|No_sSuf, { Imm8|Imm16|Imm3 or, 0x80/1, APX_F, W|Modrm|CheckOperandSize|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } or, 0x80/1, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } -xor, 0x30, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } +xor, 0x30, APX_F, D|C|W|CheckOperandSize|Modrm|No_sSuf|DstVVVV|EVexMap4|NF|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg8|Reg16|Reg32|Reg64 } xor, 0x30, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex } xor, 0x83/6, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } xor, 0x83/6, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex }