diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 97ad782012c..1acbba1791a 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -353,6 +353,16 @@ static const struct pd_reg pre_defined_registers[] =
   { "dec", 22, PPC_OPERAND_SPR },
   { "dsisr", 18, PPC_OPERAND_SPR },
 
+  /* Dense Math Registers.  */
+  { "dm0", 0, PPC_OPERAND_DMR },
+  { "dm1", 1, PPC_OPERAND_DMR },
+  { "dm2", 2, PPC_OPERAND_DMR },
+  { "dm3", 3, PPC_OPERAND_DMR },
+  { "dm4", 4, PPC_OPERAND_DMR },
+  { "dm5", 5, PPC_OPERAND_DMR },
+  { "dm6", 6, PPC_OPERAND_DMR },
+  { "dm7", 7, PPC_OPERAND_DMR },
+
   /* Floating point registers */
   { "f.0", 0, PPC_OPERAND_FPR },
   { "f.1", 1, PPC_OPERAND_FPR },
@@ -3475,7 +3485,8 @@ md_assemble (char *str)
 	       & ~operand->flags
 	       & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR
 		  | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG
-		  | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0
+		  | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC
+		  | PPC_OPERAND_DMR)) != 0
 	      && !((ex.X_md & PPC_OPERAND_GPR) != 0
 		   && ex.X_add_number != 0
 		   && (operand->flags & PPC_OPERAND_GPR_0) != 0))
diff --git a/gas/testsuite/gas/ppc/outerprod.d b/gas/testsuite/gas/ppc/outerprod.d
index 613fb189966..332102b1318 100644
--- a/gas/testsuite/gas/ppc/outerprod.d
+++ b/gas/testsuite/gas/ppc/outerprod.d
@@ -8,97 +8,184 @@
 Disassembly of section \.text:
 
 0+0 <_start>:
-.*:	(7e 80 01 62|62 01 80 7e) 	xxmfacc a5
-.*:	(7f 01 01 62|62 01 01 7f) 	xxmtacc a6
-.*:	(7f 83 01 62|62 01 83 7f) 	xxsetaccz a7
-.*:	(ec 1f f1 1e|1e f1 1f ec) 	xvi4ger8 a0,vs63,vs62
-.*:	(ec 9d e1 16|16 e1 9d ec) 	xvi4ger8pp a1,vs61,vs60
-.*:	(07 90 ff fe|fe ff 90 07) 	pmxvi4ger8 a2,vs59,vs58,15,14,255
+.*:	(7e 80 01 62|62 01 80 7e) 	dmxxmfacc a5
+.*:	(7e 80 01 62|62 01 80 7e) 	dmxxmfacc a5
+.*:	(7f 01 01 62|62 01 01 7f) 	dmxxmtacc a6
+.*:	(7f 01 01 62|62 01 01 7f) 	dmxxmtacc a6
+.*:	(7f 83 01 62|62 01 83 7f) 	dmsetaccz a7
+.*:	(7f 83 01 62|62 01 83 7f) 	dmsetaccz a7
+.*:	(ec 1f f1 1e|1e f1 1f ec) 	dmxvi4ger8 a0,vs63,vs62
+.*:	(ec 1f f1 1e|1e f1 1f ec) 	dmxvi4ger8 a0,vs63,vs62
+.*:	(ec 9d e1 16|16 e1 9d ec) 	dmxvi4ger8pp a1,vs61,vs60
+.*:	(ec 9d e1 16|16 e1 9d ec) 	dmxvi4ger8pp a1,vs61,vs60
+.*:	(07 90 ff fe|fe ff 90 07) 	pmdmxvi4ger8 a2,vs59,vs58,15,14,255
 .*:	(ed 1b d1 1e|1e d1 1b ed) 
-.*:	(07 90 80 78|78 80 90 07) 	pmxvi4ger8pp a3,vs57,vs56,7,8,128
+.*:	(07 90 ff fe|fe ff 90 07) 	pmdmxvi4ger8 a2,vs59,vs58,15,14,255
+.*:	(ed 1b d1 1e|1e d1 1b ed) 
+.*:	(07 90 80 78|78 80 90 07) 	pmdmxvi4ger8pp a3,vs57,vs56,7,8,128
+.*:	(ed 99 c1 16|16 c1 99 ed) 
+.*:	(07 90 80 78|78 80 90 07) 	pmdmxvi4ger8pp a3,vs57,vs56,7,8,128
 .*:	(ed 99 c1 16|16 c1 99 ed) 
-.*:	(ee 17 b0 1e|1e b0 17 ee) 	xvi8ger4 a4,vs55,vs54
-.*:	(ee 95 a0 16|16 a0 95 ee) 	xvi8ger4pp a5,vs53,vs52
-.*:	(07 90 b0 dc|dc b0 90 07) 	pmxvi8ger4 a6,vs51,vs50,13,12,11
+.*:	(ee 17 b0 1e|1e b0 17 ee) 	dmxvi8ger4 a4,vs55,vs54
+.*:	(ee 17 b0 1e|1e b0 17 ee) 	dmxvi8ger4 a4,vs55,vs54
+.*:	(ee 95 a0 16|16 a0 95 ee) 	dmxvi8ger4pp a5,vs53,vs52
+.*:	(ee 95 a0 16|16 a0 95 ee) 	dmxvi8ger4pp a5,vs53,vs52
+.*:	(07 90 b0 dc|dc b0 90 07) 	pmdmxvi8ger4 a6,vs51,vs50,13,12,11
 .*:	(ef 13 90 1e|1e 90 13 ef) 
-.*:	(07 90 80 a9|a9 80 90 07) 	pmxvi8ger4pp a7,vs49,vs48,10,9,8
+.*:	(07 90 b0 dc|dc b0 90 07) 	pmdmxvi8ger4 a6,vs51,vs50,13,12,11
+.*:	(ef 13 90 1e|1e 90 13 ef) 
+.*:	(07 90 80 a9|a9 80 90 07) 	pmdmxvi8ger4pp a7,vs49,vs48,10,9,8
+.*:	(ef 91 80 16|16 80 91 ef) 
+.*:	(07 90 80 a9|a9 80 90 07) 	pmdmxvi8ger4pp a7,vs49,vs48,10,9,8
 .*:	(ef 91 80 16|16 80 91 ef) 
-.*:	(ec 0f 71 5e|5e 71 0f ec) 	xvi16ger2s a0,vs47,vs46
-.*:	(ec 8d 61 56|56 61 8d ec) 	xvi16ger2spp a1,vs45,vs44
-.*:	(07 90 c0 76|76 c0 90 07) 	pmxvi16ger2s a2,vs43,vs42,7,6,3
+.*:	(ec 0f 71 5e|5e 71 0f ec) 	dmxvi16ger2s a0,vs47,vs46
+.*:	(ec 0f 71 5e|5e 71 0f ec) 	dmxvi16ger2s a0,vs47,vs46
+.*:	(ec 8d 61 56|56 61 8d ec) 	dmxvi16ger2spp a1,vs45,vs44
+.*:	(ec 8d 61 56|56 61 8d ec) 	dmxvi16ger2spp a1,vs45,vs44
+.*:	(07 90 c0 76|76 c0 90 07) 	pmdmxvi16ger2s a2,vs43,vs42,7,6,3
 .*:	(ed 0b 51 5e|5e 51 0b ed) 
-.*:	(07 90 80 54|54 80 90 07) 	pmxvi16ger2spp a3,vs41,vs40,5,4,2
+.*:	(07 90 c0 76|76 c0 90 07) 	pmdmxvi16ger2s a2,vs43,vs42,7,6,3
+.*:	(ed 0b 51 5e|5e 51 0b ed) 
+.*:	(07 90 80 54|54 80 90 07) 	pmdmxvi16ger2spp a3,vs41,vs40,5,4,2
+.*:	(ed 89 41 56|56 41 89 ed) 
+.*:	(07 90 80 54|54 80 90 07) 	pmdmxvi16ger2spp a3,vs41,vs40,5,4,2
 .*:	(ed 89 41 56|56 41 89 ed) 
-.*:	(ee 07 30 9e|9e 30 07 ee) 	xvf16ger2 a4,vs39,vs38
-.*:	(ee 85 20 96|96 20 85 ee) 	xvf16ger2pp a5,vs37,vs36
-.*:	(ef 03 14 96|96 14 03 ef) 	xvf16ger2pn a6,vs35,vs34
-.*:	(ef 81 02 96|96 02 81 ef) 	xvf16ger2np a7,vs33,vs32
-.*:	(ec 04 2e 90|90 2e 04 ec) 	xvf16ger2nn a0,vs4,vs5
-.*:	(07 90 40 32|32 40 90 07) 	pmxvf16ger2 a1,vs2,vs3,3,2,1
+.*:	(ee 07 30 9e|9e 30 07 ee) 	dmxvf16ger2 a4,vs39,vs38
+.*:	(ee 07 30 9e|9e 30 07 ee) 	dmxvf16ger2 a4,vs39,vs38
+.*:	(ee 85 20 96|96 20 85 ee) 	dmxvf16ger2pp a5,vs37,vs36
+.*:	(ee 85 20 96|96 20 85 ee) 	dmxvf16ger2pp a5,vs37,vs36
+.*:	(ef 03 14 96|96 14 03 ef) 	dmxvf16ger2pn a6,vs35,vs34
+.*:	(ef 03 14 96|96 14 03 ef) 	dmxvf16ger2pn a6,vs35,vs34
+.*:	(ef 81 02 96|96 02 81 ef) 	dmxvf16ger2np a7,vs33,vs32
+.*:	(ef 81 02 96|96 02 81 ef) 	dmxvf16ger2np a7,vs33,vs32
+.*:	(ec 04 2e 90|90 2e 04 ec) 	dmxvf16ger2nn a0,vs4,vs5
+.*:	(ec 04 2e 90|90 2e 04 ec) 	dmxvf16ger2nn a0,vs4,vs5
+.*:	(07 90 40 32|32 40 90 07) 	pmdmxvf16ger2 a1,vs2,vs3,3,2,1
 .*:	(ec 82 18 98|98 18 82 ec) 
-.*:	(07 90 00 10|10 00 90 07) 	pmxvf16ger2pp a2,vs4,vs5,1,0,0
+.*:	(07 90 40 32|32 40 90 07) 	pmdmxvf16ger2 a1,vs2,vs3,3,2,1
+.*:	(ec 82 18 98|98 18 82 ec) 
+.*:	(07 90 00 10|10 00 90 07) 	pmdmxvf16ger2pp a2,vs4,vs5,1,0,0
+.*:	(ed 04 28 90|90 28 04 ed) 
+.*:	(07 90 00 10|10 00 90 07) 	pmdmxvf16ger2pp a2,vs4,vs5,1,0,0
 .*:	(ed 04 28 90|90 28 04 ed) 
-.*:	(07 90 c0 fe|fe c0 90 07) 	pmxvf16ger2pn a3,vs6,vs7,15,14,3
+.*:	(07 90 c0 fe|fe c0 90 07) 	pmdmxvf16ger2pn a3,vs6,vs7,15,14,3
 .*:	(ed 86 3c 90|90 3c 86 ed) 
-.*:	(07 90 80 dc|dc 80 90 07) 	pmxvf16ger2np a4,vs8,vs9,13,12,2
+.*:	(07 90 c0 fe|fe c0 90 07) 	pmdmxvf16ger2pn a3,vs6,vs7,15,14,3
+.*:	(ed 86 3c 90|90 3c 86 ed) 
+.*:	(07 90 80 dc|dc 80 90 07) 	pmdmxvf16ger2np a4,vs8,vs9,13,12,2
+.*:	(ee 08 4a 90|90 4a 08 ee) 
+.*:	(07 90 80 dc|dc 80 90 07) 	pmdmxvf16ger2np a4,vs8,vs9,13,12,2
 .*:	(ee 08 4a 90|90 4a 08 ee) 
-.*:	(07 90 40 ba|ba 40 90 07) 	pmxvf16ger2nn a5,vs10,vs11,11,10,1
+.*:	(07 90 40 ba|ba 40 90 07) 	pmdmxvf16ger2nn a5,vs10,vs11,11,10,1
 .*:	(ee 8a 5e 90|90 5e 8a ee) 
-.*:	(ef 0c 68 d8|d8 68 0c ef) 	xvf32ger a6,vs12,vs13
-.*:	(ef 8e 78 d0|d0 78 8e ef) 	xvf32gerpp a7,vs14,vs15
-.*:	(ec 10 8c d0|d0 8c 10 ec) 	xvf32gerpn a0,vs16,vs17
-.*:	(ec 92 9a d0|d0 9a 92 ec) 	xvf32gernp a1,vs18,vs19
-.*:	(ed 14 ae d0|d0 ae 14 ed) 	xvf32gernn a2,vs20,vs21
-.*:	(07 90 00 98|98 00 90 07) 	pmxvf32ger a3,vs22,vs23,9,8
+.*:	(07 90 40 ba|ba 40 90 07) 	pmdmxvf16ger2nn a5,vs10,vs11,11,10,1
+.*:	(ee 8a 5e 90|90 5e 8a ee) 
+.*:	(ef 0c 68 d8|d8 68 0c ef) 	dmxvf32ger a6,vs12,vs13
+.*:	(ef 0c 68 d8|d8 68 0c ef) 	dmxvf32ger a6,vs12,vs13
+.*:	(ef 8e 78 d0|d0 78 8e ef) 	dmxvf32gerpp a7,vs14,vs15
+.*:	(ef 8e 78 d0|d0 78 8e ef) 	dmxvf32gerpp a7,vs14,vs15
+.*:	(ec 10 8c d0|d0 8c 10 ec) 	dmxvf32gerpn a0,vs16,vs17
+.*:	(ec 10 8c d0|d0 8c 10 ec) 	dmxvf32gerpn a0,vs16,vs17
+.*:	(ec 92 9a d0|d0 9a 92 ec) 	dmxvf32gernp a1,vs18,vs19
+.*:	(ec 92 9a d0|d0 9a 92 ec) 	dmxvf32gernp a1,vs18,vs19
+.*:	(ed 14 ae d0|d0 ae 14 ed) 	dmxvf32gernn a2,vs20,vs21
+.*:	(ed 14 ae d0|d0 ae 14 ed) 	dmxvf32gernn a2,vs20,vs21
+.*:	(07 90 00 98|98 00 90 07) 	pmdmxvf32ger a3,vs22,vs23,9,8
+.*:	(ed 96 b8 d8|d8 b8 96 ed) 
+.*:	(07 90 00 98|98 00 90 07) 	pmdmxvf32ger a3,vs22,vs23,9,8
 .*:	(ed 96 b8 d8|d8 b8 96 ed) 
-.*:	(07 90 00 76|76 00 90 07) 	pmxvf32gerpp a4,vs24,vs25,7,6
+.*:	(07 90 00 76|76 00 90 07) 	pmdmxvf32gerpp a4,vs24,vs25,7,6
 .*:	(ee 18 c8 d0|d0 c8 18 ee) 
-.*:	(07 90 00 54|54 00 90 07) 	pmxvf32gerpn a5,vs26,vs27,5,4
+.*:	(07 90 00 76|76 00 90 07) 	pmdmxvf32gerpp a4,vs24,vs25,7,6
+.*:	(ee 18 c8 d0|d0 c8 18 ee) 
+.*:	(07 90 00 54|54 00 90 07) 	pmdmxvf32gerpn a5,vs26,vs27,5,4
+.*:	(ee 9a dc d0|d0 dc 9a ee) 
+.*:	(07 90 00 54|54 00 90 07) 	pmdmxvf32gerpn a5,vs26,vs27,5,4
 .*:	(ee 9a dc d0|d0 dc 9a ee) 
-.*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(07 90 00 32|32 00 90 07) 	pmxvf32gernp a6,vs28,vs29,3,2
+.*:	(07 90 00 32|32 00 90 07) 	pmdmxvf32gernp a6,vs28,vs29,3,2
+.*:	(ef 1c ea d0|d0 ea 1c ef) 
+.*:	(07 90 00 32|32 00 90 07) 	pmdmxvf32gernp a6,vs28,vs29,3,2
 .*:	(ef 1c ea d0|d0 ea 1c ef) 
-.*:	(07 90 00 10|10 00 90 07) 	pmxvf32gernn a7,vs0,vs1,1,0
+.*:	(07 90 00 10|10 00 90 07) 	pmdmxvf32gernn a7,vs0,vs1,1,0
 .*:	(ef 80 0e d0|d0 0e 80 ef) 
-.*:	(ec 04 29 d8|d8 29 04 ec) 	xvf64ger a0,vs4,vs5
-.*:	(ec 88 49 d0|d0 49 88 ec) 	xvf64gerpp a1,vs8,vs9
-.*:	(ed 02 15 d0|d0 15 02 ed) 	xvf64gerpn a2,vs2,vs2
-.*:	(ed 84 1b d0|d0 1b 84 ed) 	xvf64gernp a3,vs4,vs3
-.*:	(ee 04 27 d0|d0 27 04 ee) 	xvf64gernn a4,vs4,vs4
-.*:	(07 90 00 f0|f0 00 90 07) 	pmxvf64ger a5,vs6,vs5,15,0
+.*:	(07 90 00 10|10 00 90 07) 	pmdmxvf32gernn a7,vs0,vs1,1,0
+.*:	(ef 80 0e d0|d0 0e 80 ef) 
+.*:	(ec 04 29 d8|d8 29 04 ec) 	dmxvf64ger a0,vs4,vs5
+.*:	(ec 04 29 d8|d8 29 04 ec) 	dmxvf64ger a0,vs4,vs5
+.*:	(ec 88 49 d0|d0 49 88 ec) 	dmxvf64gerpp a1,vs8,vs9
+.*:	(ec 88 49 d0|d0 49 88 ec) 	dmxvf64gerpp a1,vs8,vs9
+.*:	(ed 02 15 d0|d0 15 02 ed) 	dmxvf64gerpn a2,vs2,vs2
+.*:	(ed 02 15 d0|d0 15 02 ed) 	dmxvf64gerpn a2,vs2,vs2
+.*:	(ed 84 1b d0|d0 1b 84 ed) 	dmxvf64gernp a3,vs4,vs3
+.*:	(ed 84 1b d0|d0 1b 84 ed) 	dmxvf64gernp a3,vs4,vs3
+.*:	(ee 04 27 d0|d0 27 04 ee) 	dmxvf64gernn a4,vs4,vs4
+.*:	(ee 04 27 d0|d0 27 04 ee) 	dmxvf64gernn a4,vs4,vs4
+.*:	(07 90 00 f0|f0 00 90 07) 	pmdmxvf64ger a5,vs6,vs5,15,0
+.*:	(ee 86 29 d8|d8 29 86 ee) 
+.*:	(07 90 00 f0|f0 00 90 07) 	pmdmxvf64ger a5,vs6,vs5,15,0
 .*:	(ee 86 29 d8|d8 29 86 ee) 
-.*:	(07 90 00 e4|e4 00 90 07) 	pmxvf64gerpp a6,vs6,vs6,14,1
+.*:	(07 90 00 e4|e4 00 90 07) 	pmdmxvf64gerpp a6,vs6,vs6,14,1
 .*:	(ef 06 31 d0|d0 31 06 ef) 
-.*:	(07 90 00 d8|d8 00 90 07) 	pmxvf64gerpn a7,vs8,vs7,13,2
+.*:	(07 90 00 e4|e4 00 90 07) 	pmdmxvf64gerpp a6,vs6,vs6,14,1
+.*:	(ef 06 31 d0|d0 31 06 ef) 
+.*:	(07 90 00 d8|d8 00 90 07) 	pmdmxvf64gerpn a7,vs8,vs7,13,2
+.*:	(ef 88 3d d0|d0 3d 88 ef) 
+.*:	(07 90 00 d8|d8 00 90 07) 	pmdmxvf64gerpn a7,vs8,vs7,13,2
 .*:	(ef 88 3d d0|d0 3d 88 ef) 
-.*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(07 90 00 cc|cc 00 90 07) 	pmxvf64gernp a0,vs4,vs5,12,3
+.*:	(07 90 00 cc|cc 00 90 07) 	pmdmxvf64gernp a0,vs4,vs5,12,3
 .*:	(ec 04 2b d0|d0 2b 04 ec) 
-.*:	(07 90 00 a0|a0 00 90 07) 	pmxvf64gernn a1,vs2,vs1,10,0
+.*:	(07 90 00 cc|cc 00 90 07) 	pmdmxvf64gernp a0,vs4,vs5,12,3
+.*:	(ec 04 2b d0|d0 2b 04 ec) 
+.*:	(07 90 00 a0|a0 00 90 07) 	pmdmxvf64gernn a1,vs2,vs1,10,0
+.*:	(ec 82 0f d0|d0 0f 82 ec) 
+.*:	(07 90 00 a0|a0 00 90 07) 	pmdmxvf64gernn a1,vs2,vs1,10,0
 .*:	(ec 82 0f d0|d0 0f 82 ec) 
-.*:	(ed 03 21 90|90 21 03 ed) 	xvbf16ger2pp a2,vs3,vs4
-.*:	(ed 84 29 98|98 29 84 ed) 	xvbf16ger2 a3,vs4,vs5
-.*:	(ee 05 33 90|90 33 05 ee) 	xvbf16ger2np a4,vs5,vs6
-.*:	(ee 86 3d 90|90 3d 86 ee) 	xvbf16ger2pn a5,vs6,vs7
-.*:	(ef 07 47 90|90 47 07 ef) 	xvbf16ger2nn a6,vs7,vs8
-.*:	(07 90 c0 ff|ff c0 90 07) 	pmxvbf16ger2pp a7,vs8,vs9,15,15,3
+.*:	(ed 03 21 90|90 21 03 ed) 	dmxvbf16ger2pp a2,vs3,vs4
+.*:	(ed 03 21 90|90 21 03 ed) 	dmxvbf16ger2pp a2,vs3,vs4
+.*:	(ed 84 29 98|98 29 84 ed) 	dmxvbf16ger2 a3,vs4,vs5
+.*:	(ed 84 29 98|98 29 84 ed) 	dmxvbf16ger2 a3,vs4,vs5
+.*:	(ee 05 33 90|90 33 05 ee) 	dmxvbf16ger2np a4,vs5,vs6
+.*:	(ee 05 33 90|90 33 05 ee) 	dmxvbf16ger2np a4,vs5,vs6
+.*:	(ee 86 3d 90|90 3d 86 ee) 	dmxvbf16ger2pn a5,vs6,vs7
+.*:	(ee 86 3d 90|90 3d 86 ee) 	dmxvbf16ger2pn a5,vs6,vs7
+.*:	(ef 07 47 90|90 47 07 ef) 	dmxvbf16ger2nn a6,vs7,vs8
+.*:	(ef 07 47 90|90 47 07 ef) 	dmxvbf16ger2nn a6,vs7,vs8
+.*:	(07 90 c0 ff|ff c0 90 07) 	pmdmxvbf16ger2pp a7,vs8,vs9,15,15,3
+.*:	(ef 88 49 90|90 49 88 ef) 
+.*:	(07 90 c0 ff|ff c0 90 07) 	pmdmxvbf16ger2pp a7,vs8,vs9,15,15,3
 .*:	(ef 88 49 90|90 49 88 ef) 
-.*:	(07 90 80 cc|cc 80 90 07) 	pmxvbf16ger2 a0,vs9,vs10,12,12,2
+.*:	(07 90 80 cc|cc 80 90 07) 	pmdmxvbf16ger2 a0,vs9,vs10,12,12,2
 .*:	(ec 09 51 98|98 51 09 ec) 
-.*:	(07 90 40 aa|aa 40 90 07) 	pmxvbf16ger2np a1,vs10,vs11,10,10,1
+.*:	(07 90 80 cc|cc 80 90 07) 	pmdmxvbf16ger2 a0,vs9,vs10,12,12,2
+.*:	(ec 09 51 98|98 51 09 ec) 
+.*:	(07 90 40 aa|aa 40 90 07) 	pmdmxvbf16ger2np a1,vs10,vs11,10,10,1
+.*:	(ec 8a 5b 90|90 5b 8a ec) 
+.*:	(07 90 40 aa|aa 40 90 07) 	pmdmxvbf16ger2np a1,vs10,vs11,10,10,1
 .*:	(ec 8a 5b 90|90 5b 8a ec) 
-.*:	(60 00 00 00|00 00 00 60) 	nop
-.*:	(07 90 00 dd|dd 00 90 07) 	pmxvbf16ger2pn a2,vs12,vs13,13,13,0
+.*:	(07 90 00 dd|dd 00 90 07) 	pmdmxvbf16ger2pn a2,vs12,vs13,13,13,0
 .*:	(ed 0c 6d 90|90 6d 0c ed) 
-.*:	(07 90 c0 ee|ee c0 90 07) 	pmxvbf16ger2nn a3,vs16,vs17,14,14,3
+.*:	(07 90 00 dd|dd 00 90 07) 	pmdmxvbf16ger2pn a2,vs12,vs13,13,13,0
+.*:	(ed 0c 6d 90|90 6d 0c ed) 
+.*:	(07 90 c0 ee|ee c0 90 07) 	pmdmxvbf16ger2nn a3,vs16,vs17,14,14,3
+.*:	(ed 90 8f 90|90 8f 90 ed) 
+.*:	(07 90 c0 ee|ee c0 90 07) 	pmdmxvbf16ger2nn a3,vs16,vs17,14,14,3
 .*:	(ed 90 8f 90|90 8f 90 ed) 
-.*:	(ee 00 0b 1e|1e 0b 00 ee) 	xvi8ger4spp a4,vs32,vs33
-.*:	(07 90 f0 ff|ff f0 90 07) 	pmxvi8ger4spp a5,vs34,vs35,15,15,15
+.*:	(ee 00 0b 1e|1e 0b 00 ee) 	dmxvi8ger4spp a4,vs32,vs33
+.*:	(ee 00 0b 1e|1e 0b 00 ee) 	dmxvi8ger4spp a4,vs32,vs33
+.*:	(07 90 f0 ff|ff f0 90 07) 	pmdmxvi8ger4spp a5,vs34,vs35,15,15,15
 .*:	(ee 82 1b 1e|1e 1b 82 ee) 
-.*:	(ef 04 2a 5e|5e 2a 04 ef) 	xvi16ger2 a6,vs36,vs37
-.*:	(ef 86 3b 5e|5e 3b 86 ef) 	xvi16ger2pp a7,vs38,vs39
-.*:	(07 90 40 ff|ff 40 90 07) 	pmxvi16ger2 a0,vs38,vs39,15,15,1
+.*:	(07 90 f0 ff|ff f0 90 07) 	pmdmxvi8ger4spp a5,vs34,vs35,15,15,15
+.*:	(ee 82 1b 1e|1e 1b 82 ee) 
+.*:	(ef 04 2a 5e|5e 2a 04 ef) 	dmxvi16ger2 a6,vs36,vs37
+.*:	(ef 04 2a 5e|5e 2a 04 ef) 	dmxvi16ger2 a6,vs36,vs37
+.*:	(ef 86 3b 5e|5e 3b 86 ef) 	dmxvi16ger2pp a7,vs38,vs39
+.*:	(ef 86 3b 5e|5e 3b 86 ef) 	dmxvi16ger2pp a7,vs38,vs39
+.*:	(07 90 40 ff|ff 40 90 07) 	pmdmxvi16ger2 a0,vs38,vs39,15,15,1
+.*:	(ec 06 3a 5e|5e 3a 06 ec) 
+.*:	(07 90 40 ff|ff 40 90 07) 	pmdmxvi16ger2 a0,vs38,vs39,15,15,1
 .*:	(ec 06 3a 5e|5e 3a 06 ec) 
-.*:	(07 90 80 cc|cc 80 90 07) 	pmxvi16ger2pp a1,vs40,vs41,12,12,2
+.*:	(07 90 80 cc|cc 80 90 07) 	pmdmxvi16ger2pp a1,vs40,vs41,12,12,2
+.*:	(ec 88 4b 5e|5e 4b 88 ec) 
+.*:	(07 90 80 cc|cc 80 90 07) 	pmdmxvi16ger2pp a1,vs40,vs41,12,12,2
 .*:	(ec 88 4b 5e|5e 4b 88 ec) 
 #pass
diff --git a/gas/testsuite/gas/ppc/outerprod.s b/gas/testsuite/gas/ppc/outerprod.s
index 1f02c158daa..dd947fe9720 100644
--- a/gas/testsuite/gas/ppc/outerprod.s
+++ b/gas/testsuite/gas/ppc/outerprod.s
@@ -1,63 +1,124 @@
 	.text
 _start:
 	xxmfacc	5
+	dmxxmfacc 5
 	xxmtacc 6
+	dmxxmtacc 6
 	xxsetaccz 7
+	dmsetaccz 7
 	xvi4ger8 0,63,62
+	dmxvi4ger8 0,63,62
 	xvi4ger8pp 1,61,60
+	dmxvi4ger8pp 1,61,60
 	pmxvi4ger8 2,59,58,15,14,255
+	pmdmxvi4ger8 2,59,58,15,14,255
 	pmxvi4ger8pp 3,57,56,7,8,128
+	pmdmxvi4ger8pp 3,57,56,7,8,128
 	xvi8ger4 4,55,54
+	dmxvi8ger4 4,55,54
 	xvi8ger4pp 5,53,52
+	dmxvi8ger4pp 5,53,52
 	pmxvi8ger4 6,51,50,13,12,11
+	pmdmxvi8ger4 6,51,50,13,12,11
 	pmxvi8ger4pp 7,49,48,10,9,8
+	pmdmxvi8ger4pp 7,49,48,10,9,8
 	xvi16ger2s 0,47,46
+	dmxvi16ger2s 0,47,46
 	xvi16ger2spp 1,45,44
+	dmxvi16ger2spp 1,45,44
 	pmxvi16ger2s 2,43,42,7,6,3
+	pmdmxvi16ger2s 2,43,42,7,6,3
 	pmxvi16ger2spp 3,41,40,5,4,2
+	pmdmxvi16ger2spp 3,41,40,5,4,2
 	xvf16ger2 4,39,38
+	dmxvf16ger2 4,39,38
 	xvf16ger2pp 5,37,36
+	dmxvf16ger2pp 5,37,36
 	xvf16ger2pn 6,35,34
+	dmxvf16ger2pn 6,35,34
 	xvf16ger2np 7,33,32
+	dmxvf16ger2np 7,33,32
 	xvf16ger2nn 0,4,5
+	dmxvf16ger2nn 0,4,5
 	pmxvf16ger2 1,2,3,3,2,1
+	pmdmxvf16ger2 1,2,3,3,2,1
 	pmxvf16ger2pp 2,4,5,1,0,0
+	pmdmxvf16ger2pp 2,4,5,1,0,0
 	pmxvf16ger2pn 3,6,7,15,14,3
+	pmdmxvf16ger2pn 3,6,7,15,14,3
 	pmxvf16ger2np 4,8,9,13,12,2
+	pmdmxvf16ger2np 4,8,9,13,12,2
 	pmxvf16ger2nn 5,10,11,11,10,1
+	pmdmxvf16ger2nn 5,10,11,11,10,1
 	xvf32ger 6,12,13
+	dmxvf32ger 6,12,13
 	xvf32gerpp 7,14,15
+	dmxvf32gerpp 7,14,15
 	xvf32gerpn 0,16,17
+	dmxvf32gerpn 0,16,17
 	xvf32gernp 1,18,19
+	dmxvf32gernp 1,18,19
 	xvf32gernn 2,20,21
+	dmxvf32gernn 2,20,21
 	pmxvf32ger 3,22,23,9,8
+	pmdmxvf32ger 3,22,23,9,8
 	pmxvf32gerpp 4,24,25,7,6
+	pmdmxvf32gerpp 4,24,25,7,6
 	pmxvf32gerpn 5,26,27,5,4
+	pmdmxvf32gerpn 5,26,27,5,4
 	pmxvf32gernp 6,28,29,3,2
+	pmdmxvf32gernp 6,28,29,3,2
 	pmxvf32gernn 7,0,1,1,0
+	pmdmxvf32gernn 7,0,1,1,0
 	xvf64ger 0,4,5
+	dmxvf64ger 0,4,5
 	xvf64gerpp 1,8,9
+	dmxvf64gerpp 1,8,9
 	xvf64gerpn 2,2,2
+	dmxvf64gerpn 2,2,2
 	xvf64gernp 3,4,3
+	dmxvf64gernp 3,4,3
 	xvf64gernn 4,4,4
+	dmxvf64gernn 4,4,4
 	pmxvf64ger 5,6,5,15,0
+	pmdmxvf64ger 5,6,5,15,0
 	pmxvf64gerpp 6,6,6,14,1
+	pmdmxvf64gerpp 6,6,6,14,1
 	pmxvf64gerpn 7,8,7,13,2
+	pmdmxvf64gerpn 7,8,7,13,2
 	pmxvf64gernp 0,4,5,12,3
+	pmdmxvf64gernp 0,4,5,12,3
 	pmxvf64gernn 1,2,1,10,0
+	pmdmxvf64gernn 1,2,1,10,0
 	xvbf16ger2pp 2,3,4
+	dmxvbf16ger2pp 2,3,4
 	xvbf16ger2 3,4,5
+	dmxvbf16ger2 3,4,5
 	xvbf16ger2np 4,5,6
+	dmxvbf16ger2np 4,5,6
 	xvbf16ger2pn 5,6,7
+	dmxvbf16ger2pn 5,6,7
 	xvbf16ger2nn 6,7,8
+	dmxvbf16ger2nn 6,7,8
 	pmxvbf16ger2pp 7,8,9,15,15,3
+	pmdmxvbf16ger2pp 7,8,9,15,15,3
 	pmxvbf16ger2 0,9,10,12,12,2
+	pmdmxvbf16ger2 0,9,10,12,12,2
 	pmxvbf16ger2np 1,10,11,10,10,1
+	pmdmxvbf16ger2np 1,10,11,10,10,1
 	pmxvbf16ger2pn 2,12,13,13,13,0
+	pmdmxvbf16ger2pn 2,12,13,13,13,0
 	pmxvbf16ger2nn 3,16,17,14,14,3
+	pmdmxvbf16ger2nn 3,16,17,14,14,3
 	xvi8ger4spp 4,32,33
+	dmxvi8ger4spp 4,32,33
 	pmxvi8ger4spp 5,34,35,15,15,15
+	pmdmxvi8ger4spp 5,34,35,15,15,15
 	xvi16ger2 6,36,37
+	dmxvi16ger2 6,36,37
 	xvi16ger2pp 7,38,39
+	dmxvi16ger2pp 7,38,39
 	pmxvi16ger2 0,38,39,15,15,1
+	pmdmxvi16ger2 0,38,39,15,15,1
 	pmxvi16ger2pp 1,40,41,12,12,2
+	pmdmxvi16ger2pp 1,40,41,12,12,2
diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp
index ae8a7b61cde..f27a79cfd73 100644
--- a/gas/testsuite/gas/ppc/ppc.exp
+++ b/gas/testsuite/gas/ppc/ppc.exp
@@ -145,6 +145,7 @@ run_dump_test "rightmost"
 run_dump_test "scalarquad"
 run_dump_test "rop"
 run_dump_test "rop-checks"
+run_dump_test "rfc02653"
 
 run_dump_test "dcbt"
 run_dump_test "pr27676"
diff --git a/gas/testsuite/gas/ppc/rfc02653.d b/gas/testsuite/gas/ppc/rfc02653.d
new file mode 100644
index 00000000000..6ad49df9c04
--- /dev/null
+++ b/gas/testsuite/gas/ppc/rfc02653.d
@@ -0,0 +1,27 @@
+#as: -mfuture
+#objdump: -dr -Mfuture
+#name: RFC02653 tests
+
+.*
+
+
+Disassembly of section \.text:
+
+0+0 <_start>:
+.*:	(62 01 02 7c|7c 02 01 62) 	dmsetdmrz dm0
+.*:	(62 41 86 7c|7c 86 41 62) 	dmmr    dm1,dm2
+.*:	(62 61 07 7d|7d 07 61 62) 	dmxor   dm2,dm3
+.*:	(10 17 00 f2|f2 00 17 10) 	dmxxextfdmr512 vs0,vs2,dm4,0
+.*:	(10 37 85 f2|f2 85 37 10) 	dmxxextfdmr512 vs4,vs6,dm5,1
+.*:	(50 57 08 f3|f3 08 57 50) 	dmxxinstdmr512 dm6,vs8,vs10,0
+.*:	(50 57 89 f3|f3 89 57 50) 	dmxxinstdmr512 dm7,vs8,vs10,1
+.*:	(90 67 00 f0|f0 00 67 90) 	dmxxextfdmr256 vs12,dm0,0
+.*:	(90 7f 80 f0|f0 80 7f 90) 	dmxxextfdmr256 vs14,dm1,1
+.*:	(90 87 01 f1|f1 01 87 90) 	dmxxextfdmr256 vs16,dm2,2
+.*:	(90 9f 81 f1|f1 81 9f 90) 	dmxxextfdmr256 vs18,dm3,3
+.*:	(94 a7 00 f2|f2 00 a7 94) 	dmxxinstdmr256 dm4,vs20,0
+.*:	(94 bf 80 f2|f2 80 bf 94) 	dmxxinstdmr256 dm5,vs22,1
+.*:	(94 c7 01 f3|f3 01 c7 94) 	dmxxinstdmr256 dm6,vs24,2
+.*:	(94 df 81 f3|f3 81 df 94) 	dmxxinstdmr256 dm7,vs26,3
+.*:	(18 09 00 ec|ec 00 09 18) 	dmxvi4ger8 a0,vs0,vs1
+#pass
diff --git a/gas/testsuite/gas/ppc/rfc02653.s b/gas/testsuite/gas/ppc/rfc02653.s
new file mode 100644
index 00000000000..8b343d6cbfc
--- /dev/null
+++ b/gas/testsuite/gas/ppc/rfc02653.s
@@ -0,0 +1,18 @@
+	.text
+_start:
+	dmsetdmrz	0
+	dmmr		1,2
+	dmxor		2,3
+	dmxxextfdmr512	0,2,4,0
+	dmxxextfdmr512	4,6,5,1
+	dmxxinstdmr512	6,8,10,0
+	dmxxinstdmr512	7,8,10,1
+	dmxxextfdmr256	12,0,0
+	dmxxextfdmr256	14,1,1
+	dmxxextfdmr256	16,2,2
+	dmxxextfdmr256	18,3,3
+	dmxxinstdmr256	4,20,0
+	dmxxinstdmr256	5,22,1
+	dmxxinstdmr256	6,24,2
+	dmxxinstdmr256	7,26,3
+	dmxvi4ger8 0,0,1	# VSRs can now overlap the ACCs
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 930d13d3026..004b51db670 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -384,6 +384,9 @@ extern const unsigned int num_powerpc_operands;
 /* This operand names a VSX accumulator.  */
 #define PPC_OPERAND_ACC (0x20)
 
+/* This operand names a dense math register.  */
+#define PPC_OPERAND_DMR (0x40)
+
 /* This operand may use the symbolic names for the CR fields (even
    without -mregnames), which are
        lt  0	gt  1	eq  2	so  3	un  3
@@ -391,60 +394,60 @@ extern const unsigned int num_powerpc_operands;
        cr4 4	cr5 5	cr6 6	cr7 7
    These may be combined arithmetically, as in cr2*4+gt.  These are
    only supported on the PowerPC, not the POWER.  */
-#define PPC_OPERAND_CR_BIT (0x40)
+#define PPC_OPERAND_CR_BIT (0x80)
 
 /* This is a CR FIELD that does not use symbolic names (unless
    -mregnames is in effect).  If both PPC_OPERAND_CR_BIT and
    PPC_OPERAND_CR_REG are set then treat the field as per
    PPC_OPERAND_CR_BIT for assembly, but as if neither of these
    bits are set for disassembly.  */
-#define PPC_OPERAND_CR_REG (0x80)
+#define PPC_OPERAND_CR_REG (0x100)
 
 /* This operand names a special purpose register.  */
-#define PPC_OPERAND_SPR (0x100)
+#define PPC_OPERAND_SPR (0x200)
 
 /* This operand names a paired-single graphics quantization register.  */
-#define PPC_OPERAND_GQR (0x200)
+#define PPC_OPERAND_GQR (0x400)
 
 /* This operand is a relative branch displacement.  The disassembler
    prints these symbolically if possible.  */
-#define PPC_OPERAND_RELATIVE (0x400)
+#define PPC_OPERAND_RELATIVE (0x800)
 
 /* This operand is an absolute branch address.  The disassembler
    prints these symbolically if possible.  */
-#define PPC_OPERAND_ABSOLUTE (0x800)
+#define PPC_OPERAND_ABSOLUTE (0x1000)
 
 /* This operand takes signed values.  */
-#define PPC_OPERAND_SIGNED (0x1000)
+#define PPC_OPERAND_SIGNED (0x2000)
 
 /* This operand takes signed values, but also accepts a full positive
    range of values when running in 32 bit mode.  That is, if bits is
    16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
    this flag is ignored.  */
-#define PPC_OPERAND_SIGNOPT (0x2000)
+#define PPC_OPERAND_SIGNOPT (0x4000)
 
 /* The next operand should be wrapped in parentheses rather than
    separated from this one by a comma.  This is used for the load and
    store instructions which want their operands to look like
        reg,displacement(reg)
    */
-#define PPC_OPERAND_PARENS (0x4000)
+#define PPC_OPERAND_PARENS (0x8000)
 
 /* This operand is for the DS field in a DS form instruction.  */
-#define PPC_OPERAND_DS (0x8000)
+#define PPC_OPERAND_DS (0x10000)
 
 /* This operand is for the DQ field in a DQ form instruction.  */
-#define PPC_OPERAND_DQ (0x10000)
+#define PPC_OPERAND_DQ (0x20000)
 
 /* This operand should be regarded as a negative number for the
    purposes of overflow checking (i.e., the normal most negative
    number is disallowed and one more than the normal most positive
    number is allowed).  This flag will only be set for a signed
    operand.  */
-#define PPC_OPERAND_NEGATIVE (0x20000)
+#define PPC_OPERAND_NEGATIVE (0x40000)
 
 /* Valid range of operand is 0..n rather than 0..n-1.  */
-#define PPC_OPERAND_PLUS1 (0x40000)
+#define PPC_OPERAND_PLUS1 (0x80000)
 
 /* This operand is optional, and is zero if omitted.  This is used for
    example, in the optional BF field in the comparison instructions.  The
@@ -452,7 +455,7 @@ extern const unsigned int num_powerpc_operands;
    and the number of operands remaining for the opcode, and decide
    whether this operand is present or not.  The disassembler should
    print this operand out only if it is not zero.  */
-#define PPC_OPERAND_OPTIONAL (0x80000)
+#define PPC_OPERAND_OPTIONAL (0x100000)
 
 /* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
    is omitted, then for the next operand use this operand value plus
@@ -460,7 +463,7 @@ extern const unsigned int num_powerpc_operands;
    hack is needed because the Power rotate instructions can take
    either 4 or 5 operands.  The disassembler should print this operand
    out regardless of the PPC_OPERAND_OPTIONAL field.  */
-#define PPC_OPERAND_NEXT (0x100000)
+#define PPC_OPERAND_NEXT (0x200000)
 
 /* This flag is only used with PPC_OPERAND_OPTIONAL.  The operand is
    only optional when generating 32-bit code.  */
diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c
index 33a96701ca8..69466661800 100644
--- a/opcodes/ppc-dis.c
+++ b/opcodes/ppc-dis.c
@@ -1097,6 +1097,9 @@ print_insn_powerpc (bfd_vma memaddr,
 	  else if ((operand->flags & PPC_OPERAND_VSR) != 0)
 	    (*info->fprintf_styled_func) (info->stream, dis_style_register,
 					  "vs%" PRId64, value);
+	  else if ((operand->flags & PPC_OPERAND_DMR) != 0)
+	    (*info->fprintf_styled_func) (info->stream, dis_style_register,
+					  "dm%" PRId64, value);
 	  else if ((operand->flags & PPC_OPERAND_ACC) != 0)
 	    (*info->fprintf_styled_func) (info->stream, dis_style_register,
 					  "a%" PRId64, value);
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index b470ebd0aa9..c323a2761e3 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1477,6 +1477,26 @@ extract_pl (uint64_t insn,
   return value;
 }
 
+/* The 2-bit P field in a MMA XX2-form instruction.  This is split.  */
+
+static uint64_t
+insert_p2 (uint64_t insn,
+	   int64_t value,
+	   ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	   const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0x2) << 15) | ((value & 0x1) << 11);
+}
+
+static int64_t
+extract_p2 (uint64_t insn,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    int *invalid ATTRIBUTE_UNUSED)
+{
+  uint64_t value = ((insn >> 15) & 0x2) | ((insn >> 11) & 0x1);
+  return value;
+}
+
 /* The RA field in a D or X form instruction which is an updating
    load, which means that the RA field may not be zero and may not
    equal the RT field.  */
@@ -2129,6 +2149,25 @@ extract_xtq6 (uint64_t insn,
   return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f);
 }
 
+/* The 5-bit XAp field in an XX3 form instruction.  This is split.  */
+
+static uint64_t
+insert_xa5 (uint64_t insn,
+	    int64_t value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0x1e) << 16) | ((value & 0x20) >> 3);
+}
+
+static int64_t
+extract_xa5 (uint64_t insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1e);
+}
+
 /* The XA field in an XX3 form instruction.  This is split.  */
 
 static uint64_t
@@ -2158,7 +2197,9 @@ insert_xa6a (uint64_t insn,
 	     const char **errmsg)
 {
   int64_t acc = (insn >> 23) & 0x7;
-  if ((value >> 2) == acc)
+  /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions.  */
+  if ((dialect & PPC_OPCODE_FUTURE) == 0
+      && (value >> 2) == acc)
     *errmsg = _("VSR overlaps ACC operand");
   return insert_xa6 (insn, value, dialect, errmsg);
 }
@@ -2170,11 +2211,31 @@ extract_xa6a (uint64_t insn,
 {
   int64_t acc = (insn >> 23) & 0x7;
   int64_t value = extract_xa6 (insn, dialect, invalid);
-  if ((value >> 2) == acc)
+  /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions.  */
+  if ((dialect & PPC_OPCODE_FUTURE) == 0
+      && (value >> 2) == acc)
     *invalid = 1;
   return value;
 }
 
+/* The 5-bit XB field in an XX3 form instruction.  This is split.  */
+
+static uint64_t
+insert_xb5 (uint64_t insn,
+	    int64_t value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0x1e) << 11) | ((value & 0x20) >> 4);
+}
+
+static int64_t
+extract_xb5 (uint64_t insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1e);
+}
 /* The XB field in an XX3 form instruction.  This is split.  */
 
 static uint64_t
@@ -2204,7 +2265,9 @@ insert_xb6a (uint64_t insn,
 	     const char **errmsg)
 {
   int64_t acc = (insn >> 23) & 0x7;
-  if ((value >> 2) == acc)
+  /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions.  */
+  if ((dialect & PPC_OPCODE_FUTURE) == 0
+      && (value >> 2) == acc)
     *errmsg = _("VSR overlaps ACC operand");
   return insert_xb6 (insn, value, dialect, errmsg);
 }
@@ -2216,7 +2279,9 @@ extract_xb6a (uint64_t insn,
 {
   int64_t acc = (insn >> 23) & 0x7;
   int64_t value = extract_xb6 (insn, dialect, invalid);
-  if ((value >> 2) == acc)
+  /* Power10 doesn't allow VSRs to overlap ACCs in MMA instructions.  */
+  if ((dialect & PPC_OPCODE_FUTURE) == 0
+      && (value >> 2) == acc)
     *invalid = 1;
   return value;
 }
@@ -2824,9 +2889,17 @@ const struct powerpc_operand powerpc_operands[] =
 #define ACC BFF + 1
   { 0x7, 23, NULL, NULL, PPC_OPERAND_ACC },
 
+  /* The DMR field in a MMA instruction.  */
+#define DMR ACC + 1
+  { 0x7, 23, NULL, NULL, PPC_OPERAND_DMR },
+
+  /* The second DMR field in a two DMR operand MMA instruction.  */
+#define DMRAB DMR + 1
+  { 0x7, 13, NULL, NULL, PPC_OPERAND_DMR },
+
   /* An optional BF field.  This is used for comparison instructions,
      in which an omitted BF field is taken as zero.  */
-#define OBF ACC + 1
+#define OBF DMRAB + 1
   { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 
   /* The BFA field in an X or XL form instruction.  */
@@ -3656,6 +3729,7 @@ const struct powerpc_operand powerpc_operands[] =
 
 #define R RMC + 1
 #define MP R
+#define P1 R
   { 0x1, 16, NULL, NULL, 0 },
 
 #define RIC R + 1
@@ -3769,8 +3843,13 @@ const struct powerpc_operand powerpc_operands[] =
 #define XA6ap XA6a + 1
   { 0x3e, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR },
 
+  /* The 5-bit XAp field in an MMA XX3 form instruction.  This is split.
+     This is like XA6, but must be even.  */
+#define XA5p XA6ap + 1
+  { 0x3e, PPC_OPSHIFT_INV, insert_xa5, extract_xa5, PPC_OPERAND_VSR },
+
   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
-#define XB6 XA6ap + 1
+#define XB6 XA5p + 1
   { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 
   /* The XB field in an XX3 form instruction.  This is split and
@@ -3778,9 +3857,14 @@ const struct powerpc_operand powerpc_operands[] =
 #define XB6a XB6 + 1
   { 0x3f, PPC_OPSHIFT_INV, insert_xb6a, extract_xb6a, PPC_OPERAND_VSR },
 
+  /* The 5-bit XBp field in an MMA XX3 form instruction.  This is split.
+     This is like XB6, but must be even.  */
+#define XB5p XB6a + 1
+  { 0x3e, PPC_OPSHIFT_INV, insert_xb5, extract_xb5, PPC_OPERAND_VSR },
+
   /* The XA and XB fields in an XX3 form instruction when they must be the same.
      This is used in extended mnemonics like xvmovdp.  This is split.  */
-#define XAB6 XB6a + 1
+#define XAB6 XB5p + 1
   { 0x3f, PPC_OPSHIFT_INV, insert_xab6, extract_xab6, PPC_OPERAND_VSR },
 
   /* The XC field in an XX4 form instruction.  This is split.  */
@@ -3815,8 +3899,11 @@ const struct powerpc_operand powerpc_operands[] =
 #define PL SC2
   { 0x3, 16, insert_pl, extract_pl, PPC_OPERAND_OPTIONAL },
 
+#define P2 PL + 1
+  { 0x3, PPC_OPSHIFT_INV, insert_p2, extract_p2, 0 },
+
   /* The 8-bit IMM8 field in a XX1 form instruction.  */
-#define IMM8 SC2 + 1
+#define IMM8 P2 + 1
   { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT },
 
 #define VX_OFF IMM8 + 1
@@ -4452,15 +4539,22 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
 
 /* An X_MASK with an accumulator register and the RA and RB fields fixed.  */
 #define XACC_MASK (X_MASK | RA_MASK | RB_MASK | (3 << 21))
+#define XDMR_MASK XACC_MASK
 
-/* The mask for an XX3 form instruction with an accumulator register.  */
-#define XX3ACC_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1))
+/* An X_MASK with two dense math register.  */
+#define XDMRDMR_MASK (X_MASK | RA_MASK | (3 << 21) | (3 << 11))
 
 /* The mask for an XX3 form instruction with the DM or SHW bits
    specified.  */
 #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
 #define XX3SHW_MASK XX3DM_MASK
 
+/* The masks for X* form instructions with an ACC/DMR register.  */
+#define XX2ACC_MASK (XX2 (0x3f, 0x1ff) | (3 << 21) | 1)
+#define XX3ACC_MASK (XX3_MASK | (3 << 21) | 1)
+#define XX3DMR_MASK (XX3ACC_MASK | (1 << 11))
+#define XX2DMR_MASK (XX2ACC_MASK | (0xf << 17))
+
 /* The mask for an XX4 form instruction.  */
 #define XX4_MASK XX4 (0x3f, 0x3)
 
@@ -7245,9 +7339,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"msgclrp",	XRTRA(31,174,0,0), XRTRA_MASK, POWER8,	0,		{RB}},
 {"dcbtlse",	X(31,174),	X_MASK,	     PPCCHLK,	E500MC,		{CT, RA0, RB}},
 
+{"dmxxmfacc",	XVA(31,177,0),	XACC_MASK,   POWER10, 0,		{ACC}},
 {"xxmfacc",	XVA(31,177,0),	XACC_MASK,   POWER10, 0,		{ACC}},
+{"dmxxmtacc",	XVA(31,177,1),	XACC_MASK,   POWER10, 0,		{ACC}},
 {"xxmtacc",	XVA(31,177,1),	XACC_MASK,   POWER10, 0,		{ACC}},
+{"dmsetdmrz",	XVA(31,177,2),	XDMR_MASK,   FUTURE,  0,		{DMR}},
+{"dmsetaccz",	XVA(31,177,3),	XACC_MASK,   POWER10, 0,		{ACC}},
 {"xxsetaccz",	XVA(31,177,3),	XACC_MASK,   POWER10, 0,		{ACC}},
+{"dmmr",	XVA(31,177,6),	XDMRDMR_MASK,FUTURE,  0,		{DMR, DMRAB}},
+{"dmxor",	XVA(31,177,7),	XDMRDMR_MASK,FUTURE,  0,		{DMR, DMRAB}},
 
 {"mtmsrd",	X(31,178),	XRLARB_MASK, PPC64,	0,		{RS, A_L}},
 
@@ -8888,7 +8988,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dqua",	ZRC(59,3,0),	Z2_MASK,     POWER6,	PPCVLE,		{FRT,FRA,FRB,RMC}},
 {"dqua.",	ZRC(59,3,1),	Z2_MASK,     POWER6,	PPCVLE,		{FRT,FRA,FRB,RMC}},
 
+{"dmxvi8ger4pp",XX3(59,2),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvi8ger4pp",	XX3(59,2),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvi8ger4",	XX3(59,3),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvi8ger4",	XX3(59,3),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"fdivs",	A(59,18,0),	AFRC_MASK,   PPC,	PPCEFS|PPCVLE,	{FRT, FRA, FRB}},
@@ -8940,8 +9042,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dquai",	ZRC(59,67,0),	Z2_MASK,     POWER6,	PPCVLE,		{TE, FRT,FRB,RMC}},
 {"dquai.",	ZRC(59,67,1),	Z2_MASK,     POWER6,	PPCVLE,		{TE, FRT,FRB,RMC}},
 
-{"xvf16ger2pp",	XX3(59,18),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
-{"xvf16ger2",	XX3(59,19),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvf16ger2pp",XX3(59,18),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvf16ger2pp",	 XX3(59,18),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvf16ger2",	 XX3(59,19),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvf16ger2",	 XX3(59,19),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"dscri",	ZRC(59,98,0),	Z_MASK,	     POWER6,	PPCVLE,		{FRT, FRA, SH16}},
 {"dscri.",	ZRC(59,98,1),	Z_MASK,	     POWER6,	PPCVLE,		{FRT, FRA, SH16}},
@@ -8949,30 +9053,40 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"drintx",	ZRC(59,99,0),	Z2_MASK,     POWER6,	PPCVLE,		{R, FRT, FRB, RMC}},
 {"drintx.",	ZRC(59,99,1),	Z2_MASK,     POWER6,	PPCVLE,		{R, FRT, FRB, RMC}},
 
+{"dmxvf32gerpp",XX3(59,26),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvf32gerpp",	XX3(59,26),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvf32ger",	XX3(59,27),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvf32ger",	XX3(59,27),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"dcmpo",	X(59,130),	X_MASK,	     POWER6,	PPCVLE,		{BF,  FRA, FRB}},
 
+{"dmxvi4ger8pp",XX3(59,34),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvi4ger8pp",	XX3(59,34),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvi4ger8",	XX3(59,35),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvi4ger8",	XX3(59,35),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"dtstex",	X(59,162),	X_MASK,	     POWER6,	PPCVLE,		{BF,  FRA, FRB}},
 
-{"xvi16ger2spp",XX3(59,42),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
-{"xvi16ger2s",	XX3(59,43),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvi16ger2spp",XX3(59,42),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvi16ger2spp",  XX3(59,42),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvi16ger2s",  XX3(59,43),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvi16ger2s",	  XX3(59,43),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"dtstdc",	Z(59,194),	Z_MASK,	     POWER6,	PPCVLE,		{BF,  FRA, DCM}},
 
-{"xvbf16ger2pp",XX3(59,50),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
-{"xvbf16ger2",	XX3(59,51),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvbf16ger2pp",XX3(59,50),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvbf16ger2pp",  XX3(59,50),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvbf16ger2",  XX3(59,51),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvbf16ger2",	  XX3(59,51),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"dtstdg",	Z(59,226),	Z_MASK,	     POWER6,	PPCVLE,		{BF,  FRA, DGM}},
 
 {"drintn",	ZRC(59,227,0),	Z2_MASK,     POWER6,	PPCVLE,		{R, FRT, FRB, RMC}},
 {"drintn.",	ZRC(59,227,1),	Z2_MASK,     POWER6,	PPCVLE,		{R, FRT, FRB, RMC}},
 
+{"dmxvf64gerpp",XX3(59,58),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
 {"xvf64gerpp",	XX3(59,58),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
+{"dmxvf64ger",	XX3(59,59),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
 {"xvf64ger",	XX3(59,59),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
 
 {"dctdp",	XRC(59,258,0),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRB}},
@@ -8984,22 +9098,29 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ddedpd",	XRC(59,322,0),	X_MASK,	     POWER6,	PPCVLE,		{SP, FRT, FRB}},
 {"ddedpd.",	XRC(59,322,1),	X_MASK,	     POWER6,	PPCVLE,		{SP, FRT, FRB}},
 
+{"dmxvi16ger2",	XX3(59,75),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvi16ger2",	XX3(59,75),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
-{"xvf16ger2np",	XX3(59,82),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvf16ger2np", XX3(59,82),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvf16ger2np",	  XX3(59,82),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"dxex",	XRC(59,354,0),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRB}},
 {"dxex.",	XRC(59,354,1),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRB}},
 
-{"xvf32gernp",	XX3(59,90),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvf32gernp",  XX3(59,90),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvf32gernp",	  XX3(59,90),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
-{"xvi8ger4spp",	XX3(59,99),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvi8ger4spp", XX3(59,99),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvi8ger4spp",	  XX3(59,99),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
-{"xvi16ger2pp",	XX3(59,107),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvi16ger2pp", XX3(59,107),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvi16ger2pp",	  XX3(59,107),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
-{"xvbf16ger2np",XX3(59,114),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvbf16ger2np",XX3(59,114),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvbf16ger2np",  XX3(59,114),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
-{"xvf64gernp",	XX3(59,122),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
+{"dmxvf64gernp",  XX3(59,122),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
+{"xvf64gernp",	  XX3(59,122),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
 
 {"dsub",	XRC(59,514,0),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRA, FRB}},
 {"dsub.",	XRC(59,514,1),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRA, FRB}},
@@ -9007,8 +9128,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"ddiv",	XRC(59,546,0),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRA, FRB}},
 {"ddiv.",	XRC(59,546,1),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRA, FRB}},
 
-{"xvf16ger2pn",	XX3(59,146),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvf16ger2pn", XX3(59,146),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvf16ger2pn",	  XX3(59,146),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
+{"dmxvf32gerpn",XX3(59,154),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvf32gerpn",	XX3(59,154),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"dcmpu",	X(59,642),	X_MASK,	     POWER6,	PPCVLE,		{BF,  FRA, FRB}},
@@ -9016,8 +9139,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dtstsf",	X(59,674),	X_MASK,	     POWER6,	PPCVLE,		{BF,  FRA, FRB}},
 {"dtstsfi",	X(59,675),	X_MASK|1<<22,POWER9,	PPCVLE,		{BF, UIM6, FRB}},
 
-{"xvbf16ger2pn",XX3(59,178),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvbf16ger2pn",XX3(59,178),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvbf16ger2pn",  XX3(59,178),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
+{"dmxvf64gerpn",XX3(59,186),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
 {"xvf64gerpn",	XX3(59,186),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
 
 {"drsp",	XRC(59,770,0),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRB}},
@@ -9029,7 +9154,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"denbcd",	XRC(59,834,0),	X_MASK,	     POWER6,	PPCVLE,		{S, FRT, FRB}},
 {"denbcd.",	XRC(59,834,1),	X_MASK,	     POWER6,	PPCVLE,		{S, FRT, FRB}},
 
-{"xvf16ger2nn",	XX3(59,210),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvf16ger2nn", XX3(59,210),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvf16ger2nn",	  XX3(59,210),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"fcfids",	XRC(59,846,0),	XRA_MASK, POWER7|PPCA2,	PPCVLE,		{FRT, FRB}},
 {"fcfids.",	XRC(59,846,1),	XRA_MASK, POWER7|PPCA2,	PPCVLE,		{FRT, FRB}},
@@ -9037,13 +9163,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"diex",	XRC(59,866,0),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRA, FRB}},
 {"diex.",	XRC(59,866,1),	X_MASK,	     POWER6,	PPCVLE,		{FRT, FRA, FRB}},
 
+{"dmxvf32gernn",XX3(59,218),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 {"xvf32gernn",	XX3(59,218),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
-{"xvbf16ger2nn",XX3(59,242),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"dmxvbf16ger2nn",XX3(59,242),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
+{"xvbf16ger2nn",  XX3(59,242),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6a, XB6a}},
 
 {"fcfidus",	XRC(59,974,0),	XRA_MASK, POWER7|PPCA2,	PPCVLE,		{FRT, FRB}},
 {"fcfidus.",	XRC(59,974,1),	XRA_MASK, POWER7|PPCA2,	PPCVLE,		{FRT, FRB}},
 
+{"dmxvf64gernn",XX3(59,250),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
 {"xvf64gernn",	XX3(59,250),	XX3ACC_MASK, POWER10,	PPCVLE,		{ACC, XA6ap, XB6a}},
 
 {"xsaddsp",	XX3(60,0),	XX3_MASK,    PPCVSX2,	PPCVLE,		{XT6, XA6, XB6}},
@@ -9220,6 +9349,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xvnegsp",	XX2(60,441),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
 {"xvmaxdp",	XX3(60,224),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
 {"xvnmaddadp",	XX3(60,225),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
+{"dmxxextfdmr512",XX3(60,226),	XX3DMR_MASK, FUTURE,	PPCVLE,		{XA5p, XB5p, DMR, P1}},
 {"xvcvdpuxds",	XX2(60,456),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
 {"xvcvspdp",	XX2(60,457),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
 {"xxgenpcvbm",	X(60,916),	XX1_MASK,    POWER10,	PPCVLE,		{XT6, VB, UIMM}},
@@ -9227,6 +9357,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xsiexpdp",	X(60,918),	XX1_MASK,    PPCVSX3,	PPCVLE,		{XT6, RA, RB}},
 {"xvmindp",	XX3(60,232),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
 {"xvnmaddmdp",	XX3(60,233),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
+{"dmxxinstdmr512",XX3(60,234),	XX3DMR_MASK, FUTURE,	PPCVLE,		{DMR, XA5p, XB5p,P1}},
 {"xvcvdpsxds",	XX2(60,472),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
 {"xvabsdp",	XX2(60,473),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
 {"xxgenpcvwm",	X(60,948),	XX1_MASK,    POWER10,	PPCVLE,		{XT6, VB, UIMM}},
@@ -9247,6 +9378,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"xvmovdp",	XX3(60,240),	XX3_MASK,    PPCVSX,	PPCVLE|EXT,	{XT6, XAB6}},
 {"xvcpsgndp",	XX3(60,240),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
 {"xvnmsubadp",	XX3(60,241),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
+{"dmxxextfdmr256",XX2(60,484),	XX2DMR_MASK, FUTURE,	PPCVLE,		{XB5p, DMR, P2}},
+{"dmxxinstdmr256",XX2(60,485),	XX2DMR_MASK, FUTURE,	PPCVLE,		{DMR, XB5p, P2}},
 {"xvcvuxddp",	XX2(60,488),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
 {"xvnabsdp",	XX2(60,489),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
 {"xvtstdcdp",	XX2(60,490),  XX2DCMXS_MASK, PPCVSX3,	PPCVLE,		{XT6, XB6, DCMXS}},
@@ -9624,34 +9757,63 @@ const struct powerpc_opcode prefix_opcodes[] = {
 {"plq",		  P8LS|OP(56),	       P_D_MASK,	POWER10, 0,	{RTQ, D34, PRAQ, PCREL}},
 {"pld",		  P8LS|OP(57),	       P_D_MASK,	POWER10, 0,	{RT, D34, PRA0, PCREL}},
 {"plxvp",	  P8LS|OP(58),	       P_D_MASK,	POWER10, 0,	{XTP, D34, PRA0, PCREL}},
+{"pmdmxvi8ger4pp",PMMIRR|XX3(59,2),    P_GER4_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
 {"pmxvi8ger4pp",  PMMIRR|XX3(59,2),    P_GER4_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
+{"pmdmxvi8ger4",  PMMIRR|XX3(59,3),    P_GER4_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
 {"pmxvi8ger4",	  PMMIRR|XX3(59,3),    P_GER4_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
+{"pmdmxvf16ger2pp",PMMIRR|XX3(59,18),  P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2pp", PMMIRR|XX3(59,18),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf16ger2", PMMIRR|XX3(59,19),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2",	  PMMIRR|XX3(59,19),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf32gerpp",PMMIRR|XX3(59,26),   P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmxvf32gerpp",  PMMIRR|XX3(59,26),   P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
+{"pmdmxvf32ger",  PMMIRR|XX3(59,27),   P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmxvf32ger",	  PMMIRR|XX3(59,27),   P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
+{"pmdmxvi4ger8pp",PMMIRR|XX3(59,34),   P_GER8_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},
 {"pmxvi4ger8pp",  PMMIRR|XX3(59,34),   P_GER8_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},
+{"pmdmxvi4ger8",  PMMIRR|XX3(59,35),   P_GER8_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},
 {"pmxvi4ger8",	  PMMIRR|XX3(59,35),   P_GER8_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}},
+{"pmdmxvi16ger2spp",PMMIRR|XX3(59,42), P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvi16ger2spp",PMMIRR|XX3(59,42),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvi16ger2s",PMMIRR|XX3(59,43),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvi16ger2s",  PMMIRR|XX3(59,43),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvbf16ger2pp",PMMIRR|XX3(59,50), P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvbf16ger2pp",PMMIRR|XX3(59,50),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvbf16ger2",PMMIRR|XX3(59,51),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvbf16ger2",  PMMIRR|XX3(59,51),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf64gerpp",PMMIRR|XX3(59,58),   P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmxvf64gerpp",  PMMIRR|XX3(59,58),   P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
+{"pmdmxvf64ger",  PMMIRR|XX3(59,59),   P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmxvf64ger",	  PMMIRR|XX3(59,59),   P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
+{"pmdmxvi16ger2", PMMIRR|XX3(59,75),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvi16ger2",   PMMIRR|XX3(59,75),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf16ger2np",PMMIRR|XX3(59,82),  P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2np", PMMIRR|XX3(59,82),   P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf32gernp",PMMIRR|XX3(59,90),   P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmxvf32gernp",  PMMIRR|XX3(59,90),   P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
+{"pmdmxvi8ger4spp",PMMIRR|XX3(59,99),  P_GER4_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
 {"pmxvi8ger4spp", PMMIRR|XX3(59,99),   P_GER4_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}},
+{"pmdmxvi16ger2pp",PMMIRR|XX3(59,107), P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvi16ger2pp", PMMIRR|XX3(59,107),  P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvbf16ger2np",PMMIRR|XX3(59,114),P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvbf16ger2np",PMMIRR|XX3(59,114),  P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf64gernp",PMMIRR|XX3(59,122),  P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmxvf64gernp",  PMMIRR|XX3(59,122),  P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
+{"pmdmxvf16ger2pn",PMMIRR|XX3(59,146), P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2pn", PMMIRR|XX3(59,146),  P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf32gerpn",PMMIRR|XX3(59,154),  P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmxvf32gerpn",  PMMIRR|XX3(59,154),  P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
+{"pmdmxvbf16ger2pn",PMMIRR|XX3(59,178),P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvbf16ger2pn",PMMIRR|XX3(59,178),  P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf64gerpn",PMMIRR|XX3(59,186),  P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmxvf64gerpn",  PMMIRR|XX3(59,186),  P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
+{"pmdmxvf16ger2nn",PMMIRR|XX3(59,210), P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvf16ger2nn", PMMIRR|XX3(59,210),  P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf32gernn",PMMIRR|XX3(59,218),  P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
 {"pmxvf32gernn",  PMMIRR|XX3(59,218),  P_GER_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK}},
+{"pmdmxvbf16ger2nn",PMMIRR|XX3(59,242),P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
 {"pmxvbf16ger2nn",PMMIRR|XX3(59,242),  P_GER2_MASK,	POWER10, 0,	{ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}},
+{"pmdmxvf64gernn",PMMIRR|XX3(59,250),  P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pmxvf64gernn",  PMMIRR|XX3(59,250),  P_GER64_MASK,	POWER10, 0,	{ACC, XA6ap, XB6a, XMSK, YMSK2}},
 {"pstq",	  P8LS|OP(60),	       P_D_MASK,	POWER10, 0,	{RSQ, D34, PRA0, PCREL}},
 {"pstd",	  P8LS|OP(61),	       P_D_MASK,	POWER10, 0,	{RS, D34, PRA0, PCREL}},
