diff mbox series

[3/3,Binutils] aarch64: Add GCS system registers.

Message ID 204e389f-7daa-74e9-935c-7284e87b55fd@arm.com
State Not Applicable
Headers
Series [1/3,Binutils] aarch64: Add support for GCS extension. |

Checks

Context Check Description
snail/binutils-gdb-check fail Git am fail log

Commit Message

Srinath Parvathaneni Oct. 31, 2023, 5:52 p.m. UTC 
  Hi,

This patch adds support for 10 new AArch64 system registers
(gcscre0_el1, gcscr_el1, gcscr_el12, gcscr_el2, gcscr_el3,
gcspr_el0, gcspr_el1 ,gcspr_el12, gcspr_el2 and gcspr_el3),
which are enabled on using Guarded Control Stack (+gcs flag)
feature.

Regression tested for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.

Comments

Nick Clifton Nov. 2, 2023, 11:57 a.m. UTC | #1 
Hi Srinath,

> This patch adds support for 10 new AArch64 system registers
> (gcscre0_el1, gcscr_el1, gcscr_el12, gcscr_el2, gcscr_el3,
> gcspr_el0, gcspr_el1 ,gcspr_el12, gcspr_el2 and gcspr_el3),
> which are enabled on using Guarded Control Stack (+gcs flag)
> feature.
> 
> Regression tested for aarch64-none-elf target and found no regressions.
> 
> Ok for binutils-master?

Approved - please apply.

Cheers
   Nick
diff mbox series

Patch

diff --git a/gas/testsuite/gas/aarch64/gcs-sysregs-bad.d b/gas/testsuite/gas/aarch64/gcs-sysregs-bad.d
new file mode 100644
index 0000000000000000000000000000000000000000..439c1bdbabaeb05ed23f998c76a409864b3d844e
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/gcs-sysregs-bad.d
@@ -0,0 +1,3 @@ 
+#as: -march=armv8-a
+#source: gcs-sysregs.s
+#error_output: gcs-sysregs-bad.l
diff --git a/gas/testsuite/gas/aarch64/gcs-sysregs-bad.l b/gas/testsuite/gas/aarch64/gcs-sysregs-bad.l
new file mode 100644
index 0000000000000000000000000000000000000000..9ebfd8cfde8bdd2109fc45eb21c466124ec0a5fb
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/gcs-sysregs-bad.l
@@ -0,0 +1,21 @@ 
+[^:]*: Assembler messages:
+.*: Error: selected processor does not support system register name 'gcscr_el1'
+.*: Error: selected processor does not support system register name 'gcscr_el1'
+.*: Error: selected processor does not support system register name 'gcspr_el1'
+.*: Error: selected processor does not support system register name 'gcspr_el1'
+.*: Error: selected processor does not support system register name 'gcscr_el2'
+.*: Error: selected processor does not support system register name 'gcscr_el2'
+.*: Error: selected processor does not support system register name 'gcspr_el2'
+.*: Error: selected processor does not support system register name 'gcspr_el2'
+.*: Error: selected processor does not support system register name 'gcscr_el3'
+.*: Error: selected processor does not support system register name 'gcscr_el3'
+.*: Error: selected processor does not support system register name 'gcspr_el3'
+.*: Error: selected processor does not support system register name 'gcspr_el3'
+.*: Error: selected processor does not support system register name 'gcspr_el0'
+.*: Error: selected processor does not support system register name 'gcspr_el0'
+.*: Error: selected processor does not support system register name 'gcspr_el12'
+.*: Error: selected processor does not support system register name 'gcspr_el12'
+.*: Error: selected processor does not support system register name 'gcscr_el12'
+.*: Error: selected processor does not support system register name 'gcscr_el12'
+.*: Error: selected processor does not support system register name 'gcscre0_el1'
+.*: Error: selected processor does not support system register name 'gcscre0_el1'
diff --git a/gas/testsuite/gas/aarch64/gcs-sysregs.d b/gas/testsuite/gas/aarch64/gcs-sysregs.d
new file mode 100644
index 0000000000000000000000000000000000000000..f75c2708a14be2555c14d0e043486da88c9b50ad
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/gcs-sysregs.d
@@ -0,0 +1,29 @@ 
+#name: Test of Guarded Control Stack system registers
+#as: -march=armv8.8-a+gcs
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d5182500 	msr	gcscr_el1, x0
+.*:	d538251e 	mrs	x30, gcscr_el1
+.*:	d5182520 	msr	gcspr_el1, x0
+.*:	d538253e 	mrs	x30, gcspr_el1
+.*:	d51c2500 	msr	gcscr_el2, x0
+.*:	d53c251e 	mrs	x30, gcscr_el2
+.*:	d51c2520 	msr	gcspr_el2, x0
+.*:	d53c253e 	mrs	x30, gcspr_el2
+.*:	d51e2500 	msr	gcscr_el3, x0
+.*:	d53e251e 	mrs	x30, gcscr_el3
+.*:	d51e2520 	msr	gcspr_el3, x0
+.*:	d53e253e 	mrs	x30, gcspr_el3
+.*:	d51b2520 	msr	gcspr_el0, x0
+.*:	d53b253e 	mrs	x30, gcspr_el0
+.*:	d51d2520 	msr	gcspr_el12, x0
+.*:	d53d253e 	mrs	x30, gcspr_el12
+.*:	d51d2500 	msr	gcscr_el12, x0
+.*:	d53d251e 	mrs	x30, gcscr_el12
+.*:	d5182540 	msr	gcscre0_el1, x0
+.*:	d538255e 	mrs	x30, gcscre0_el1
diff --git a/gas/testsuite/gas/aarch64/gcs-sysregs.s b/gas/testsuite/gas/aarch64/gcs-sysregs.s
new file mode 100644
index 0000000000000000000000000000000000000000..0f5de0153880166abac2c7f74b2c98210011e228
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/gcs-sysregs.s
@@ -0,0 +1,20 @@ 
+	msr gcscr_el1, x0
+	mrs x30, gcscr_el1
+	msr gcspr_el1, x0
+	mrs x30, gcspr_el1
+	msr gcscr_el2, x0
+	mrs x30, gcscr_el2
+	msr gcspr_el2, x0
+	mrs x30, gcspr_el2
+	msr gcscr_el3, x0
+	mrs x30, gcscr_el3
+	msr gcspr_el3, x0
+	mrs x30, gcspr_el3
+	msr gcspr_el0, x0
+	mrs x30, gcspr_el0
+	msr gcspr_el12, x0
+	mrs x30, gcspr_el12
+	msr gcscr_el12, x0
+	mrs x30, gcscr_el12
+	msr gcscre0_el1, x0
+	mrs x30, gcscre0_el1
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 9adabea5cd41939dcde94c94579389b897ac7346..2f5780a21d49b9c2bf6b9e2c61aad82a7a5069b9 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -419,6 +419,16 @@ 
   SYSREG ("fpcr",		CPENC (3,3,4,4,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("fpexc32_el2",	CPENC (3,4,5,3,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("fpsr",		CPENC (3,3,4,4,1),	0,			AARCH64_NO_FEATURES)
+  SYSREG ("gcspr_el0",		CPENC (3,3,2,5,1),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcspr_el1",		CPENC (3,0,2,5,1),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcspr_el2",		CPENC (3,4,2,5,1),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcspr_el12",		CPENC (3,5,2,5,1),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcspr_el3",		CPENC (3,6,2,5,1),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscre0_el1",	CPENC (3,0,2,5,2),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscr_el1",		CPENC (3,0,2,5,0),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscr_el2",		CPENC (3,4,2,5,0),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscr_el12",		CPENC (3,5,2,5,0),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
+  SYSREG ("gcscr_el3",		CPENC (3,6,2,5,0),    	F_ARCHEXT,		AARCH64_FEATURE (GCS))
   SYSREG ("gcr_el1",		CPENC (3,0,1,0,6),	F_ARCHEXT,		AARCH64_FEATURE (MEMTAG))
   SYSREG ("gmid_el1",		CPENC (3,1,0,0,4),	F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE (MEMTAG))
   SYSREG ("gpccr_el3",		CPENC (3,6,2,1,6),	0,			AARCH64_NO_FEATURES)