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[111.98.113.1]) by smtp.gmail.com with ESMTPSA id h4-20020a170902eec400b001db7ed7ac34sm6465631plb.297.2024.02.20.09.56.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Feb 2024 09:56:27 -0800 (PST) From: Tatsuyuki Ishi To: binutils@sourceware.org Cc: i@maskray.me, nelson@rivosinc.com, rui314@gmail.com, ruiu@bluewhale.systems, Tatsuyuki Ishi Subject: [PATCH v4 3/9] RISC-V: Add assembly support for TLSDESC. Date: Wed, 21 Feb 2024 02:55:50 +0900 Message-ID: <20240220175556.304692-4-ishitatsuyuki@gmail.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240220175556.304692-1-ishitatsuyuki@gmail.com> References: <20230817180852.121628-2-ishitatsuyuki@gmail.com> <20240220175556.304692-1-ishitatsuyuki@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1774500739865715451 X-GMAIL-MSGID: 1791442028283335250 gas/ * tc-riscv.c (percent_op_*): Add support for %tlsdesc_hi, %tlsdesc_load_lo, %tlsdesc_add_lo and %tlsdesc_call. percent_op_rtype renamed to percent_op_relax_only as this matcher is extended to handle jalr as well which is not R-type. (riscv_ip): Apply the percent_op_relax_only rename and update comment. (md_apply_fix): Add TLSDESC_* to relaxable list. Add TLSDESC_HI20 to TLS relocation check list. * testsuite/gas/riscv/tlsdesc.*: New test cases for TLSDESC relocation generation. opcodes/ * riscv-opc.c (riscv_opcodes): Add a new syntax for jalr with %tlsdesc_call annotations. --- v4: Change test case to use objdump: -dr, and remove the rv32 arch restriction. gas/config/tc-riscv.c | 18 +++++++++++----- gas/testsuite/gas/riscv/tlsdesc.d | 36 +++++++++++++++++++++++++++++++ gas/testsuite/gas/riscv/tlsdesc.s | 24 +++++++++++++++++++++ opcodes/riscv-opc.c | 1 + 4 files changed, 74 insertions(+), 5 deletions(-) create mode 100644 gas/testsuite/gas/riscv/tlsdesc.d create mode 100644 gas/testsuite/gas/riscv/tlsdesc.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index a4161420128..55c527520d5 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2202,6 +2202,7 @@ static const struct percent_op_match percent_op_utype[] = {"tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, {"pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, {"got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, + {"tlsdesc_hi", BFD_RELOC_RISCV_TLSDESC_HI20}, {"tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, {"tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, {"hi", BFD_RELOC_RISCV_HI20}, @@ -2213,6 +2214,8 @@ static const struct percent_op_match percent_op_itype[] = {"lo", BFD_RELOC_RISCV_LO12_I}, {"tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, {"pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, + {"tlsdesc_load_lo", BFD_RELOC_RISCV_TLSDESC_LOAD_LO12}, + {"tlsdesc_add_lo", BFD_RELOC_RISCV_TLSDESC_ADD_LO12}, {0, 0} }; @@ -2224,8 +2227,9 @@ static const struct percent_op_match percent_op_stype[] = {0, 0} }; -static const struct percent_op_match percent_op_rtype[] = +static const struct percent_op_match percent_op_relax_only[] = { + {"tlsdesc_call", BFD_RELOC_RISCV_TLSDESC_CALL}, {"tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, {0, 0} }; @@ -3386,10 +3390,10 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, *imm_reloc = BFD_RELOC_RISCV_LO12_I; goto load_store; case '1': - /* This is used for TLS, where the fourth operand is - %tprel_add, to get a relocation applied to an add - instruction, for relaxation to use. */ - p = percent_op_rtype; + /* This is used for TLS relocations that acts as relaxation + markers and do not change the instruction encoding, + i.e. %tprel_add and %tlsdesc_call. */ + p = percent_op_relax_only; goto alu_op; case '0': /* AMO displacement, which must be zero. */ load_store: @@ -4252,6 +4256,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_RISCV_TPREL_LO12_I: case BFD_RELOC_RISCV_TPREL_LO12_S: case BFD_RELOC_RISCV_TPREL_ADD: + case BFD_RELOC_RISCV_TLSDESC_HI20: relaxable = true; /* Fall through. */ @@ -4425,6 +4430,9 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) case BFD_RELOC_RISCV_CALL: case BFD_RELOC_RISCV_CALL_PLT: + case BFD_RELOC_RISCV_TLSDESC_LOAD_LO12: + case BFD_RELOC_RISCV_TLSDESC_ADD_LO12: + case BFD_RELOC_RISCV_TLSDESC_CALL: relaxable = true; break; diff --git a/gas/testsuite/gas/riscv/tlsdesc.d b/gas/testsuite/gas/riscv/tlsdesc.d new file mode 100644 index 00000000000..5cd26ac3280 --- /dev/null +++ b/gas/testsuite/gas/riscv/tlsdesc.d @@ -0,0 +1,36 @@ +#source: tlsdesc.s +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+00 <_start>: +[ ]+0:[ ]+00000517[ ]+auipc[ ]+a0,0x0 +[ ]+0:[ ]+R_RISCV_TLSDESC_HI20[ ]+sg1 +[ ]+0:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+4:[ ]+00052283[ ]+lw[ ]+t0,0\(a0\) # 0( <.*>)? +[ ]+4:[ ]+R_RISCV_TLSDESC_LOAD_LO12[ ]+\.desc1 +[ ]+4:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+8:[ ]+00050513[ ]+mv[ ]+a0,a0 +[ ]+8:[ ]+R_RISCV_TLSDESC_ADD_LO12[ ]+\.desc1 +[ ]+8:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+c:[ ]+000282e7[ ]+jalr[ ]+t0,t0 +[ ]+c:[ ]+R_RISCV_TLSDESC_CALL[ ]+\.desc1 +[ ]+c:[ ]+R_RISCV_RELAX[ ]+\*ABS\* + +0+10 <\.desc2>: +[ ]+10:[ ]+00000517[ ]+auipc[ ]+a0,0x0 +[ ]+10:[ ]+R_RISCV_TLSDESC_HI20[ ]+sl1 +[ ]+10:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+14:[ ]+00052283[ ]+lw[ ]+t0,0\(a0\) # 10( <.*>)? +[ ]+14:[ ]+R_RISCV_TLSDESC_LOAD_LO12[ ]+\.desc2 +[ ]+14:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+18:[ ]+00050513[ ]+mv[ ]+a0,a0 +[ ]+18:[ ]+R_RISCV_TLSDESC_ADD_LO12[ ]+\.desc2 +[ ]+18:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+1c:[ ]+000282e7[ ]+jalr[ ]+t0,t0 +[ ]+1c:[ ]+R_RISCV_TLSDESC_CALL[ ]+\.desc2 +[ ]+1c:[ ]+R_RISCV_RELAX[ ]+\*ABS\* +[ ]+20:[ ]+00008067[ ]+ret diff --git a/gas/testsuite/gas/riscv/tlsdesc.s b/gas/testsuite/gas/riscv/tlsdesc.s new file mode 100644 index 00000000000..15468d5f947 --- /dev/null +++ b/gas/testsuite/gas/riscv/tlsdesc.s @@ -0,0 +1,24 @@ + .section .tbss,"awT",@nobits + .global sg1 +sg1: + .zero 4 +sl1: + .zero 4 + + .text + .globl _start + .type _start,@function +_start: +.desc1: + auipc a0, %tlsdesc_hi(sg1) + lw t0, %tlsdesc_load_lo(.desc1)(a0) + addi a0, a0, %tlsdesc_add_lo(.desc1) + jalr t0, t0, %tlsdesc_call(.desc1) + +.desc2: + auipc a0, %tlsdesc_hi(sl1) + lw t0, %tlsdesc_load_lo(.desc2)(a0) + addi a0, a0, %tlsdesc_add_lo(.desc2) + jalr t0, t0, %tlsdesc_call(.desc2) + + ret diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index fdd05ac75dc..dcc592e1fc2 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -384,6 +384,7 @@ const struct riscv_opcode riscv_opcodes[] = {"jalr", 0, INSN_CLASS_I, "s,j", MATCH_JALR|(X_RA << OP_SH_RD), MASK_JALR|MASK_RD, match_opcode, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,s", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_ALIAS|INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,o(s)", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, +{"jalr", 0, INSN_CLASS_I, "d,s,1", MATCH_JALR, MASK_JALR|MASK_IMM, match_opcode, INSN_JSR }, {"jalr", 0, INSN_CLASS_I, "d,s,j", MATCH_JALR, MASK_JALR, match_opcode, INSN_JSR }, {"j", 0, INSN_CLASS_C, "Ca", MATCH_C_J, MASK_C_J, match_opcode, INSN_ALIAS|INSN_BRANCH }, {"j", 0, INSN_CLASS_I, "a", MATCH_JAL, MASK_JAL|MASK_RD, match_opcode, INSN_ALIAS|INSN_BRANCH },