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Thu, 15 Feb 2024 15:58:29 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 15 Feb 2024 15:58:29 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel Subject: [PATCH 11/14] s390: Print base register 0 as "0" in disassembly Date: Thu, 15 Feb 2024 16:58:18 +0100 Message-Id: <20240215155821.4065623-12-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240215155821.4065623-1-jremus@linux.ibm.com> References: <20240215155821.4065623-1-jremus@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-GUID: W2lfle_rqOog2CiYvk9NleFbCog4l0Vv X-Proofpoint-ORIG-GUID: W2lfle_rqOog2CiYvk9NleFbCog4l0Vv X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-15_14,2024-02-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 impostorscore=0 mlxscore=0 adultscore=0 priorityscore=1501 mlxlogscore=697 malwarescore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2402150128 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790981271626869010 X-GMAIL-MSGID: 1790981271626869010 Base and index register 0 have no effect in address computation: "A value of zero in the B [base] or X [index] field specifies that no base or index is to be applied, and, thus, general register 0 cannot be designated as containing a base address or index." IBM z/Architecture Principles of Operation [1], chapter "Organization", section "General Registers". Index register 0 is omitted in the s390 disassembly. Base register 0 is omitted in D(B), D(L,B) and D(X,B) - the latter only if the index register is zero. To make it more apparent print base register 0 as "0" instead of "%r0", whenever it would still be printed in the disassembly. [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-dis.c: Print base register 0 as "0" in disassembly. binutils/ * NEWS: Mention base register 0 now being printed as "0" in s390 disassembly. gas/ * testsuite/gas/s390/zarch-base-index-0.d: Update test case output verification patterns to accept "0" as base base register due to disassembler output format change. * gas/testsuite/gas/s390/zarch-omitted-base-index.d: Likewise. Reviewed-by: Andreas Krebbel Signed-off-by: Jens Remus --- binutils/NEWS | 2 + gas/testsuite/gas/s390/zarch-base-index-0.d | 66 +++++++++---------- .../gas/s390/zarch-omitted-base-index.d | 4 +- opcodes/s390-dis.c | 17 +++-- 4 files changed, 50 insertions(+), 39 deletions(-) diff --git a/binutils/NEWS b/binutils/NEWS index 7b7ac1cbba11..9c7c8f1f6033 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Base register 0 is now printed as "0" instead of "%r0" in s390 disassembly. + * When objdump or readelf are used to display the contents of a .eh_frame section they will now also display the contents of the .eh_frame_hdr section, if present. diff --git a/gas/testsuite/gas/s390/zarch-base-index-0.d b/gas/testsuite/gas/s390/zarch-base-index-0.d index e6266040c8e7..4dd913bff920 100644 --- a/gas/testsuite/gas/s390/zarch-base-index-0.d +++ b/gas/testsuite/gas/s390/zarch-base-index-0.d @@ -17,8 +17,8 @@ Disassembly of section .text: .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) .*: 5a 10 30 10 [ ]*a %r1,16\(%r3\) -.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) -.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) +.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\) .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 .*: 5a 10 00 10 [ ]*a %r1,16 @@ -31,46 +31,46 @@ Disassembly of section .text: .*: 5a 00 00 00 [ ]*a %r0,0 .*: 5a 00 00 00 [ ]*a %r0,0 .*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 -.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,%r0\),0 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 +.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,0\),0 .*: f3 01 10 10 20 20 [ ]*unpk 16\(1,%r1\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\) -.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,%r0\),0\(2,%r0\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\) +.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,0\),0\(2,0\) .*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 .*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0 -.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 -.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 +.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 diff --git a/gas/testsuite/gas/s390/zarch-omitted-base-index.d b/gas/testsuite/gas/s390/zarch-omitted-base-index.d index b2ff292628b1..cb168a2fe187 100644 --- a/gas/testsuite/gas/s390/zarch-omitted-base-index.d +++ b/gas/testsuite/gas/s390/zarch-omitted-base-index.d @@ -18,5 +18,5 @@ Disassembly of section .text: .*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0 .*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\) .*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32 -.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\) -.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32 +.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\) +.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32 diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c index a4cba77c6aeb..ee2f2cb62ed2 100644 --- a/opcodes/s390-dis.c +++ b/opcodes/s390-dis.c @@ -234,8 +234,13 @@ s390_print_insn_with_opcode (bfd_vma memaddr, { info->fprintf_styled_func (info->stream, dis_style_text, "%c", separator); - info->fprintf_styled_func (info->stream, dis_style_register, - "%%r%u", val.u); + if ((flags & (S390_OPERAND_BASE | S390_OPERAND_INDEX)) + && val.u == 0) + info->fprintf_styled_func (info->stream, dis_style_register, + "%u", val.u); + else + info->fprintf_styled_func (info->stream, dis_style_register, + "%%r%u", val.u); } else if (flags & S390_OPERAND_FPR) { @@ -248,8 +253,12 @@ s390_print_insn_with_opcode (bfd_vma memaddr, { info->fprintf_styled_func (info->stream, dis_style_text, "%c", separator); - info->fprintf_styled_func (info->stream, dis_style_register, - "%%v%i", val.u); + if ((flags & S390_OPERAND_INDEX) && val.u == 0) + info->fprintf_styled_func (info->stream, dis_style_register, + "%u", val.u); + else + info->fprintf_styled_func (info->stream, dis_style_register, + "%%v%i", val.u); } else if (flags & S390_OPERAND_AR) {