@@ -1,5 +1,7 @@
-*- text -*-
+* Base register 0 is now printed as "0" instead of "%r0" in s390 disassembly.
+
* When objdump or readelf are used to display the contents of a .eh_frame
section they will now also display the contents of the .eh_frame_hdr section,
if present.
@@ -17,8 +17,8 @@ Disassembly of section .text:
.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\)
.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\)
.*: 5a 10 30 10 [ ]*a %r1,16\(%r3\)
-.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\)
-.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,%r0\)
+.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\)
+.*: 5a 12 00 10 [ ]*a %r1,16\(%r2,0\)
.*: 5a 10 00 10 [ ]*a %r1,16
.*: 5a 10 00 10 [ ]*a %r1,16
.*: 5a 10 00 10 [ ]*a %r1,16
@@ -31,46 +31,46 @@ Disassembly of section .text:
.*: 5a 00 00 00 [ ]*a %r0,0
.*: 5a 00 00 00 [ ]*a %r0,0
.*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\)
-.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\)
-.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\)
-.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\)
+.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\)
+.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\)
+.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\)
.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32
.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32
.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
-.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,%r0\),0
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
+.*: d2 00 00 00 00 00 [ ]*mvc 0\(1,0\),0
.*: f3 01 10 10 20 20 [ ]*unpk 16\(1,%r1\),32\(2,%r2\)
-.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\)
-.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\)
-.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,%r0\),32\(2,%r2\)
-.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\)
-.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\)
-.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,%r0\),32\(2,%r0\)
-.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,%r0\),0\(2,%r0\)
+.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\)
+.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\)
+.*: f3 01 00 10 20 20 [ ]*unpk 16\(1,0\),32\(2,%r2\)
+.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\)
+.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\)
+.*: f3 01 10 10 00 20 [ ]*unpk 16\(1,%r1\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 10 00 20 [ ]*unpk 16\(1,0\),32\(2,0\)
+.*: f3 01 00 00 00 00 [ ]*unpk 0\(1,0\),0\(2,0\)
.*: e7 12 30 10 00 13 [ ]*vgef %v1,16\(%v2,%r3\),0
.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0
.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0
.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0
.*: e7 10 30 10 00 13 [ ]*vgef %v1,16\(%r3\),0
-.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0
-.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,%r0\),0
+.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0
+.*: e7 12 00 10 00 13 [ ]*vgef %v1,16\(%v2,0\),0
.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0
.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0
.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0
@@ -18,5 +18,5 @@ Disassembly of section .text:
.*: e7 10 00 10 00 13 [ ]*vgef %v1,16,0
.*: d2 00 10 10 20 20 [ ]*mvc 16\(1,%r1\),32\(%r2\)
.*: d2 00 10 10 00 20 [ ]*mvc 16\(1,%r1\),32
-.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,%r0\),32\(%r2\)
-.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,%r0\),32
+.*: d2 00 00 10 20 20 [ ]*mvc 16\(1,0\),32\(%r2\)
+.*: d2 00 00 10 00 20 [ ]*mvc 16\(1,0\),32
@@ -234,8 +234,13 @@ s390_print_insn_with_opcode (bfd_vma memaddr,
{
info->fprintf_styled_func (info->stream, dis_style_text,
"%c", separator);
- info->fprintf_styled_func (info->stream, dis_style_register,
- "%%r%u", val.u);
+ if ((flags & (S390_OPERAND_BASE | S390_OPERAND_INDEX))
+ && val.u == 0)
+ info->fprintf_styled_func (info->stream, dis_style_register,
+ "%u", val.u);
+ else
+ info->fprintf_styled_func (info->stream, dis_style_register,
+ "%%r%u", val.u);
}
else if (flags & S390_OPERAND_FPR)
{
@@ -248,8 +253,12 @@ s390_print_insn_with_opcode (bfd_vma memaddr,
{
info->fprintf_styled_func (info->stream, dis_style_text,
"%c", separator);
- info->fprintf_styled_func (info->stream, dis_style_register,
- "%%v%i", val.u);
+ if ((flags & S390_OPERAND_INDEX) && val.u == 0)
+ info->fprintf_styled_func (info->stream, dis_style_register,
+ "%u", val.u);
+ else
+ info->fprintf_styled_func (info->stream, dis_style_register,
+ "%%v%i", val.u);
}
else if (flags & S390_OPERAND_AR)
{