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bh=W+SnrbsYLzNBSOKiaG3JSbY7ucofnpqwew3MPqyrQn0=; b=Ln1Y7bd6n9dFflPiFWcK9iADsZpZwd0NjdjuonciWYADhTINi+EByLFKoS3Wbd9GVs AMuVZiFK8ZnDJc4m+86pJXqKzc9AJ9oeL28byy9qwIe1m9eeMYqyYjFTaXXlhyVR1iip pAZcpwb0YulKLPlTCC5xa0tLAHJunEawdLT9hf3Bm+hKMvGKiRDu4RG0+PPkdYLXHDfQ 6oYfgj2kStGnKLWRprH83RmidmGgjQ4CXtqqNt0b3EE9d3D2shhoQBpUSOP1i/AWXiif apBOY+GCkKVKo1sHhxZqT8On658i6LgA+2xP0veUGjrONxILvdje53GJ6eLIXNZLPlGy gpYw== X-Gm-Message-State: AOJu0YxIMQQLmRhstIYRiZpSWz+l27WJL1IelOC4L4OwGXhSEtEJslix idKEJYWbeFb+8hptOsvd+2lheCjJeBQLAzxH6issxWlDuHzeUZQfWizwctE3MTNITUaAVgLuuqi Q X-Received: by 2002:a05:622a:1a1a:b0:42c:6bec:9e8e with SMTP id f26-20020a05622a1a1a00b0042c6bec9e8emr8176073qtb.68.1707759732651; Mon, 12 Feb 2024 09:42:12 -0800 (PST) Received: from borderland.rhod.uc.edu ([129.137.96.2]) by smtp.gmail.com with ESMTPSA id w5-20020ac857c5000000b0042c750bf876sm339604qta.43.2024.02.12.09.42.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Feb 2024 09:42:12 -0800 (PST) From: Will Hawkins To: binutils@sourceware.org Cc: Will Hawkins Subject: [PATCH v2 1/1] objdump, as: Add callx support for BPF CPU v1 Date: Mon, 12 Feb 2024 12:42:06 -0500 Message-ID: <20240212174209.620310-2-hawkinsw@obs.cr> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240212174209.620310-1-hawkinsw@obs.cr> References: <20240212174209.620310-1-hawkinsw@obs.cr> MIME-Version: 1.0 X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790715902427015831 X-GMAIL-MSGID: 1790715902427015831 Add support for (dis)assembling the callx instruction back to CPU v1. gas/ChangeLog: * config/tc-bpf.c (struct bpf_insn): Add rmm32 for handling * instructions where a register is encoded in the immediate. (encode_insn): Encode instruction where register goes in immediate. (md_assemble): Assemble the callx instruction. * testsuite/gas/bpf/bpf.exp: Add callx test and refactor others (remove * pseudo-c mnemonics). * testsuite/gas/bpf/indcall-1.d: Moved to... * testsuite/gas/bpf/callr.d: ...here. * testsuite/gas/bpf/indcall-1.s: Moved to... * testsuite/gas/bpf/callr.s: ...here. * testsuite/gas/bpf/indcall-1-pseudoc.d: Removed. * testsuite/gas/bpf/indcall-1-pseudoc.s: Removed. include/ChangeLog: * opcode/bpf.h (enum bpf_insn_id): Add BPF_INSN_CALLX (struct bpf_opcode): Add rmm32, has_rmm32. opcodes/ChangeLog: * bpf-dis.c (print_insn_bpf): Support printing callx. * bpf-opc.c: Add callx. ChangeLog: * sim/bpf/bpf-sim.c (execute): Support callx. Signed-off-by: Will Hawkins --- gas/config/tc-bpf.c | 25 ++++++++++++++++++- gas/testsuite/gas/bpf/bpf.exp | 4 +-- .../gas/bpf/{indcall-1.d => callr.d} | 4 +-- .../gas/bpf/{indcall-1.s => callr.s} | 2 +- gas/testsuite/gas/bpf/indcall-1-pseudoc.d | 23 ----------------- gas/testsuite/gas/bpf/indcall-1-pseudoc.s | 13 ---------- include/opcode/bpf.h | 3 ++- opcodes/bpf-dis.c | 6 +++++ opcodes/bpf-opc.c | 4 ++- sim/bpf/bpf-sim.c | 4 +++ 10 files changed, 44 insertions(+), 44 deletions(-) rename gas/testsuite/gas/bpf/{indcall-1.d => callr.d} (90%) rename gas/testsuite/gas/bpf/{indcall-1.s => callr.s} (90%) delete mode 100644 gas/testsuite/gas/bpf/indcall-1-pseudoc.d delete mode 100644 gas/testsuite/gas/bpf/indcall-1-pseudoc.s diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c index 43e098c2a86..5bc8b169819 100644 --- a/gas/config/tc-bpf.c +++ b/gas/config/tc-bpf.c @@ -38,6 +38,7 @@ struct bpf_insn bpf_insn_word opcode; uint8_t dst; uint8_t src; + uint8_t rmm32; expressionS offset16; expressionS imm32; expressionS imm64; @@ -50,6 +51,7 @@ struct bpf_insn unsigned int has_disp16 : 1; unsigned int has_disp32 : 1; unsigned int has_imm32 : 1; + unsigned int has_rmm32 : 1; unsigned int has_imm64 : 1; unsigned int is_relaxable : 1; @@ -935,7 +937,13 @@ encode_insn (struct bpf_insn *insn, char *bytes, if (immediate_overflow (imm, 32)) as_bad (_("immediate out of range, shall fit in 32 bits")); else - encode_int32 (insn->imm32.X_add_number, bytes + 4); + encode_int32 (insn->imm32.X_add_number, bytes + 4); + } + + if (insn->has_rmm32) + { + int64_t imm = insn->rmm32; + encode_int32 (imm, bytes + 4); } if (insn->has_disp32 && insn->disp32.X_op == O_constant) @@ -1610,6 +1618,21 @@ md_assemble (char *str ATTRIBUTE_UNUSED) insn.has_imm32 = 1; p += 4; } + else if (strncmp (p, "%r32", 4) == 0) + { + uint8_t regno; + char *news = parse_bpf_register (s, 'r', ®no); + if (news == NULL) + { + PARSE_ERROR ("expected signed 32-bit immediate " + "indicating register"); + break; + } + s = news; + insn.rmm32 = regno; + insn.has_rmm32 = 1; + p += 4; + } else if (strncmp (p, "%o16", 4) == 0) { while (*s == ' ' || *s == '\t') diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp index dae8bd924d0..60c8d2ae852 100644 --- a/gas/testsuite/gas/bpf/bpf.exp +++ b/gas/testsuite/gas/bpf/bpf.exp @@ -41,8 +41,8 @@ if {[istarget bpf*-*-*]} { run_dump_test atomic-v1 run_dump_test atomic run_dump_test atomic-pseudoc - run_dump_test indcall-1 - run_dump_test indcall-1-pseudoc + run_dump_test callr + run_dump_test callx run_dump_test jump-relax-ja run_dump_test jump-relax-jump diff --git a/gas/testsuite/gas/bpf/indcall-1.d b/gas/testsuite/gas/bpf/callr.d similarity index 90% rename from gas/testsuite/gas/bpf/indcall-1.d rename to gas/testsuite/gas/bpf/callr.d index 51103bba2a1..ba70983d0ad 100644 --- a/gas/testsuite/gas/bpf/indcall-1.d +++ b/gas/testsuite/gas/bpf/callr.d @@ -1,6 +1,6 @@ #as: -EL -misa-spec=xbpf #objdump: -dr -M xbpf,dec -#source: indcall-1.s +#source: callr.s #name: BPF indirect call 1, normal syntax .*: +file format .*bpf.* @@ -14,7 +14,7 @@ Disassembly of section \.text: 18: 18 06 00 00 38 00 00 00 lddw %r6,56 20: 00 00 00 00 00 00 00 00[ ]* 18: R_BPF_64_64 .text - 28: 8d 06 00 00 00 00 00 00 call %r6 + 28: 8d 06 00 00 00 00 00 00 callr %r6 30: 95 00 00 00 00 00 00 00 exit 0000000000000038 : diff --git a/gas/testsuite/gas/bpf/indcall-1.s b/gas/testsuite/gas/bpf/callr.s similarity index 90% rename from gas/testsuite/gas/bpf/indcall-1.s rename to gas/testsuite/gas/bpf/callr.s index 5d49e41040a..d4f8208b2d4 100644 --- a/gas/testsuite/gas/bpf/indcall-1.s +++ b/gas/testsuite/gas/bpf/callr.s @@ -6,7 +6,7 @@ main: mov %r1, 1 mov %r2, 2 lddw %r6, bar - call %r6 + callr %r6 exit bar: diff --git a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d deleted file mode 100644 index 7a95bad8e65..00000000000 --- a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d +++ /dev/null @@ -1,23 +0,0 @@ -#as: -EL -mdialect=pseudoc -misa-spec=xbpf -#objdump: -M xbpf,pseudoc,dec -dr -#source: indcall-1-pseudoc.s -#name: BPF indirect call 1, pseudoc syntax - -.*: +file format .*bpf.* - -Disassembly of section \.text: - -0000000000000000
: - 0: b7 00 00 00 01 00 00 00 r0=1 - 8: b7 01 00 00 01 00 00 00 r1=1 - 10: b7 02 00 00 02 00 00 00 r2=2 - 18: 18 06 00 00 38 00 00 00 r6=56 ll - 20: 00 00 00 00 00 00 00 00[ ]* - 18: R_BPF_64_64 .text - 28: 8d 06 00 00 00 00 00 00 callx r6 - 30: 95 00 00 00 00 00 00 00 exit - -0000000000000038 : - 38: b7 00 00 00 00 00 00 00 r0=0 - 40: 95 00 00 00 00 00 00 00 exit -#pass diff --git a/gas/testsuite/gas/bpf/indcall-1-pseudoc.s b/gas/testsuite/gas/bpf/indcall-1-pseudoc.s deleted file mode 100644 index 2042697f15b..00000000000 --- a/gas/testsuite/gas/bpf/indcall-1-pseudoc.s +++ /dev/null @@ -1,13 +0,0 @@ - - .text - .align 4 -main: - r0 = 1 - r1 = 1 - r2 = 2 - r6 = bar ll - callx r6 - exit -bar: - r0 = 0 - exit diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h index df1e3bd0918..d5ea3c11df8 100644 --- a/include/opcode/bpf.h +++ b/include/opcode/bpf.h @@ -202,7 +202,7 @@ enum bpf_insn_id BPF_INSN_JAR, BPF_INSN_JEQR, BPF_INSN_JGTR, BPF_INSN_JSGTR, BPF_INSN_JGER, BPF_INSN_JSGER, BPF_INSN_JLTR, BPF_INSN_JSLTR, BPF_INSN_JSLER, BPF_INSN_JLER, BPF_INSN_JSETR, BPF_INSN_JNER, - BPF_INSN_CALLR, BPF_INSN_CALL, BPF_INSN_EXIT, + BPF_INSN_CALLR, BPF_INSN_CALLX, BPF_INSN_CALL, BPF_INSN_EXIT, /* Compare-and-jump instructions (reg OP imm.) */ BPF_INSN_JEQI, BPF_INSN_JGTI, BPF_INSN_JSGTI, BPF_INSN_JGEI, BPF_INSN_JSGEI, BPF_INSN_JLTI, BPF_INSN_JSLTI, @@ -254,6 +254,7 @@ struct bpf_opcode %d16 - 16-bit signed displacement (in 64-bit words minus one.) %o16 - 16-bit signed offset (in bytes.) %i32 - 32-bit signed immediate. + %r32 - 32-bit signed immediate indicating a register. %I32 - Like %i32. %i64 - 64-bit signed immediate. %w - expect zero or more white spaces and print a single space. diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c index d4020c259fb..50e714cb74b 100644 --- a/opcodes/bpf-dis.c +++ b/opcodes/bpf-dis.c @@ -251,6 +251,12 @@ print_insn_bpf (bfd_vma pc, disassemble_info *info) imm32); p += 4; } + else if (strncmp (p, "%r32", 4) == 0) + { + int32_t imm32 = bpf_extract_imm32 (word, endian); + print_register (info, p, imm32); + p += 4; + } else if (strncmp (p, "%o16", 4) == 0 || strncmp (p, "%d16", 4) == 0) { diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index 19e096501a2..cbf4441c7d6 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -272,8 +272,10 @@ const struct bpf_opcode bpf_opcodes[] = BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_X}, {BPF_INSN_JNER, "jne%W%dr , %sr , %d16", "if%w%dr != %sr%wgoto%w%d16", BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_X}, - {BPF_INSN_CALLR, "call%W%dr", "callx%w%dr", + {BPF_INSN_CALLR, "callr%W%dr", "callr%w%dr", BPF_XBPF, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_X}, + {BPF_INSN_CALLX, "callx%W%r32", "callx%w%r32", + BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_X}, {BPF_INSN_CALL, "call%W%d32", "call%w%d32", BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_K}, {BPF_INSN_EXIT, "exit", "exit", diff --git a/sim/bpf/bpf-sim.c b/sim/bpf/bpf-sim.c index c1f103823fb..a3976d0b4bf 100644 --- a/sim/bpf/bpf-sim.c +++ b/sim/bpf/bpf-sim.c @@ -1096,6 +1096,10 @@ execute (SIM_CPU *cpu, struct bpf_insn *insn) BPF_TRACE ("BPF_INSN_CALLR\n"); bpf_call (cpu, DISP (bpf_regs[insn->dst]), insn->src); break; + case BPF_INSN_CALLX: + BPF_TRACE ("BPF_INSN_CALLX\n"); + bpf_call (cpu, DISP (bpf_regs[insn->dst]), insn->src); + break; case BPF_INSN_CALL: BPF_TRACE ("BPF_INSN_CALL\n"); bpf_call (cpu, insn->imm32, insn->src);