diff mbox series

[1/1] objdump: Add callx support for BPF CPU v1

Message ID 20240209180734.443763-2-hawkinsw@obs.cr
State Unresolved
Headers
Series objdump: Add callx support for BPF CPU v1 |

Checks

Context Check Description
snail/binutils-gdb-check warning Git am fail log

Commit Message

Will Hawkins Feb. 9, 2024, 6:07 p.m. UTC 
  Add support for disassembling the callx instruction back to CPU v1.

include/ChangeLog:

	* opcode/bpf.h (enum bpf_insn_id):

opcodes/ChangeLog:

	* bpf-opc.c:

ChangeLog:

	* sim/bpf/bpf-sim.c (execute):

Signed-off-by: Will Hawkins <hawkinsw@obs.cr>
---
 include/opcode/bpf.h | 2 +-
 opcodes/bpf-opc.c    | 2 ++
 sim/bpf/bpf-sim.c    | 4 ++++
 3 files changed, 7 insertions(+), 1 deletion(-)

Comments

Hans-Peter Nilsson Feb. 10, 2024, 4:47 a.m. UTC | #1 
On Fri, 9 Feb 2024, Will Hawkins wrote:

> Add support for disassembling the callx instruction back to CPU v1.
> 
> include/ChangeLog:
> 
> 	* opcode/bpf.h (enum bpf_insn_id):
> 
> opcodes/ChangeLog:
> 
> 	* bpf-opc.c:
> 
> ChangeLog:
> 
> 	* sim/bpf/bpf-sim.c (execute):

Not commenting on the rest of the patch but there's missing text 
after ":" above. Beware: gcc/contrib/mklog.py doesn't help with 
that part. :)

Happy hacking!

brgds, H-P
Will Hawkins Feb. 10, 2024, 6:13 a.m. UTC | #2 
On Fri, Feb 9, 2024 at 11:47 PM Hans-Peter Nilsson <hp@bitrange.com> wrote:
>
> On Fri, 9 Feb 2024, Will Hawkins wrote:
>
> > Add support for disassembling the callx instruction back to CPU v1.
> >
> > include/ChangeLog:
> >
> >       * opcode/bpf.h (enum bpf_insn_id):
> >
> > opcodes/ChangeLog:
> >
> >       * bpf-opc.c:
> >
> > ChangeLog:
> >
> >       * sim/bpf/bpf-sim.c (execute):
>
> Not commenting on the rest of the patch but there's missing text
> after ":" above. Beware: gcc/contrib/mklog.py doesn't help with
> that part. :)
>

Thank you! I thought something looked suspicious but because it was
what contrib/mklog.py gave me, I assumed you all had special
requirements! I will fix it and resubmit.

Thank you again!
Will



> Happy hacking!
>
> brgds, H-P
Will Hawkins Feb. 11, 2024, 11:26 p.m. UTC | #3 
On Sat, Feb 10, 2024 at 1:13 AM Will Hawkins <hawkinsw@obs.cr> wrote:
>
> On Fri, Feb 9, 2024 at 11:47 PM Hans-Peter Nilsson <hp@bitrange.com> wrote:
> >
> > On Fri, 9 Feb 2024, Will Hawkins wrote:
> >
> > > Add support for disassembling the callx instruction back to CPU v1.
> > >
> > > include/ChangeLog:
> > >
> > >       * opcode/bpf.h (enum bpf_insn_id):
> > >
> > > opcodes/ChangeLog:
> > >
> > >       * bpf-opc.c:
> > >
> > > ChangeLog:
> > >
> > >       * sim/bpf/bpf-sim.c (execute):
> >
> > Not commenting on the rest of the patch but there's missing text
> > after ":" above. Beware: gcc/contrib/mklog.py doesn't help with
> > that part. :)
> >
>
> Thank you! I thought something looked suspicious but because it was
> what contrib/mklog.py gave me, I assumed you all had special
> requirements! I will fix it and resubmit.
>
> Thank you again!
> Will
>
>

Please disregard this version of the patch. I will resubmit a v2 patch
soon. There is a discrepancy between the way that gcc encodes the
callx (aka callr) and the way that clang encodes the callx. I am
working with the author of the IETF standardization document for the
BPF ISA to understand how the instruction encoding will be specified.
Once that discussion has concluded, I will resubmit the patch.

Sorry for the extra emails.

Will


>
> > Happy hacking!
> >
> > brgds, H-P
diff mbox series

Patch

diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h
index df1e3bd0918..48cef368e4e 100644
--- a/include/opcode/bpf.h
+++ b/include/opcode/bpf.h
@@ -202,7 +202,7 @@  enum bpf_insn_id
   BPF_INSN_JAR, BPF_INSN_JEQR, BPF_INSN_JGTR, BPF_INSN_JSGTR,
   BPF_INSN_JGER, BPF_INSN_JSGER, BPF_INSN_JLTR, BPF_INSN_JSLTR,
   BPF_INSN_JSLER, BPF_INSN_JLER, BPF_INSN_JSETR, BPF_INSN_JNER,
-  BPF_INSN_CALLR, BPF_INSN_CALL, BPF_INSN_EXIT,
+  BPF_INSN_CALLR, BPF_INSN_CALLX, BPF_INSN_CALL, BPF_INSN_EXIT,
   /* Compare-and-jump instructions (reg OP imm.)  */
   BPF_INSN_JEQI, BPF_INSN_JGTI, BPF_INSN_JSGTI,
   BPF_INSN_JGEI, BPF_INSN_JSGEI, BPF_INSN_JLTI, BPF_INSN_JSLTI,
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index 19e096501a2..3f030a39c1b 100644
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -274,6 +274,8 @@  const struct bpf_opcode bpf_opcodes[] =
    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_X},
   {BPF_INSN_CALLR, "call%W%dr", "callx%w%dr",
    BPF_XBPF, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_X},
+  {BPF_INSN_CALLX, "callx%W%dr", "callx%w%dr",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_X},
   {BPF_INSN_CALL, "call%W%d32", "call%w%d32",
    BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_K},
   {BPF_INSN_EXIT, "exit", "exit",
diff --git a/sim/bpf/bpf-sim.c b/sim/bpf/bpf-sim.c
index c1f103823fb..a3976d0b4bf 100644
--- a/sim/bpf/bpf-sim.c
+++ b/sim/bpf/bpf-sim.c
@@ -1096,6 +1096,10 @@  execute (SIM_CPU *cpu, struct bpf_insn *insn)
       BPF_TRACE ("BPF_INSN_CALLR\n");
       bpf_call (cpu, DISP (bpf_regs[insn->dst]), insn->src);
       break;
+    case BPF_INSN_CALLX:
+      BPF_TRACE ("BPF_INSN_CALLX\n");
+      bpf_call (cpu, DISP (bpf_regs[insn->dst]), insn->src);
+      break;
     case BPF_INSN_CALL:
       BPF_TRACE ("BPF_INSN_CALL\n");
       bpf_call (cpu, insn->imm32, insn->src);