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[8.43.85.97]) by mx.google.com with ESMTPS id r23-20020a0cb297000000b0067f06f0a9c1si6743245qve.200.2023.12.18.01.29.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Dec 2023 01:29:49 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 65EE53857C4B for ; Mon, 18 Dec 2023 09:29:49 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-111.freemail.mail.aliyun.com (out30-111.freemail.mail.aliyun.com [115.124.30.111]) by sourceware.org (Postfix) with ESMTPS id B55733858424 for ; Mon, 18 Dec 2023 09:29:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B55733858424 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org B55733858424 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.111 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702891784; cv=none; b=mOjjcuMnng/+emrBiOmfd4PDCLzl9eqAC7Zp4G3M0dqYtgmG3mkplvsxWDm9aa3b+Fn6gD0uYjO/paQw3Tk16m3dwLd8TRBEp+AoM+GYWAVmzjpbwD/K7bA5XJQ2FoKHq+N/MTwTFSlsr3XZduvbxjWjFTN5VA6Ozjib9AglRdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702891784; c=relaxed/simple; bh=Qgsu7WZnA/VKreu20dDasFJtsov+mpHXEg3f8XsNxWs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=Jl2z0SY2vu0wfXy3BveKyaZ39WHoP1tnY4h0H57NNRy+BH2Kdz4WlZPgtDeNu5XmVXDtON+G4st9wStlo86DIksg3piAY9BNsfnYSx5Nits/Iek+w6ze0HjeJg5Ex/XK+jnHeYm4/JIxsQiYvDKa1XE6oG1WHXy9ta0FQKw2Hx0= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R101e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vyjvlt2_1702891769; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vyjvlt2_1702891769) by smtp.aliyun-inc.com; Mon, 18 Dec 2023 17:29:31 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvl Date: Mon, 18 Dec 2023 17:29:21 +0800 Message-Id: <20231218092921.239-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-20.7 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1785611460927614238 X-GMAIL-MSGID: 1785611460927614238 Since the particularity of "vsetvl" was not taken into account in the initial support patches for XTheadVector, the program operation failed due to instruction coding errors. According to T-Head SPEC ([1]), the "vsetvl" in the XTheadVector extension consists of SEW, LMUL and EDIV, which is quite different from the "V" extension. Therefore, we cannot simply reuse the processing of vsetvl in V extension. We have set up tens of thousands of test cases to ensure that no further encoding issues are there, and and execute all compiled test files on real HW and make sure they don't trigger SIGILL. Ref: [1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * config/tc-riscv.c (my_getVsetvliExpression): Add handling for the XTheadVector extension. * testsuite/gas/riscv/x-thead-vector.d: Change test. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv.h (OP_MASK_XTHEADVLMUL): New macro. (OP_SH_XTHEADVLMUL): Likewise. (OP_MASK_XTHEADVSEW): Likewise. (OP_SH_XTHEADVSEW): Likewise. (OP_MASK_XTHEADVEDIV): Likewise. (OP_SH_XTHEADVEDIV): Likewise. (OP_MASK_XTHEADVTYPE_RES): Likewise. (OP_SH_XTHEADVTYPE_RES): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Likewise. * riscv-opc.c: Likewise. --- gas/config/tc-riscv.c | 49 ++++++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.d | 3 +- gas/testsuite/gas/riscv/x-thead-vector.s | 1 + include/opcode/riscv.h | 11 ++++++ opcodes/riscv-dis.c | 20 ++++++++++ opcodes/riscv-opc.c | 12 ++++++ 6 files changed, 95 insertions(+), 1 deletion(-) base-commit: c4fb39bb31a53bbb2df3be3200d694f025c5b892 diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index b902c6ba2c1..eb6e5260016 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -2371,8 +2371,57 @@ my_getVsetvliExpression (expressionS *ep, char *str) { unsigned int vsew_value = 0, vlmul_value = 0; unsigned int vta_value = 0, vma_value = 0; + unsigned int vlen_value = 0, vediv_value = 0; /* XTheadVector. */ bfd_boolean vsew_found = FALSE, vlmul_found = FALSE; bfd_boolean vta_found = FALSE, vma_found = FALSE; + bfd_boolean vlen_found = FALSE, vediv_found = FALSE; /* XTheadVector. */ + + /* Vsetvl has a different expression for XTheadVector. */ + if (riscv_subset_supports (&riscv_rps_as, "xtheadvector")) + { + if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), + &vsew_value)) + { + if (*str == ',') + ++str; + if (vsew_found) + as_bad (_("multiple vsew constants")); + vsew_found = TRUE; + } + + if (arg_lookup (&str, riscv_vlen, ARRAY_SIZE (riscv_vlen), + &vlen_value)) + { + if (*str == ',') + ++str; + if (vlen_found) + as_bad (_("multiple vlen constants")); + vlen_found = TRUE; + } + if (arg_lookup (&str, riscv_vediv, ARRAY_SIZE (riscv_vediv), + &vediv_value)) + { + if (*str == ',') + ++str; + if (vediv_found) + as_bad (_("multiple vediv constants")); + vediv_found = TRUE; + } + + if (vlen_found || vediv_found || vsew_found) + { + ep->X_op = O_constant; + ep->X_add_number + = (vediv_value << 5) | (vsew_value << 2) | (vlen_value); + expr_parse_end = str; + } + else + { + my_getExpression (ep, str); + str = expr_parse_end; + } + return; + } if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value)) { diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index 014c2fdb80d..17b30dd1064 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -8,8 +8,9 @@ Disassembly of section .text: 0+000 <.text>: [ ]+[0-9a-f]+:[ ]+80c5f557[ ]+th.vsetvl[ ]+a0,a1,a2 -[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,tu,mu +[ ]+[0-9a-f]+:[ ]+0005f557[ ]+th.vsetvli[ ]+a0,a1,e8,m1,d1 [ ]+[0-9a-f]+:[ ]+7ff5f557[ ]+th.vsetvli[ ]+a0,a1,2047 +[ ]+[0-9a-f]+:[ ]+0455f557[ ]+th.vsetvli[ ]+a0,a1,e16,m2,d4 [ ]+[0-9a-f]+:[ ]+12050207[ ]+th.vlb.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+12050207[ ]+th.vlb.v[ ]+v4,\(a0\) [ ]+[0-9a-f]+:[ ]+10050207[ ]+th.vlb.v[ ]+v4,\(a0\),v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index 3a4dea38c8b..43c63a45735 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -1,6 +1,7 @@ th.vsetvl a0, a1, a2 th.vsetvli a0, a1, 0 th.vsetvli a0, a1, 0x7ff + th.vsetvli a0, a1, e16,m2,d4 th.vlb.v v4, (a0) th.vlb.v v4, 0(a0) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 6687b434074..179d122a83c 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -328,6 +328,15 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define OP_MASK_VWD 0x1 #define OP_SH_VWD 26 +#define OP_MASK_XTHEADVLMUL 0x3 +#define OP_SH_XTHEADVLMUL 0 +#define OP_MASK_XTHEADVSEW 0x7 +#define OP_SH_XTHEADVSEW 2 +#define OP_MASK_XTHEADVEDIV 0x3 +#define OP_SH_XTHEADVEDIV 5 +#define OP_MASK_XTHEADVTYPE_RES 0xf +#define OP_SH_XTHEADVTYPE_RES 7 + #define NVECR 32 #define NVECM 1 @@ -595,6 +604,8 @@ extern const char * const riscv_vsew[8]; extern const char * const riscv_vlmul[8]; extern const char * const riscv_vta[2]; extern const char * const riscv_vma[2]; +extern const char * const riscv_vlen[4]; +extern const char * const riscv_vediv[4]; extern const char * const riscv_fli_symval[32]; extern const float riscv_fli_numval[32]; diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 68674380797..ef01cb4af27 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -367,6 +367,26 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info { int imm = (*oparg == 'b') ? EXTRACT_RVV_VB_IMM (l) : EXTRACT_RVV_VC_IMM (l); + + if (riscv_subset_supports (&riscv_rps_dis, "xtheadvector")) + { + unsigned int imm_vediv = EXTRACT_OPERAND (XTHEADVEDIV, imm); + unsigned int imm_vlmul = EXTRACT_OPERAND (XTHEADVLMUL, imm); + unsigned int imm_vsew = EXTRACT_OPERAND (XTHEADVSEW, imm); + unsigned int imm_vtype_res + = EXTRACT_OPERAND (XTHEADVTYPE_RES, imm); + if (imm_vsew < ARRAY_SIZE (riscv_vsew) + && imm_vlmul < ARRAY_SIZE (riscv_vlen) + && imm_vediv < ARRAY_SIZE (riscv_vediv) + && ! imm_vtype_res) + print (info->stream, dis_style_text, "%s,%s,%s", + riscv_vsew[imm_vsew], riscv_vlen[imm_vlmul], + riscv_vediv[imm_vediv]); + else + print (info->stream, dis_style_immediate, "%d", imm); + break; + } + unsigned int imm_vlmul = EXTRACT_OPERAND (VLMUL, imm); unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm); unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm); diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bf388cdaa2f..d5619ddbc41 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -110,6 +110,18 @@ const char * const riscv_vma[2] = "mu", "ma" }; +/* XTheadVector, List of vsetvli vlmul constants. */ +const char * const riscv_vlen[4] = +{ + "m1", "m2", "m4", "m8" +}; + +/* XTheadVector, List of vsetvli vediv constants. */ +const char * const riscv_vediv[4] = +{ + "d1", "d2", "d4", "d8" +}; + /* The FLI.[HSDQ] symbolic constants (NULL for numeric constant). */ const char * const riscv_fli_symval[32] = {