From patchwork Fri Dec 8 16:03:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jens Remus X-Patchwork-Id: 175882 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp5550861vqy; Fri, 8 Dec 2023 08:03:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IEuItgj9Cnu16rK1JfOxoXG8QyDikoOTdhhAXxQEG+JpRxQYXuZ18nba0n6qVCyCZH8rBiS X-Received: by 2002:ac8:580b:0:b0:425:4043:7655 with SMTP id g11-20020ac8580b000000b0042540437655mr370542qtg.125.1702051438671; Fri, 08 Dec 2023 08:03:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1702051438; cv=pass; d=google.com; s=arc-20160816; b=jpXwIcxlfkUetaMoZU5leU4H0JnlUf0K6dI3qHGwCRGAR4VsG4NYzU4bZS8lpZ4YxR SK9y349mFWh1qso3SKh0+saGjE8kHRI9iLw3KipQFk3P+2372S8n3oMDeeEcbx5aiQLo DXzU0HyjVoW3CtoUu+cbGQ2S4A3RD4r3C3CzT9kDfdMqQkGReWvxKym7a5mxcKYO6Dhp C+S5WtNgZRuwW/rNJstZdTNcjuXIOLCyamwcx8QY/k/z0SEE4UcF3JzJ8fWvWcErq/Gi 0P/FwW+av3gkKK+JGDU79486maExGqaM9FZdzfGXD9d6Jhcoq7Fi3zuWXlwg7tsl3pLk rSKQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=FyJCZ4Ty9WJYtufI1nPdY7PsH2/ufpP7htfMYcs5Qdc=; fh=lE3HXkiifBSVPU+f05x++3qNjjxlDvLZxwnRCBzavKo=; b=U3xGsCn9QjQxHBD/moEcjp1YL93Mi4LWcNcW/OsHg2g7FmIj0LrApcIvEGE5exO9vO 9/v4UBh5K0J8qhru6ceDDFno2+w3OWn2KnMYBls+2T1OVDeIWvnlj1MUM26n6yJ0DtAN juURX4i2Mg1TfF4aIBiIy0H8MoGPPAROxVoDzhoCKd+x2NOM6dxFzamdyxeVsyH5sBiZ EV6CXM1T4OSmEcyt9ZoqtGVR6AY03dLPQG+aq/QcVCDfrfJLKiYd7S6dtaPsRiqbKqwj Bzji9RE4t2fwHuIAL8B+9jA/I++EeIDb3IfIJc2maFzBgem1Yf+gZVRM39/GlCuOJioo fp9g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=BvI8ylzZ; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id s22-20020ab02896000000b007c3df377d1dsi493184uap.213.2023.12.08.08.03.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 08:03:58 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@ibm.com header.s=pp1 header.b=BvI8ylzZ; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=REJECT sp=NONE dis=NONE) header.from=ibm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 551DF3858422 for ; Fri, 8 Dec 2023 16:03:55 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 39B4D3858C20 for ; Fri, 8 Dec 2023 16:03:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 39B4D3858C20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 39B4D3858C20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702051425; cv=none; b=MMYjH8RMnA99qvHH1nPp4BX3Xlqx5PVMiQfsr3X/e8aY6PQawYZ4KOrmwbCnbAGrG5PAjO7xxpNIE1KGwDIJuUomcGusGowoiVA78iQClQabduE6RNfqpxwsqyRrySZ1i8sna6Vi3oOwwSDr/pfnSn+KpE9JtKfIZIszDjVQU/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1702051425; c=relaxed/simple; bh=B/QwSYNzE/jc0RfQyVwk7De/XrED9kmelsUUx98yGEY=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=ApMkPVftJ8w4Hyv3s8wR/805YNu+nazBxh2H9aOb2DVj6J3/k1yvUyfCNNFGlUY7+Lto6dDJvPElWbPFPRWUvrwKom040D4aljCIAZr+Tq8GA7ENITOhIH+s/Z+02qWvhWxZiNJxJCFvNhFH7XpOjAXioWeMvEjk9hj+ehzRpK8= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0353727.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3B8G2JD1016475 for ; Fri, 8 Dec 2023 16:03:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=FyJCZ4Ty9WJYtufI1nPdY7PsH2/ufpP7htfMYcs5Qdc=; b=BvI8ylzZOocKubgldzP/sWy6JZ8jp2k6e8V1k8oyjOnPnbIhOJIPQ6ALlYQfT7QVIfG2 joCKlz2nA/uwGhaYrriZSxDjE5g48EToVSvFaZXXE8Kv6ys31jpXA/AaqXiLvEaqS5hE WgATGXY0FAFaPzvu7vQoqVgb7ftDco+q87uFh4B6hSrC76dXADeKXqkDUORtg0KkWRsW l17Tsn2ZduVUQ3QE/9+Hh9PGnmoxTA2mhvb9pInmF6LZBLHDVSmvPFRgJBkNnxG/1rWG SQeXkFOnM2iJEndinPC+4+M2n7I3sPBeba9Te5u4/nXVzPNnVPEAX2pPFIz0yXh0th73 hg== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3uv6acg0uq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 08 Dec 2023 16:03:40 +0000 Received: from m0353727.ppops.net (m0353727.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 3B8G33Xg018841 for ; Fri, 8 Dec 2023 16:03:40 GMT Received: from ppma23.wdc07v.mail.ibm.com (5d.69.3da9.ip4.static.sl-reverse.com [169.61.105.93]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3uv6acg0tt-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 08 Dec 2023 16:03:40 +0000 Received: from pps.filterd (ppma23.wdc07v.mail.ibm.com [127.0.0.1]) by ppma23.wdc07v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 3B8DbmsJ013754; Fri, 8 Dec 2023 16:03:39 GMT Received: from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225]) by ppma23.wdc07v.mail.ibm.com (PPS) with ESMTPS id 3utau4jf3t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 08 Dec 2023 16:03:39 +0000 Received: from smtpav05.fra02v.mail.ibm.com (smtpav05.fra02v.mail.ibm.com [10.20.54.104]) by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 3B8G3at911928082 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 8 Dec 2023 16:03:36 GMT Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DEB3420040; Fri, 8 Dec 2023 16:03:35 +0000 (GMT) Received: from smtpav05.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B574620043; Fri, 8 Dec 2023 16:03:35 +0000 (GMT) Received: from tuxmaker.boeblingen.de.ibm.com (unknown [9.152.85.9]) by smtpav05.fra02v.mail.ibm.com (Postfix) with ESMTP; Fri, 8 Dec 2023 16:03:35 +0000 (GMT) From: Jens Remus To: binutils@sourceware.org Cc: Jens Remus , Andreas Krebbel , Nick Clifton Subject: [PATCH 2/2] s390: Optionally print instruction description in disassembly Date: Fri, 8 Dec 2023 17:03:30 +0100 Message-Id: <20231208160330.1387610-3-jremus@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231208160330.1387610-1-jremus@linux.ibm.com> References: <20231208160330.1387610-1-jremus@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 5NOEhu84wE4pAdT8xB3hC4T8xcX4OT-e X-Proofpoint-ORIG-GUID: prJ-3-CpqZCIczXMxZYy_SG3x4FYTWjS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-08_11,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2312080132 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784730289288216060 X-GMAIL-MSGID: 1784730289288216060 Print instruction description as comment in disassembly with s390 architecture specific option "insndesc": - For objdump it can be enabled with option "-M insndesc" - In gdb it can be enabled with "set disassembler-options insndesc" Since comments are not column aligned the output can enhanced for readability by postprocessing using a filter such as "expand": ... | expand -t 8,16,24,32,40,80 Or when using in combination with objdump option --visualize-jumps: ... | expand | sed -e 's/ *#/\t#/' | expand -t 1,80 Note that the instruction descriptions add about 128 KB to s390-opc.o: s390-opc.o without instruction descriptions: 216368 bytes s390-opc.o with instruction descriptions : 348432 bytes binutils/ * NEWS: Mention new s390-specific disassembler option "insndesc". include/ * opcode/s390.h (struct s390_opcode): Add field to hold instruction description. opcodes/ * s390-mkopc.c: Copy instruction description from s390-opc.txt into generated operation code table s390-opc.tab. * s390-opc.c (s390_opformats): Provide NULL as description in .insn pseudo-mnemonics opcode table. * s390-dis.c: Add s390 specific disassembler option "insndesc" and optionally print the instruction description as comment in the disassembly when it is specified. Signed-off-by: Jens Remus Reviewed-by: Andreas Krebbel --- binutils/NEWS | 5 ++++ include/opcode/s390.h | 5 +++- opcodes/s390-dis.c | 13 ++++++++- opcodes/s390-mkopc.c | 18 ++++++++----- opcodes/s390-opc.c | 62 +++++++++++++++++++++---------------------- 5 files changed, 63 insertions(+), 40 deletions(-) diff --git a/binutils/NEWS b/binutils/NEWS index 73df7053be4..35b84e62b95 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -19,6 +19,11 @@ * objdump --visualize-jumps is now supported on s390 architecture. +* The s390 disassembly now optionally includes the instruction description as + comment with the s390-specific disassembler option "insndesc": + - For objdump it can be enabled with "objdump -M insndesc ...". + - In gdb it can be enabled with "set disassembler-options insndesc". + Changes in 2.41: * The MIPS port now supports the Sony Interactive Entertainment Allegrex diff --git a/include/opcode/s390.h b/include/opcode/s390.h index d540e1dfd00..319bfe2d629 100644 --- a/include/opcode/s390.h +++ b/include/opcode/s390.h @@ -81,7 +81,7 @@ enum s390_opcode_cpu_val struct s390_opcode { - /* The opcode name. */ + /* The opcode name (mnemonic). */ const char * name; /* The opcode itself. Those bits which will be filled in with @@ -110,6 +110,9 @@ struct s390_opcode /* Instruction specific flags. */ unsigned int flags; + + /* Instruction description. */ + const char * description; }; /* The table itself is sorted by major opcode number, and is otherwise diff --git a/opcodes/s390-dis.c b/opcodes/s390-dis.c index 8c8a98c4e24..fca965fbb5d 100644 --- a/opcodes/s390-dis.c +++ b/opcodes/s390-dis.c @@ -31,6 +31,7 @@ static int opc_index[256]; static int current_arch_mask = 0; static int option_use_insn_len_bits_p = 0; +static int option_print_insn_desc = 0; typedef struct { @@ -43,7 +44,8 @@ static const s390_options_t options[] = { "esa" , N_("Disassemble in ESA architecture mode") }, { "zarch", N_("Disassemble in z/Architecture mode") }, { "insnlength", N_("Print unknown instructions according to " - "length from first two bits") } + "length from first two bits") }, + { "insndesc", N_("Print instruction description as comment") }, }; /* Set up index table for first opcode byte. */ @@ -63,6 +65,7 @@ disassemble_init_s390 (struct disassemble_info *info) current_arch_mask = 1 << S390_OPCODE_ZARCH; option_use_insn_len_bits_p = 0; + option_print_insn_desc = 0; for (p = info->disassembler_options; p != NULL; ) { @@ -72,6 +75,8 @@ disassemble_init_s390 (struct disassemble_info *info) current_arch_mask = 1 << S390_OPCODE_ZARCH; else if (startswith (p, "insnlength")) option_use_insn_len_bits_p = 1; + else if (startswith (p, "insndesc")) + option_print_insn_desc = 1; else /* xgettext:c-format */ opcodes_error_handler (_("unknown S/390 disassembler option: %s"), p); @@ -311,6 +316,12 @@ s390_print_insn_with_opcode (bfd_vma memaddr, else separator = ','; } + + /* Optional: instruction name. */ + if (option_print_insn_desc && opcode->description + && opcode->description[0] != '\0') + info->fprintf_styled_func (info->stream, dis_style_comment_start, "\t# %s", + opcode->description); } /* Check whether opcode A's mask is more specific than that of B. */ diff --git a/opcodes/s390-mkopc.c b/opcodes/s390-mkopc.c index 5f921ee0628..80ffe42978c 100644 --- a/opcodes/s390-mkopc.c +++ b/opcodes/s390-mkopc.c @@ -32,6 +32,7 @@ struct op_struct int mode_bits; int min_cpu; int flags; + char description[80]; unsigned long long sort_value; int no_nibbles; @@ -53,7 +54,7 @@ createTable (void) static void insertOpcode (char *opcode, char *mnemonic, char *format, - int min_cpu, int mode_bits, int flags) + int min_cpu, int mode_bits, int flags, char* description) { char *str; unsigned long long sort_value; @@ -98,6 +99,7 @@ insertOpcode (char *opcode, char *mnemonic, char *format, op_array[ix].min_cpu = min_cpu; op_array[ix].mode_bits = mode_bits; op_array[ix].flags = flags; + strcpy(op_array[ix].description, description); no_ops++; } @@ -159,7 +161,7 @@ const struct s390_cond_ext_format s390_crb_extensions[NUM_CRB_EXTENSIONS] = static void insertExpandedMnemonic (char *opcode, char *mnemonic, char *format, - int min_cpu, int mode_bits, int flags) + int min_cpu, int mode_bits, int flags, char *description) { char *tag; char prefix[15]; @@ -172,7 +174,7 @@ insertExpandedMnemonic (char *opcode, char *mnemonic, char *format, if (!(tag = strpbrk (mnemonic, "*$"))) { - insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits, flags); + insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits, flags, description); return; } @@ -252,7 +254,7 @@ insertExpandedMnemonic (char *opcode, char *mnemonic, char *format, opcode[mask_start] = ext_table[i].nibble; strcat (new_mnemonic, ext_table[i].extension); strcat (new_mnemonic, suffix); - insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits, flags); + insertOpcode (opcode, new_mnemonic, format, min_cpu, mode_bits, flags, description); } return; @@ -273,7 +275,8 @@ static const char file_header[] = " instruction which matches.\n" " MODE_BITS - zarch or esa\n" " MIN_CPU - number of the min cpu level required\n" - " FLAGS - instruction flags. */\n\n" + " FLAGS - instruction flags.\n" + " DESCRIPTION - description of the instruction. */\n\n" "const struct s390_opcode s390_opcodes[] =\n {\n"; /* `dumpTable': write opcode table. */ @@ -299,7 +302,8 @@ dumpTable (void) op_array[ix].format, op_array[ix].format); printf ("%i, ", op_array[ix].mode_bits); printf ("%i, ", op_array[ix].min_cpu); - printf ("%i}", op_array[ix].flags); + printf ("%i, ", op_array[ix].flags); + printf ("\"%s\" }", op_array[ix].description); if (ix < no_ops-1) printf (",\n"); else @@ -452,7 +456,7 @@ main (void) str++; } while (*str != 0); } - insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits, flag_bits); + insertExpandedMnemonic (opcode, mnemonic, format, min_cpu, mode_bits, flag_bits, description); } dumpTable (); diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index cbfdb3df0b7..e44621a7479 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -774,37 +774,37 @@ unused_s390_operands_static_asserts (void) const struct s390_opcode s390_opformats[] = { - { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 }, - { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 }, - { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 }, - { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 }, - { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 }, - { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6 ,0 }, - { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 }, - { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 }, - { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 }, - { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6 ,0 }, - { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 }, - { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 }, - { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 }, - { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 }, - { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 }, - { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 }, - { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0 ,0 }, - { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 }, - { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 }, - { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 }, - { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 }, - { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 }, - { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0 ,0 }, - { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 }, - { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0 ,0 }, - { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9 ,0 }, - { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9 ,0 }, - { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9 ,0 }, - { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9 ,0 }, - { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9 ,0 }, - { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10 ,0 }, + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0, 0, NULL }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0, NULL }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0, 0, NULL }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0, 0, NULL }, + { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0, 0, NULL }, + { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6, 0, NULL }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, NULL }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, NULL }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 0, NULL }, + { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6, 0, NULL }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, NULL }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0, 0, NULL }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 0, NULL }, + { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 0, NULL }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, NULL }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0, 0, NULL }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0, 0, NULL }, + { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, NULL }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, NULL }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, NULL }, + { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3, 0, NULL }, + { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6, 0, NULL }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0, NULL }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0, NULL }, + { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0, 0, NULL }, + { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9, 0, NULL }, + { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9, 0, NULL }, + { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9, 0, NULL }, + { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9, 0, NULL }, + { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9, 0, NULL }, + { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10, 0, NULL }, }; const int s390_num_opformats =