@@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
{"zvl256b", "zvl128b", check_implicit_always},
{"zvl128b", "zvl64b", check_implicit_always},
{"zvl64b", "zvl32b", check_implicit_always},
+ {"zicntr", "zicsr", check_implicit_always},
+ {"zihpm", "zicsr", check_implicit_always},
{"zcd", "d", check_implicit_always},
{"zcf", "f", check_implicit_always},
{"zfa", "f", check_implicit_always},
@@ -1260,12 +1262,14 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 },
{"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 },
{"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
+ {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 },
{"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
new file mode 100644
@@ -0,0 +1,6 @@
+#as: -march-attr -misa-spec=20191213
+#readelf: -A
+#source: attribute-15.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
new file mode 100644
@@ -0,0 +1 @@
+ .attribute arch,"rv32i_zicntr_zihpm"
new file mode 100644
@@ -0,0 +1,6 @@
+#as: -march-attr -misa-spec=20191213
+#readelf: -A
+#source: attribute-16.s
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv64i2p1_zicntr2p0_zicsr2p0_zihpm2p0"
new file mode 100644
@@ -0,0 +1 @@
+ .attribute arch,"rv64i_zicntr_zihpm"