diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 97219b64011..09dbd2d6e4d 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1199,6 +1199,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"ssstateen", "zicsr",	check_implicit_always},
   {"sstc", "zicsr",		check_implicit_always},
   {"svadu", "zicsr",		check_implicit_always},
+
+  {"xsfvcp", "zve32x",  check_implicit_always},
   {NULL, NULL, NULL}
 };
 
@@ -1376,6 +1378,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
   {"xtheadvector",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xtheadzvamo",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
   {"xventanacondops",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
+  {"xsfvcp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0},
   {NULL, 0, 0, 0, 0}
 };
 
@@ -2595,6 +2598,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "xtheadzvamo");
     case INSN_CLASS_XVENTANACONDOPS:
       return riscv_subset_supports (rps, "xventanacondops");
+    case INSN_CLASS_XSFVCP:
+      return riscv_subset_supports (rps, "xsfvcp");
     default:
       rps->error_handler
         (_("internal: unreachable INSN_CLASS_*"));
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index af9a34a2185..9922c47dc22 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1499,6 +1499,24 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		    goto unknown_validate_operand;
 		}
 	      break;
+	    case 's': /* Vendor-specific (SiFive) operands.  */
+	      switch (*++oparg)
+		{
+		  case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
+		  case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
+		  case 'O':
+		    switch (*++oparg)
+		      {
+			case '2': USE_BITS (OP_MASK_XSO2, OP_SH_XSO2); break;
+			case '1': USE_BITS (OP_MASK_XSO1, OP_SH_XSO1); break;
+			default:
+			  goto unknown_validate_operand;
+		      }
+		    break;
+		  default:
+		    goto unknown_validate_operand;
+		}
+		break;
 	    default:
 	      goto unknown_validate_operand;
 	    }
@@ -3626,7 +3644,55 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 			goto unknown_riscv_ip_operand;
 		    }
 		  break;
-
+		case 's': /* Vendor-specific (SiFive) operands.  */
+#define UIMM_BITFIELD_VAL(S, E) (1 << ((E) - (S) + 1))
+#define ENCODE_UIMM_BIT_FIELD(NAME, IP, EXPR, RELOC, ASARG, \
+			      START, END) \
+  do \
+    { \
+      if (my_getOpcodeExpression (EXPR, RELOC, ASARG) \
+	  || EXPR->X_op != O_constant \
+	  || EXPR->X_add_number < 0 \
+	  || EXPR->X_add_number >= UIMM_BITFIELD_VAL (START, END)) \
+	{ \
+	  as_bad (_("bad value for <bit-%s-%s> " \
+		    "field, value must be 0...%d"), \
+		  #START, #END, UIMM_BITFIELD_VAL (START, END)); \
+	  break; \
+	} \
+      INSERT_OPERAND (NAME, *IP, EXPR->X_add_number); \
+      EXPR->X_op = O_absent; \
+      ASARG = expr_parse_end; \
+    } \
+  while (0);
+		  switch (*++oparg)
+		    {
+		    case 'd': /* Xsd */
+		      ENCODE_UIMM_BIT_FIELD
+			(RD, ip, imm_expr, imm_reloc, asarg, 7, 11);
+		      continue;
+		    case 't': /* Xst */
+		      ENCODE_UIMM_BIT_FIELD
+			(RS2, ip, imm_expr, imm_reloc, asarg, 20, 24)
+		      continue;
+		    case 'O':
+		      switch (*++oparg)
+			{
+			case '2': /* XsO2 */
+			  ENCODE_UIMM_BIT_FIELD
+			    (XSO2, ip, imm_expr, imm_reloc, asarg, 26, 27);
+			  continue;
+			case '1': /* XsO1 */
+			  ENCODE_UIMM_BIT_FIELD
+			    (XSO1, ip, imm_expr, imm_reloc, asarg, 26, 26);
+			  continue;
+			}
+		    default:
+		      goto unknown_riscv_ip_operand;
+		    }
+#undef UIMM_BITFIELD_VAL
+#undef ENCODE_UIMM_BIT_FIELD
+		  break;
 		default:
 		  goto unknown_riscv_ip_operand;
 		}
diff --git a/gas/testsuite/gas/riscv/sifive-insns.d b/gas/testsuite/gas/riscv/sifive-insns.d
new file mode 100644
index 00000000000..f7d63d1bce0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/sifive-insns.d
@@ -0,0 +1,37 @@
+#as:
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+0ef5cfdb[ 	]+sf.vc.x[ 	]+0x3,0xf,0x1f,a1
+[ 	]+[0-9a-f]+:[ 	]+0ef7bfdb[ 	]+sf.vc.i[ 	]+0x3,0xf,0x1f,15
+[ 	]+[0-9a-f]+:[ 	]+2e208fdb[ 	]+sf.vc.vv[ 	]+0x3,0x1f,v2,v1
+[ 	]+[0-9a-f]+:[ 	]+2e25cfdb[ 	]+sf.vc.xv[ 	]+0x3,0x1f,v2,a1
+[ 	]+[0-9a-f]+:[ 	]+2e27bfdb[ 	]+sf.vc.iv[ 	]+0x3,0x1f,v2,15
+[ 	]+[0-9a-f]+:[ 	]+2e25dfdb[ 	]+sf.vc.fv[ 	]+0x1,0x1f,v2,fa1
+[ 	]+[0-9a-f]+:[ 	]+ae20805b[ 	]+sf.vc.vvv[ 	]+0x3,v0,v2,v1
+[ 	]+[0-9a-f]+:[ 	]+ae25c05b[ 	]+sf.vc.xvv[ 	]+0x3,v0,v2,a1
+[ 	]+[0-9a-f]+:[ 	]+ae27b05b[ 	]+sf.vc.ivv[ 	]+0x3,v0,v2,15
+[ 	]+[0-9a-f]+:[ 	]+ae25d05b[ 	]+sf.vc.fvv[ 	]+0x1,v0,v2,fa1
+[ 	]+[0-9a-f]+:[ 	]+fe20805b[ 	]+sf.vc.vvw[ 	]+0x3,v0,v2,v1
+[ 	]+[0-9a-f]+:[ 	]+fe25c05b[ 	]+sf.vc.xvw[ 	]+0x3,v0,v2,a1
+[ 	]+[0-9a-f]+:[ 	]+fe27b05b[ 	]+sf.vc.ivw[ 	]+0x3,v0,v2,15
+[ 	]+[0-9a-f]+:[ 	]+fe25d05b[ 	]+sf.vc.fvw[ 	]+0x1,v0,v2,fa1
+[ 	]+[0-9a-f]+:[ 	]+0cf5c05b[ 	]+sf.vc.v.x[ 	]+0x3,0xf,v0,a1
+[ 	]+[0-9a-f]+:[ 	]+0cf7b05b[ 	]+sf.vc.v.i[ 	]+0x3,0xf,v0,15
+[ 	]+[0-9a-f]+:[ 	]+2c20805b[ 	]+sf.vc.v.vv[ 	]+0x3,v0,v2,v1
+[ 	]+[0-9a-f]+:[ 	]+2c25c05b[ 	]+sf.vc.v.xv[ 	]+0x3,v0,v2,a1
+[ 	]+[0-9a-f]+:[ 	]+2c27b05b[ 	]+sf.vc.v.iv[ 	]+0x3,v0,v2,15
+[ 	]+[0-9a-f]+:[ 	]+2c25d05b[ 	]+sf.vc.v.fv[ 	]+0x1,v0,v2,fa1
+[ 	]+[0-9a-f]+:[ 	]+ac20805b[ 	]+sf.vc.v.vvv[ 	]+0x3,v0,v2,v1
+[ 	]+[0-9a-f]+:[ 	]+ac25c05b[ 	]+sf.vc.v.xvv[ 	]+0x3,v0,v2,a1
+[ 	]+[0-9a-f]+:[ 	]+ac27b05b[ 	]+sf.vc.v.ivv[ 	]+0x3,v0,v2,15
+[ 	]+[0-9a-f]+:[ 	]+ac25d05b[ 	]+sf.vc.v.fvv[ 	]+0x1,v0,v2,fa1
+[ 	]+[0-9a-f]+:[ 	]+fc20805b[ 	]+sf.vc.v.vvw[ 	]+0x3,v0,v2,v1
+[ 	]+[0-9a-f]+:[ 	]+fc25c05b[ 	]+sf.vc.v.xvw[ 	]+0x3,v0,v2,a1
+[ 	]+[0-9a-f]+:[ 	]+fc27b05b[ 	]+sf.vc.v.ivw[ 	]+0x3,v0,v2,15
+[ 	]+[0-9a-f]+:[ 	]+fc25d05b[ 	]+sf.vc.v.fvw[ 	]+0x1,v0,v2,fa1
diff --git a/gas/testsuite/gas/riscv/sifive-insns.s b/gas/testsuite/gas/riscv/sifive-insns.s
new file mode 100644
index 00000000000..d593692c5c0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/sifive-insns.s
@@ -0,0 +1,33 @@
+	.attribute arch, "rv32iv"
+	# xsfvcp
+	.option push
+	.option arch, +xsfvcp
+	sf.vc.x 0x3, 0xf, 0x1f, a1
+	sf.vc.i 0x3, 0xf, 0x1f, 15
+	sf.vc.vv 0x3, 0x1f, v2, v1
+	sf.vc.xv 0x3, 0x1f, v2, a1
+	sf.vc.iv 0x3, 0x1f, v2, 15
+	sf.vc.fv 0x1, 0x1f, v2, fa1
+	sf.vc.vvv 0x3, v0, v2, v1
+	sf.vc.xvv 0x3, v0, v2, a1
+	sf.vc.ivv 0x3, v0, v2, 15
+	sf.vc.fvv 0x1, v0, v2, fa1
+	sf.vc.vvw 0x3, v0, v2, v1
+	sf.vc.xvw 0x3, v0, v2, a1
+	sf.vc.ivw 0x3, v0, v2, 15
+	sf.vc.fvw 0x1, v0, v2, fa1
+	sf.vc.v.x 0x3, 0xf, v0, a1
+	sf.vc.v.i 0x3, 0xf, v0, 15
+	sf.vc.v.vv 0x3, v0, v2, v1
+	sf.vc.v.xv 0x3, v0, v2, a1
+	sf.vc.v.iv 0x3, v0, v2, 15
+	sf.vc.v.fv 0x1, v0, v2, fa1
+	sf.vc.v.vvv 0x3, v0, v2, v1
+	sf.vc.v.xvv 0x3, v0, v2, a1
+	sf.vc.v.ivv 0x3, v0, v2, 15
+	sf.vc.v.fvv 0x1, v0, v2, fa1
+	sf.vc.v.vvw 0x3, v0, v2, v1
+	sf.vc.v.xvw 0x3, v0, v2, a1
+	sf.vc.v.ivw 0x3, v0, v2, 15
+	sf.vc.v.fvw 0x1, v0, v2, fa1
+	.option pop
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1e417217b7d..09be27fb7dd 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2974,6 +2974,63 @@
 #define MASK_VT_MASKC 0xfe00707f
 #define MATCH_VT_MASKCN 0x707b
 #define MASK_VT_MASKCN 0xfe00707f
+/* Sifive vector coprocessor interface instruction.  */
+#define MATCH_SF_VC_X 0x0200405b
+#define MASK_SF_VC_X 0xf200707f
+#define MATCH_SF_VC_V_X 0x0000405b
+#define MASK_SF_VC_V_X 0xf200707f
+#define MATCH_SF_VC_I 0x0200305b
+#define MASK_SF_VC_I 0xf200707f
+#define MATCH_SF_VC_V_I 0x0000305b
+#define MASK_SF_VC_V_I 0xf200707f
+#define MATCH_SF_VC_VV 0x2200005b
+#define MASK_SF_VC_VV 0xf200707f
+#define MATCH_SF_VC_V_VV 0x2000005b
+#define MASK_SF_VC_V_VV 0xf200707f
+#define MATCH_SF_VC_XV 0x2200405b
+#define MASK_SF_VC_XV 0xf200707f
+#define MATCH_SF_VC_V_XV 0x2000405b
+#define MASK_SF_VC_V_XV 0xf200707f
+#define MATCH_SF_VC_IV 0x2200305b
+#define MASK_SF_VC_IV 0xf200707f
+#define MATCH_SF_VC_V_IV 0x2000305b
+#define MASK_SF_VC_V_IV 0xf200707f
+#define MATCH_SF_VC_FV 0x2a00505b
+#define MASK_SF_VC_FV 0xfa00707f
+#define MATCH_SF_VC_V_FV 0x2800505b
+#define MASK_SF_VC_V_FV 0xfa00707f
+#define MATCH_SF_VC_VVV 0xa200005b
+#define MASK_SF_VC_VVV 0xf200707f
+#define MATCH_SF_VC_V_VVV 0xa000005b
+#define MASK_SF_VC_V_VVV 0xf200707f
+#define MATCH_SF_VC_XVV 0xa200405b
+#define MASK_SF_VC_XVV 0xf200707f
+#define MATCH_SF_VC_V_XVV 0xa000405b
+#define MASK_SF_VC_V_XVV 0xf200707f
+#define MATCH_SF_VC_IVV 0xa200305b
+#define MASK_SF_VC_IVV 0xf200707f
+#define MATCH_SF_VC_V_IVV 0xa000305b
+#define MASK_SF_VC_V_IVV 0xf200707f
+#define MATCH_SF_VC_FVV 0xaa00505b
+#define MASK_SF_VC_FVV 0xfa00707f
+#define MATCH_SF_VC_V_FVV 0xa800505b
+#define MASK_SF_VC_V_FVV 0xfa00707f
+#define MATCH_SF_VC_VVW 0xf200005b
+#define MASK_SF_VC_VVW 0xf200707f
+#define MATCH_SF_VC_V_VVW 0xf000005b
+#define MASK_SF_VC_V_VVW 0xf200707f
+#define MATCH_SF_VC_XVW 0xf200405b
+#define MASK_SF_VC_XVW 0xf200707f
+#define MATCH_SF_VC_V_XVW 0xf000405b
+#define MASK_SF_VC_V_XVW 0xf200707f
+#define MATCH_SF_VC_IVW 0xf200305b
+#define MASK_SF_VC_IVW 0xf200707f
+#define MATCH_SF_VC_V_IVW 0xf000305b
+#define MASK_SF_VC_V_IVW 0xf200707f
+#define MATCH_SF_VC_FVW 0xfa00505b
+#define MASK_SF_VC_FVW 0xfa00707f
+#define MATCH_SF_VC_V_FVW 0xf800505b
+#define MASK_SF_VC_V_FVW 0xfa00707f
 /* Unprivileged Counter/Timers CSR addresses.  */
 #define CSR_CYCLE 0xc00
 #define CSR_TIME 0xc01
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 3099c9e256c..7cb270d4ac0 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -331,6 +331,12 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define NVECR 32
 #define NVECM 1
 
+/* SiFive fields.  */
+#define OP_MASK_XSO2            0x3
+#define OP_SH_XSO2              26
+#define OP_MASK_XSO1            0x1
+#define OP_SH_XSO1              26
+
 /* ABI names for selected x-registers.  */
 
 #define X_RA 1
@@ -470,6 +476,7 @@ enum riscv_insn_class
   INSN_CLASS_XTHEADVECTOR,
   INSN_CLASS_XTHEADZVAMO,
   INSN_CLASS_XVENTANACONDOPS,
+  INSN_CLASS_XSFVCP,
 };
 
 /* This structure holds information for a particular instruction.  */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 2d7c154cc3d..79131f452ea 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -702,11 +702,36 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		    goto undefined_modifier;
 		}
 	      break;
+	    case 's': /* SiFive vector coprocessor interface */
+	      switch (*++oparg)
+		{
+		case 'd':
+		  print (info->stream, dis_style_register, "0x%x",
+			 (unsigned) EXTRACT_OPERAND (RD, l));
+		  break;
+		case 't':
+		  print (info->stream, dis_style_register, "0x%x",
+			 (unsigned) EXTRACT_OPERAND (RS2, l));
+		  break;
+		case 'O':
+		  switch (*++oparg)
+		    {
+		    case '2':
+		      print (info->stream, dis_style_register, "0x%x",
+			     (unsigned) EXTRACT_OPERAND (XSO2, l));
+		      break;
+		    case '1':
+		      print (info->stream, dis_style_register, "0x%x",
+			     (unsigned) EXTRACT_OPERAND (XSO1, l));
+		      break;
+		    }
+		  break;
+		}
+	      break;
 	    default:
 	      goto undefined_modifier;
 	    }
 	  break;
-
 	default:
 	undefined_modifier:
 	  /* xgettext:c-format */
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index fcba49972f0..f05f5d1d279 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2899,6 +2899,36 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
 {"vt.maskcn",  64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKCN, MASK_VT_MASKCN, match_opcode, 0 },
 
+/* Sifive vector coprocessor interface instruction.  */
+{"sf.vc.x",     0, INSN_CLASS_XSFVCP, "XsO2,Xst,Xsd,s",  MATCH_SF_VC_X, MASK_SF_VC_X, match_opcode, 0 },
+{"sf.vc.v.x",   0, INSN_CLASS_XSFVCP, "XsO2,Xst,Vd,s",  MATCH_SF_VC_V_X, MASK_SF_VC_V_X, match_opcode, 0 },
+{"sf.vc.i",     0, INSN_CLASS_XSFVCP, "XsO2,Xst,Xsd,Vi", MATCH_SF_VC_I, MASK_SF_VC_I, match_opcode, 0 },
+{"sf.vc.v.i",   0, INSN_CLASS_XSFVCP, "XsO2,Xst,Vd,Vi", MATCH_SF_VC_V_I, MASK_SF_VC_V_I, match_opcode, 0 },
+{"sf.vc.vv",    0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,Vs", MATCH_SF_VC_VV, MASK_SF_VC_VV, match_opcode, 0 },
+{"sf.vc.v.vv",  0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VV, MASK_SF_VC_V_VV, match_opcode, 0 },
+{"sf.vc.xv",    0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,s",  MATCH_SF_VC_XV, MASK_SF_VC_XV, match_opcode, 0 },
+{"sf.vc.v.xv",  0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_V_XV, MASK_SF_VC_V_XV, match_opcode, 0 },
+{"sf.vc.iv",    0, INSN_CLASS_XSFVCP, "XsO2,Xsd,Vt,Vi", MATCH_SF_VC_IV, MASK_SF_VC_IV, match_opcode, 0 },
+{"sf.vc.v.iv",  0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IV, MASK_SF_VC_V_IV, match_opcode, 0 },
+{"sf.vc.fv",    0, INSN_CLASS_XSFVCP, "XsO1,Xsd,Vt,S",  MATCH_SF_VC_FV, MASK_SF_VC_FV, match_opcode, 0 },
+{"sf.vc.v.fv",  0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FV, MASK_SF_VC_V_FV, match_opcode, 0 },
+{"sf.vc.vvv",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_VVV, MASK_SF_VC_VVV, match_opcode, 0 },
+{"sf.vc.v.vvv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VVV, MASK_SF_VC_V_VVV, match_opcode, 0 },
+{"sf.vc.xvv",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_XVV, MASK_SF_VC_XVV, match_opcode, 0 },
+{"sf.vc.v.xvv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_V_XVV, MASK_SF_VC_V_XVV, match_opcode, 0 },
+{"sf.vc.ivv",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_IVV, MASK_SF_VC_IVV, match_opcode, 0 },
+{"sf.vc.v.ivv", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IVV, MASK_SF_VC_V_IVV, match_opcode, 0 },
+{"sf.vc.fvv",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVV, MASK_SF_VC_FVV, match_opcode, 0 },
+{"sf.vc.v.fvv", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVV, MASK_SF_VC_V_FVV, match_opcode, 0 },
+{"sf.vc.vvw",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_VVW, MASK_SF_VC_VVW, match_opcode, 0 },
+{"sf.vc.v.vvw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vs", MATCH_SF_VC_V_VVW, MASK_SF_VC_V_VVW, match_opcode, 0 },
+{"sf.vc.xvw",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_XVW, MASK_SF_VC_XVW, match_opcode, 0 },
+{"sf.vc.v.xvw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,s",  MATCH_SF_VC_V_XVW, MASK_SF_VC_V_XVW, match_opcode, 0 },
+{"sf.vc.ivw",   0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_IVW, MASK_SF_VC_IVW, match_opcode, 0 },
+{"sf.vc.v.ivw", 0, INSN_CLASS_XSFVCP, "XsO2,Vd,Vt,Vi", MATCH_SF_VC_V_IVW, MASK_SF_VC_V_IVW, match_opcode, 0 },
+{"sf.vc.fvw",   0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_FVW, MASK_SF_VC_FVW, match_opcode, 0 },
+{"sf.vc.v.fvw", 0, INSN_CLASS_XSFVCP, "XsO1,Vd,Vt,S",  MATCH_SF_VC_V_FVW, MASK_SF_VC_V_FVW, match_opcode, 0 },
+
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
 };
