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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id n16-20020ac85a10000000b004181a080726si1059719qta.659.2023.11.16.22.21.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Nov 2023 22:21:18 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E0DCD3858415 for ; Fri, 17 Nov 2023 06:21:17 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-131.freemail.mail.aliyun.com (out30-131.freemail.mail.aliyun.com [115.124.30.131]) by sourceware.org (Postfix) with ESMTPS id DEE4C3858D20 for ; Fri, 17 Nov 2023 06:21:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org DEE4C3858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org DEE4C3858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.131 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700202073; cv=none; b=ex6fYNkpxyriNK1cpjpNiSyoSzvoM7BlA5dMk8DasSl4FkZHKW70LIJKSDtQHy4UI7AWPaiPaQ5mfwZ8bLWLtO5poB7FFGcJCCmrtJYUl4nRAc+DCMQeP6VsfYXhBLMVY2cNGaHRzgGo0eowzclernOO0yY0zdKmKhcq25AwZ5o= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700202073; c=relaxed/simple; bh=GiELJbNdtPEbHXkemaLCMUYyIo+gENQFfVBuIthbuNA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=NVE5gxGYHk7/GzGheDs+1JJw7ALPKhunQBGS897wAlvUdfSe5znLXnsn1S2zDwCh6LBI+Tmv7A/4PunepuIIcWcV80oU9LgOdPz/cmSiJnQq47W/TQBBW5mISUuWvjrsW6H+w6/gZT0Jx8rnu3uoPTsN911eMhVyD4bJui2lpgc= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R161e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046050; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0VwYf5Lo_1700202064; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0VwYf5Lo_1700202064) by smtp.aliyun-inc.com; Fri, 17 Nov 2023 14:21:06 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension. Date: Fri, 17 Nov 2023 14:20:53 +0800 Message-Id: <20231117062053.1873-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-20.4 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782791094383568948 X-GMAIL-MSGID: 1782791094383568948 The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the XTheadFmv extension in T-Head specific is incorrect, and it also has some impact on the implementation of the binutils, so this patch corrects this. For details see: https://github.com/T-head-Semi/thead-extension-spec/pull/34 gas/ChangeLog: * testsuite/gas/riscv/x-thead-fmv.d: Correct test. * testsuite/gas/riscv/x-thead-fmv.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding. (MASK_TH_FMV_HW_X): Likewise. (MATCH_TH_FMV_X_HW): Likewise. (MASK_TH_FMV_X_HW): Likewise. opcodes/ChangeLog: * riscv-opc.c: Correct operands. Reviewed-by: Christoph Muellner Tested-by: Christoph Muellner --- gas/testsuite/gas/riscv/x-thead-fmv.d | 4 ++-- gas/testsuite/gas/riscv/x-thead-fmv.s | 2 +- include/opcode/riscv-opc.h | 8 ++++---- opcodes/riscv-opc.c | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) base-commit: 0da4f405f8d9d15b9381075debce788251e31815 diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d index af8ce0c8ee0..50ccc62413f 100644 --- a/gas/testsuite/gas/riscv/x-thead-fmv.d +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d @@ -7,5 +7,5 @@ Disassembly of section .text: 0+000 : -[ ]+[0-9a-f]+:[ ]+5005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 -[ ]+[0-9a-f]+:[ ]+6005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 +[ ]+[0-9a-f]+:[ ]+a005158b[ ]+th.fmv.hw.x[ ]+fa1,a0 +[ ]+[0-9a-f]+:[ ]+c005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s index 250ba8358ae..8ca2ec2f093 100644 --- a/gas/testsuite/gas/riscv/x-thead-fmv.s +++ b/gas/testsuite/gas/riscv/x-thead-fmv.s @@ -1,3 +1,3 @@ target: - th.fmv.hw.x a0, fa1 + th.fmv.hw.x fa1, a0 th.fmv.x.hw a1, fa0 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 24217062edc..061e35d8603 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2515,10 +2515,10 @@ #define MATCH_TH_FSURW 0x5000700b #define MASK_TH_FSURW 0xf800707f /* Vendor-specific (T-Head) XTheadFmv instructions. */ -#define MATCH_TH_FMV_HW_X 0x5000100b -#define MASK_TH_FMV_HW_X 0xfff0707f -#define MATCH_TH_FMV_X_HW 0x6000100b -#define MASK_TH_FMV_X_HW 0xfff0707f +#define MATCH_TH_FMV_X_HW 0xc000100b +#define MASK_TH_FMV_X_HW 0xfff0707f +#define MATCH_TH_FMV_HW_X 0xa000100b +#define MASK_TH_FMV_HW_X 0xfff0707f /* Vendor-specific (T-Head) XTheadInt instructions. */ #define MATCH_TH_IPOP 0x0050000b #define MASK_TH_IPOP 0xffffffff diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 72d727cd77e..3a4ab62d274 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2157,7 +2157,7 @@ const struct riscv_opcode riscv_opcodes[] = {"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xtu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadFmv instructions. */ -{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, +{"th.fmv.hw.x", 32, INSN_CLASS_XTHEADFMV, "D,s", MATCH_TH_FMV_HW_X, MASK_TH_FMV_HW_X, match_opcode, 0}, {"th.fmv.x.hw", 32, INSN_CLASS_XTHEADFMV, "d,S", MATCH_TH_FMV_X_HW, MASK_TH_FMV_X_HW, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadInt instructions. */