diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d
index 09e4a9c2f73..50061606298 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.d
+++ b/gas/testsuite/gas/riscv/x-thead-vector.d
@@ -720,3 +720,35 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+88891257[ 	]+th.vfncvt.f.xu.v[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+88899257[ 	]+th.vfncvt.f.x.v[ 	]+v4,v8,v0.t
 [ 	]+[0-9a-f]+:[ 	]+888a1257[ 	]+th.vfncvt.f.f.v[ 	]+v4,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+02862257[ 	]+th.vredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+1a842257[ 	]+th.vredmaxu.vs[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+1e842257[ 	]+th.vredmax.vs[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+12842257[ 	]+th.vredminu.vs[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+16842257[ 	]+th.vredmin.vs[ 	]+v4,v8,v8
+[ 	]+[0-9a-f]+:[ 	]+06862257[ 	]+th.vredand.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0a862257[ 	]+th.vredor.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0e862257[ 	]+th.vredxor.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+00862257[ 	]+th.vredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+18842257[ 	]+th.vredmaxu.vs[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+1c842257[ 	]+th.vredmax.vs[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+10842257[ 	]+th.vredminu.vs[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+14842257[ 	]+th.vredmin.vs[ 	]+v4,v8,v8,v0.t
+[ 	]+[0-9a-f]+:[ 	]+04862257[ 	]+th.vredand.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+08862257[ 	]+th.vredor.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0c862257[ 	]+th.vredxor.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c2860257[ 	]+th.vwredsumu.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c6860257[ 	]+th.vwredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c0860257[ 	]+th.vwredsumu.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c4860257[ 	]+th.vwredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+0e861257[ 	]+th.vfredosum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+06861257[ 	]+th.vfredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+1e861257[ 	]+th.vfredmax.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+16861257[ 	]+th.vfredmin.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+0c861257[ 	]+th.vfredosum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+04861257[ 	]+th.vfredsum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+1c861257[ 	]+th.vfredmax.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+14861257[ 	]+th.vfredmin.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+ce861257[ 	]+th.vfwredosum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+c6861257[ 	]+th.vfwredsum.vs[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+cc861257[ 	]+th.vfwredosum.vs[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+c4861257[ 	]+th.vfwredsum.vs[ 	]+v4,v8,v12,v0.t
diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s
index f7de24fdd63..eb1eccc5abc 100644
--- a/gas/testsuite/gas/riscv/x-thead-vector.s
+++ b/gas/testsuite/gas/riscv/x-thead-vector.s
@@ -752,3 +752,39 @@
 	th.vfncvt.f.xu.v v4, v8, v0.t
 	th.vfncvt.f.x.v v4, v8, v0.t
 	th.vfncvt.f.f.v v4, v8, v0.t
+
+	th.vredsum.vs v4, v8, v12
+	th.vredmaxu.vs v4, v8, v8
+	th.vredmax.vs v4, v8, v8
+	th.vredminu.vs v4, v8, v8
+	th.vredmin.vs v4, v8, v8
+	th.vredand.vs v4, v8, v12
+	th.vredor.vs v4, v8, v12
+	th.vredxor.vs v4, v8, v12
+	th.vredsum.vs v4, v8, v12, v0.t
+	th.vredmaxu.vs v4, v8, v8, v0.t
+	th.vredmax.vs v4, v8, v8, v0.t
+	th.vredminu.vs v4, v8, v8, v0.t
+	th.vredmin.vs v4, v8, v8, v0.t
+	th.vredand.vs v4, v8, v12, v0.t
+	th.vredor.vs v4, v8, v12, v0.t
+	th.vredxor.vs v4, v8, v12, v0.t
+
+	th.vwredsumu.vs v4, v8, v12
+	th.vwredsum.vs v4, v8, v12
+	th.vwredsumu.vs v4, v8, v12, v0.t
+	th.vwredsum.vs v4, v8, v12, v0.t
+
+	th.vfredosum.vs v4, v8, v12
+	th.vfredsum.vs v4, v8, v12
+	th.vfredmax.vs v4, v8, v12
+	th.vfredmin.vs v4, v8, v12
+	th.vfredosum.vs v4, v8, v12, v0.t
+	th.vfredsum.vs v4, v8, v12, v0.t
+	th.vfredmax.vs v4, v8, v12, v0.t
+	th.vfredmin.vs v4, v8, v12, v0.t
+
+	th.vfwredosum.vs v4, v8, v12
+	th.vfwredsum.vs v4, v8, v12
+	th.vfwredosum.vs v4, v8, v12, v0.t
+	th.vfwredsum.vs v4, v8, v12, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 2ec07a0b2a5..233172d7c5f 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -3839,6 +3839,38 @@
 #define MASK_TH_VFNCVTFXV    0xfc0ff07f
 #define MATCH_TH_VFNCVTFFV   0x880a1057
 #define MASK_TH_VFNCVTFFV    0xfc0ff07f
+#define MATCH_TH_VREDSUMVV  0x00002057
+#define MASK_TH_VREDSUMVV   0xfc00707f
+#define MATCH_TH_VREDMAXVV  0x1c002057
+#define MASK_TH_VREDMAXVV   0xfc00707f
+#define MATCH_TH_VREDMAXUVV 0x18002057
+#define MASK_TH_VREDMAXUVV  0xfc00707f
+#define MATCH_TH_VREDMINVV  0x14002057
+#define MASK_TH_VREDMINVV   0xfc00707f
+#define MATCH_TH_VREDMINUVV 0x10002057
+#define MASK_TH_VREDMINUVV  0xfc00707f
+#define MATCH_TH_VREDANDVV  0x04002057
+#define MASK_TH_VREDANDVV   0xfc00707f
+#define MATCH_TH_VREDORVV   0x08002057
+#define MASK_TH_VREDORVV    0xfc00707f
+#define MATCH_TH_VREDXORVV  0x0c002057
+#define MASK_TH_VREDXORVV   0xfc00707f
+#define MATCH_TH_VWREDSUMUVV 0xc0000057
+#define MASK_TH_VWREDSUMUVV  0xfc00707f
+#define MATCH_TH_VWREDSUMVV  0xc4000057
+#define MASK_TH_VWREDSUMVV   0xfc00707f
+#define MATCH_TH_VFREDOSUMV 0x0c001057
+#define MASK_TH_VFREDOSUMV  0xfc00707f
+#define MATCH_TH_VFREDSUMV  0x04001057
+#define MASK_TH_VFREDSUMV   0xfc00707f
+#define MATCH_TH_VFREDMAXV  0x1c001057
+#define MASK_TH_VFREDMAXV   0xfc00707f
+#define MATCH_TH_VFREDMINV  0x14001057
+#define MASK_TH_VFREDMINV   0xfc00707f
+#define MATCH_TH_VFWREDOSUMV 0xcc001057
+#define MASK_TH_VFWREDOSUMV  0xfc00707f
+#define MATCH_TH_VFWREDSUMV  0xc4001057
+#define MASK_TH_VFWREDSUMV   0xfc00707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index a556f44d99d..39be63f2ee6 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2844,6 +2844,22 @@ const struct riscv_opcode riscv_opcodes[] =
 {"th.vfncvt.f.xu.v",0,INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXUV, MASK_TH_VFNCVTFXUV, match_opcode, 0},
 {"th.vfncvt.f.x.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFXV, MASK_TH_VFNCVTFXV, match_opcode, 0},
 {"th.vfncvt.f.f.v",0, INSN_CLASS_XTHEADVECTOR, "Vd,VtVm", MATCH_TH_VFNCVTFFV, MASK_TH_VFNCVTFFV, match_opcode, 0},
+{"th.vredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDSUMVV, MASK_TH_VREDSUMVV, match_opcode, 0},
+{"th.vredmaxu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDMAXUVV, MASK_TH_VREDMAXUVV, match_opcode, 0},
+{"th.vredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDMAXVV, MASK_TH_VREDMAXVV, match_opcode, 0},
+{"th.vredminu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDMINUVV, MASK_TH_VREDMINUVV, match_opcode, 0},
+{"th.vredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDMINVV, MASK_TH_VREDMINVV, match_opcode, 0},
+{"th.vredand.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDANDVV, MASK_TH_VREDANDVV, match_opcode, 0},
+{"th.vredor.vs",  0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDORVV, MASK_TH_VREDORVV, match_opcode, 0},
+{"th.vredxor.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VREDXORVV, MASK_TH_VREDXORVV, match_opcode, 0},
+{"th.vwredsumu.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWREDSUMUVV, MASK_TH_VWREDSUMUVV, match_opcode, 0},
+{"th.vwredsum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VWREDSUMVV, MASK_TH_VWREDSUMVV, match_opcode, 0},
+{"th.vfredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDOSUMV, MASK_TH_VFREDOSUMV, match_opcode, 0},
+{"th.vfredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDSUMV, MASK_TH_VFREDSUMV, match_opcode, 0},
+{"th.vfredmax.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDMAXV, MASK_TH_VFREDMAXV, match_opcode, 0},
+{"th.vfredmin.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFREDMINV, MASK_TH_VFREDMINV, match_opcode, 0},
+{"th.vfwredosum.vs",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWREDOSUMV, MASK_TH_VFWREDOSUMV, match_opcode, 0},
+{"th.vfwredsum.vs", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VFWREDSUMV, MASK_TH_VFWREDSUMV, match_opcode, 0},
 
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 {"vt.maskc",   64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },
