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[8.43.85.97]) by mx.google.com with ESMTPS id k20-20020a05620a0b9400b0076edc6ca0afsi3992810qkh.172.2023.11.09.23.32.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 23:32:20 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4EEFF3858281 for ; Fri, 10 Nov 2023 07:32:20 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) by sourceware.org (Postfix) with ESMTPS id 33A063856DE6 for ; Fri, 10 Nov 2023 07:32:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 33A063856DE6 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 33A063856DE6 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.97 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601536; cv=none; b=GTHtCOx7lycVRXx4/D0GM0znjPZo8Jbre7Pp2ADQcZprs2XO+lvhfIF+wM9bEVRuXNhJhRZ6+slRud+/IyklS9kCmcOp/hVDO6zpu5feklTaRIhA7cbk4/13kmq0GmYTjg0tXZuFgsdavE7+bN8DhDXLizznfLQ7dXWzpYQU6ms= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699601536; c=relaxed/simple; bh=UOfMBuJwOI3TN67wkdBzPMMM+cGEqVDLLYw/6bE39aM=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=W7IRfJfhUT79se8aW/0diaAGTOkvYM2HiOEZH0oH6ddMSleq3HgL+Fd4G5TbkRojCrMAgfdlQbJEwYu2jvRM2y/OOyapaCBWDX1ETmzGHFehqB/4eMBS1Q1769wBxl9OBjXRnMTbAc17QqVHae2ZY3dTE+CGiAfdeuxJp2t6oF8= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R211e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3dMcS_1699601526; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3dMcS_1699601526) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:32:07 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 08/12] RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension Date: Fri, 10 Nov 2023 15:31:56 +0800 Message-Id: <20231110073156.1961-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20231110071759.1640-1-jinma@linux.alibaba.com> References: <20231110071759.1640-1-jinma@linux.alibaba.com> MIME-Version: 1.0 X-Spam-Status: No, score=-20.4 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782161384820259854 X-GMAIL-MSGID: 1782161384820259854 T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds fixed-point arithmetic instructions for the "XTheadVector" extension. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for fixed-point arithmetic instructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv-opc.h (MATCH_TH_VSADDUVV): New. opcodes/ChangeLog: * riscv-opc.c: Likewise. --- gas/testsuite/gas/riscv/x-thead-vector.d | 86 ++++++++++++++++++++++ gas/testsuite/gas/riscv/x-thead-vector.s | 92 ++++++++++++++++++++++++ include/opcode/riscv-opc.h | 72 +++++++++++++++++++ opcodes/riscv-opc.c | 36 ++++++++++ 4 files changed, 286 insertions(+) diff --git a/gas/testsuite/gas/riscv/x-thead-vector.d b/gas/testsuite/gas/riscv/x-thead-vector.d index e3a1579300b..9a199177f37 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.d +++ b/gas/testsuite/gas/riscv/x-thead-vector.d @@ -464,3 +464,89 @@ Disassembly of section .text: [ ]+[0-9a-f]+:[ ]+5e05c457[ ]+th.vmv.v.x[ ]+v8,a1 [ ]+[0-9a-f]+:[ ]+5e07b457[ ]+th.vmv.v.i[ ]+v8,15 [ ]+[0-9a-f]+:[ ]+5e083457[ ]+th.vmv.v.i[ ]+v8,-16 +[ ]+[0-9a-f]+:[ ]+82860257[ ]+th.vsaddu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8285c257[ ]+th.vsaddu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+8287b257[ ]+th.vsaddu.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+82883257[ ]+th.vsaddu.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+80860257[ ]+th.vsaddu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8085c257[ ]+th.vsaddu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+8087b257[ ]+th.vsaddu.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+80883257[ ]+th.vsaddu.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+86860257[ ]+th.vsadd.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8685c257[ ]+th.vsadd.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+8687b257[ ]+th.vsadd.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+86883257[ ]+th.vsadd.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+84860257[ ]+th.vsadd.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8485c257[ ]+th.vsadd.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+8487b257[ ]+th.vsadd.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+84883257[ ]+th.vsadd.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+8a860257[ ]+th.vssubu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8a85c257[ ]+th.vssubu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+88860257[ ]+th.vssubu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8885c257[ ]+th.vssubu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+8e860257[ ]+th.vssub.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+8e85c257[ ]+th.vssub.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+8c860257[ ]+th.vssub.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+8c85c257[ ]+th.vssub.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+92860257[ ]+th.vaadd.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9285c257[ ]+th.vaadd.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+9287b257[ ]+th.vaadd.vi[ ]+v4,v8,15 +[ ]+[0-9a-f]+:[ ]+92883257[ ]+th.vaadd.vi[ ]+v4,v8,-16 +[ ]+[0-9a-f]+:[ ]+90860257[ ]+th.vaadd.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9085c257[ ]+th.vaadd.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+9087b257[ ]+th.vaadd.vi[ ]+v4,v8,15,v0.t +[ ]+[0-9a-f]+:[ ]+90883257[ ]+th.vaadd.vi[ ]+v4,v8,-16,v0.t +[ ]+[0-9a-f]+:[ ]+9a860257[ ]+th.vasub.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9a85c257[ ]+th.vasub.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+98860257[ ]+th.vasub.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9885c257[ ]+th.vasub.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+9e860257[ ]+th.vsmul.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+9e85c257[ ]+th.vsmul.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+9c860257[ ]+th.vsmul.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+9c85c257[ ]+th.vsmul.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+f2860257[ ]+th.vwsmaccu.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+f285c257[ ]+th.vwsmaccu.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+f6860257[ ]+th.vwsmacc.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+f685c257[ ]+th.vwsmacc.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+fa860257[ ]+th.vwsmaccsu.vv[ ]+v4,v12,v8 +[ ]+[0-9a-f]+:[ ]+fa85c257[ ]+th.vwsmaccsu.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+fe85c257[ ]+th.vwsmaccus.vx[ ]+v4,a1,v8 +[ ]+[0-9a-f]+:[ ]+f0860257[ ]+th.vwsmaccu.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f085c257[ ]+th.vwsmaccu.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f4860257[ ]+th.vwsmacc.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f485c257[ ]+th.vwsmacc.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f8860257[ ]+th.vwsmaccsu.vv[ ]+v4,v12,v8,v0.t +[ ]+[0-9a-f]+:[ ]+f885c257[ ]+th.vwsmaccsu.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+fc85c257[ ]+th.vwsmaccus.vx[ ]+v4,a1,v8,v0.t +[ ]+[0-9a-f]+:[ ]+aa860257[ ]+th.vssrl.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+aa85c257[ ]+th.vssrl.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+aa80b257[ ]+th.vssrl.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+aa8fb257[ ]+th.vssrl.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+a8860257[ ]+th.vssrl.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+a885c257[ ]+th.vssrl.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+a880b257[ ]+th.vssrl.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+a88fb257[ ]+th.vssrl.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+ae860257[ ]+th.vssra.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ae85c257[ ]+th.vssra.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+ae80b257[ ]+th.vssra.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+ae8fb257[ ]+th.vssra.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+ac860257[ ]+th.vssra.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+ac85c257[ ]+th.vssra.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+ac80b257[ ]+th.vssra.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+ac8fb257[ ]+th.vssra.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+ba860257[ ]+th.vnclipu.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+ba85c257[ ]+th.vnclipu.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+ba80b257[ ]+th.vnclipu.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+ba8fb257[ ]+th.vnclipu.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+b8860257[ ]+th.vnclipu.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+b885c257[ ]+th.vnclipu.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+b880b257[ ]+th.vnclipu.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+b88fb257[ ]+th.vnclipu.vi[ ]+v4,v8,31,v0.t +[ ]+[0-9a-f]+:[ ]+be860257[ ]+th.vnclip.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+be85c257[ ]+th.vnclip.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+be80b257[ ]+th.vnclip.vi[ ]+v4,v8,1 +[ ]+[0-9a-f]+:[ ]+be8fb257[ ]+th.vnclip.vi[ ]+v4,v8,31 +[ ]+[0-9a-f]+:[ ]+bc860257[ ]+th.vnclip.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+bc85c257[ ]+th.vnclip.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+bc80b257[ ]+th.vnclip.vi[ ]+v4,v8,1,v0.t +[ ]+[0-9a-f]+:[ ]+bc8fb257[ ]+th.vnclip.vi[ ]+v4,v8,31,v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s index 55887e0ce41..b2fbb0c343f 100644 --- a/gas/testsuite/gas/riscv/x-thead-vector.s +++ b/gas/testsuite/gas/riscv/x-thead-vector.s @@ -472,3 +472,95 @@ th.vmv.v.x v8, a1 th.vmv.v.i v8, 15 th.vmv.v.i v8, -16 + + th.vsaddu.vv v4, v8, v12 + th.vsaddu.vx v4, v8, a1 + th.vsaddu.vi v4, v8, 15 + th.vsaddu.vi v4, v8, -16 + th.vsaddu.vv v4, v8, v12, v0.t + th.vsaddu.vx v4, v8, a1, v0.t + th.vsaddu.vi v4, v8, 15, v0.t + th.vsaddu.vi v4, v8, -16, v0.t + th.vsadd.vv v4, v8, v12 + th.vsadd.vx v4, v8, a1 + th.vsadd.vi v4, v8, 15 + th.vsadd.vi v4, v8, -16 + th.vsadd.vv v4, v8, v12, v0.t + th.vsadd.vx v4, v8, a1, v0.t + th.vsadd.vi v4, v8, 15, v0.t + th.vsadd.vi v4, v8, -16, v0.t + th.vssubu.vv v4, v8, v12 + th.vssubu.vx v4, v8, a1 + th.vssubu.vv v4, v8, v12, v0.t + th.vssubu.vx v4, v8, a1, v0.t + th.vssub.vv v4, v8, v12 + th.vssub.vx v4, v8, a1 + th.vssub.vv v4, v8, v12, v0.t + th.vssub.vx v4, v8, a1, v0.t + + th.vaadd.vv v4, v8, v12 + th.vaadd.vx v4, v8, a1 + th.vaadd.vi v4, v8, 15 + th.vaadd.vi v4, v8, -16 + th.vaadd.vv v4, v8, v12, v0.t + th.vaadd.vx v4, v8, a1, v0.t + th.vaadd.vi v4, v8, 15, v0.t + th.vaadd.vi v4, v8, -16, v0.t + th.vasub.vv v4, v8, v12 + th.vasub.vx v4, v8, a1 + th.vasub.vv v4, v8, v12, v0.t + th.vasub.vx v4, v8, a1, v0.t + + th.vsmul.vv v4, v8, v12 + th.vsmul.vx v4, v8, a1 + th.vsmul.vv v4, v8, v12, v0.t + th.vsmul.vx v4, v8, a1, v0.t + + th.vwsmaccu.vv v4, v12, v8 + th.vwsmaccu.vx v4, a1, v8 + th.vwsmacc.vv v4, v12, v8 + th.vwsmacc.vx v4, a1, v8 + th.vwsmaccsu.vv v4, v12, v8 + th.vwsmaccsu.vx v4, a1, v8 + th.vwsmaccus.vx v4, a1, v8 + th.vwsmaccu.vv v4, v12, v8, v0.t + th.vwsmaccu.vx v4, a1, v8, v0.t + th.vwsmacc.vv v4, v12, v8, v0.t + th.vwsmacc.vx v4, a1, v8, v0.t + th.vwsmaccsu.vv v4, v12, v8, v0.t + th.vwsmaccsu.vx v4, a1, v8, v0.t + th.vwsmaccus.vx v4, a1, v8, v0.t + + th.vssrl.vv v4, v8, v12 + th.vssrl.vx v4, v8, a1 + th.vssrl.vi v4, v8, 1 + th.vssrl.vi v4, v8, 31 + th.vssrl.vv v4, v8, v12, v0.t + th.vssrl.vx v4, v8, a1, v0.t + th.vssrl.vi v4, v8, 1, v0.t + th.vssrl.vi v4, v8, 31, v0.t + th.vssra.vv v4, v8, v12 + th.vssra.vx v4, v8, a1 + th.vssra.vi v4, v8, 1 + th.vssra.vi v4, v8, 31 + th.vssra.vv v4, v8, v12, v0.t + th.vssra.vx v4, v8, a1, v0.t + th.vssra.vi v4, v8, 1, v0.t + th.vssra.vi v4, v8, 31, v0.t + + th.vnclipu.vv v4, v8, v12 + th.vnclipu.vx v4, v8, a1 + th.vnclipu.vi v4, v8, 1 + th.vnclipu.vi v4, v8, 31 + th.vnclipu.vv v4, v8, v12, v0.t + th.vnclipu.vx v4, v8, a1, v0.t + th.vnclipu.vi v4, v8, 1, v0.t + th.vnclipu.vi v4, v8, 31, v0.t + th.vnclip.vv v4, v8, v12 + th.vnclip.vx v4, v8, a1 + th.vnclip.vi v4, v8, 1 + th.vnclip.vi v4, v8, 31 + th.vnclip.vv v4, v8, v12, v0.t + th.vnclip.vx v4, v8, a1, v0.t + th.vnclip.vi v4, v8, 1, v0.t + th.vnclip.vi v4, v8, 31, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 553f3142ed8..059b2fa68bb 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -3599,6 +3599,78 @@ #define MASK_TH_VMVVX 0xfff0707f #define MATCH_TH_VMVVI 0x5e003057 #define MASK_TH_VMVVI 0xfff0707f +#define MATCH_TH_VSADDUVV 0x80000057 +#define MASK_TH_VSADDUVV 0xfc00707f +#define MATCH_TH_VSADDUVX 0x80004057 +#define MASK_TH_VSADDUVX 0xfc00707f +#define MATCH_TH_VSADDUVI 0x80003057 +#define MASK_TH_VSADDUVI 0xfc00707f +#define MATCH_TH_VSADDVV 0x84000057 +#define MASK_TH_VSADDVV 0xfc00707f +#define MATCH_TH_VSADDVX 0x84004057 +#define MASK_TH_VSADDVX 0xfc00707f +#define MATCH_TH_VSADDVI 0x84003057 +#define MASK_TH_VSADDVI 0xfc00707f +#define MATCH_TH_VSSUBUVV 0x88000057 +#define MASK_TH_VSSUBUVV 0xfc00707f +#define MATCH_TH_VSSUBUVX 0x88004057 +#define MASK_TH_VSSUBUVX 0xfc00707f +#define MATCH_TH_VSSUBVV 0x8c000057 +#define MASK_TH_VSSUBVV 0xfc00707f +#define MATCH_TH_VSSUBVX 0x8c004057 +#define MASK_TH_VSSUBVX 0xfc00707f +#define MATCH_TH_VAADDVV 0x90000057 +#define MASK_TH_VAADDVV 0xfc00707f +#define MATCH_TH_VAADDVX 0x90004057 +#define MASK_TH_VAADDVX 0xfc00707f +#define MATCH_TH_VAADDVI 0x90003057 +#define MASK_TH_VAADDVI 0xfc00707f +#define MATCH_TH_VASUBVV 0x98000057 +#define MASK_TH_VASUBVV 0xfc00707f +#define MATCH_TH_VASUBVX 0x98004057 +#define MASK_TH_VASUBVX 0xfc00707f +#define MATCH_TH_VSMULVV 0x9c000057 +#define MASK_TH_VSMULVV 0xfc00707f +#define MATCH_TH_VSMULVX 0x9c004057 +#define MASK_TH_VSMULVX 0xfc00707f +#define MATCH_TH_VWSMACCUVV 0xf0000057 +#define MASK_TH_VWSMACCUVV 0xfc00707f +#define MATCH_TH_VWSMACCUVX 0xf0004057 +#define MASK_TH_VWSMACCUVX 0xfc00707f +#define MATCH_TH_VWSMACCVV 0xf4000057 +#define MASK_TH_VWSMACCVV 0xfc00707f +#define MATCH_TH_VWSMACCVX 0xf4004057 +#define MASK_TH_VWSMACCVX 0xfc00707f +#define MATCH_TH_VWSMACCSUVV 0xf8000057 +#define MASK_TH_VWSMACCSUVV 0xfc00707f +#define MATCH_TH_VWSMACCSUVX 0xf8004057 +#define MASK_TH_VWSMACCSUVX 0xfc00707f +#define MATCH_TH_VWSMACCUSVX 0xfc004057 +#define MASK_TH_VWSMACCUSVX 0xfc00707f +#define MATCH_TH_VSSRLVV 0xa8000057 +#define MASK_TH_VSSRLVV 0xfc00707f +#define MATCH_TH_VSSRLVX 0xa8004057 +#define MASK_TH_VSSRLVX 0xfc00707f +#define MATCH_TH_VSSRLVI 0xa8003057 +#define MASK_TH_VSSRLVI 0xfc00707f +#define MATCH_TH_VSSRAVV 0xac000057 +#define MASK_TH_VSSRAVV 0xfc00707f +#define MATCH_TH_VSSRAVX 0xac004057 +#define MASK_TH_VSSRAVX 0xfc00707f +#define MATCH_TH_VSSRAVI 0xac003057 +#define MASK_TH_VSSRAVI 0xfc00707f +#define MATCH_TH_VNCLIPUVV 0xb8000057 +#define MASK_TH_VNCLIPUVV 0xfc00707f +#define MATCH_TH_VNCLIPUVX 0xb8004057 +#define MASK_TH_VNCLIPUVX 0xfc00707f +#define MATCH_TH_VNCLIPUVI 0xb8003057 +#define MASK_TH_VNCLIPUVI 0xfc00707f +#define MATCH_TH_VNCLIPVV 0xbc000057 +#define MASK_TH_VNCLIPVV 0xfc00707f +#define MATCH_TH_VNCLIPVX 0xbc004057 +#define MASK_TH_VNCLIPVX 0xfc00707f +#define MATCH_TH_VNCLIPVI 0xbc003057 +#define MASK_TH_VNCLIPVI 0xfc00707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bd7b866358f..c7d6d171902 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2722,6 +2722,42 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vmv.v.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs", MATCH_TH_VMVVV, MASK_TH_VMVVV, match_opcode, 0 }, {"th.vmv.v.x", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s", MATCH_TH_VMVVX, MASK_TH_VMVVX, match_opcode, 0 }, {"th.vmv.v.i", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vi", MATCH_TH_VMVVI, MASK_TH_VMVVI, match_opcode, 0 }, +{"th.vsaddu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSADDUVV, MASK_TH_VSADDUVV, match_opcode, 0 }, +{"th.vsaddu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSADDUVX, MASK_TH_VSADDUVX, match_opcode, 0 }, +{"th.vsaddu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VSADDUVI, MASK_TH_VSADDUVI, match_opcode, 0 }, +{"th.vsadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSADDVV, MASK_TH_VSADDVV, match_opcode, 0 }, +{"th.vsadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSADDVX, MASK_TH_VSADDVX, match_opcode, 0 }, +{"th.vsadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VSADDVI, MASK_TH_VSADDVI, match_opcode, 0 }, +{"th.vssubu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSSUBUVV, MASK_TH_VSSUBUVV, match_opcode, 0 }, +{"th.vssubu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSSUBUVX, MASK_TH_VSSUBUVX, match_opcode, 0 }, +{"th.vssub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSSUBVV, MASK_TH_VSSUBVV, match_opcode, 0 }, +{"th.vssub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSSUBVX, MASK_TH_VSSUBVX, match_opcode, 0 }, +{"th.vaadd.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VAADDVV, MASK_TH_VAADDVV, match_opcode, 0 }, +{"th.vaadd.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VAADDVX, MASK_TH_VAADDVX, match_opcode, 0 }, +{"th.vaadd.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,ViVm", MATCH_TH_VAADDVI, MASK_TH_VAADDVI, match_opcode, 0 }, +{"th.vasub.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VASUBVV, MASK_TH_VASUBVV, match_opcode, 0 }, +{"th.vasub.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VASUBVX, MASK_TH_VASUBVX, match_opcode, 0 }, +{"th.vsmul.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSMULVV, MASK_TH_VSMULVV, match_opcode, 0 }, +{"th.vsmul.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSMULVX, MASK_TH_VSMULVX, match_opcode, 0 }, +{"th.vwsmaccu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWSMACCUVV, MASK_TH_VWSMACCUVV, match_opcode, 0 }, +{"th.vwsmaccu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWSMACCUVX, MASK_TH_VWSMACCUVX, match_opcode, 0 }, +{"th.vwsmacc.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWSMACCVV, MASK_TH_VWSMACCVV, match_opcode, 0 }, +{"th.vwsmacc.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWSMACCVX, MASK_TH_VWSMACCVX, match_opcode, 0 }, +{"th.vwsmaccsu.vv",0, INSN_CLASS_XTHEADVECTOR, "Vd,Vs,VtVm", MATCH_TH_VWSMACCSUVV, MASK_TH_VWSMACCSUVV, match_opcode, 0 }, +{"th.vwsmaccsu.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWSMACCSUVX, MASK_TH_VWSMACCSUVX, match_opcode, 0 }, +{"th.vwsmaccus.vx",0, INSN_CLASS_XTHEADVECTOR, "Vd,s,VtVm", MATCH_TH_VWSMACCUSVX, MASK_TH_VWSMACCUSVX, match_opcode, 0 }, +{"th.vssrl.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSSRLVV, MASK_TH_VSSRLVV, match_opcode, 0 }, +{"th.vssrl.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSSRLVX, MASK_TH_VSSRLVX, match_opcode, 0 }, +{"th.vssrl.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSSRLVI, MASK_TH_VSSRLVI, match_opcode, 0 }, +{"th.vssra.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VSSRAVV, MASK_TH_VSSRAVV, match_opcode, 0 }, +{"th.vssra.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VSSRAVX, MASK_TH_VSSRAVX, match_opcode, 0 }, +{"th.vssra.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VSSRAVI, MASK_TH_VSSRAVI, match_opcode, 0 }, +{"th.vnclipu.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNCLIPUVV, MASK_TH_VNCLIPUVV, match_opcode, 0 }, +{"th.vnclipu.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNCLIPUVX, MASK_TH_VNCLIPUVX, match_opcode, 0 }, +{"th.vnclipu.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNCLIPUVI, MASK_TH_VNCLIPUVI, match_opcode, 0 }, +{"th.vnclip.vv", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VsVm", MATCH_TH_VNCLIPVV, MASK_TH_VNCLIPVV, match_opcode, 0 }, +{"th.vnclip.vx", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,sVm", MATCH_TH_VNCLIPVX, MASK_TH_VNCLIPVX, match_opcode, 0 }, +{"th.vnclip.vi", 0, INSN_CLASS_XTHEADVECTOR, "Vd,Vt,VjVm", MATCH_TH_VNCLIPVI, MASK_TH_VNCLIPVI, match_opcode, 0 }, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 },