diff mbox series

[02/12] RISC-V: Add CSRs for T-Head VECTOR vendor extension

Message ID 20231110072015.1684-1-jinma@linux.alibaba.com
State Unresolved
Headers
Series [01/12] RISC-V: Add T-Head VECTOR vendor extension. |

Checks

Context Check Description
snail/binutils-gdb-check warning Git am fail log

Commit Message

Jin Ma Nov. 10, 2023, 7:20 a.m. UTC 
  T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the CSRs for XTheadVector. Because of the
conflict between encoding and teh 'V' extension, it is implemented
by alias. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add the class for
	the CSRs of the "XTheadVector" extension.
	(riscv_csr_address): Likewise.
	* testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test.
	* testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test.
	* testsuite/gas/riscv/x-thead-vector-csr.d: New test.
	* testsuite/gas/riscv/x-thead-vector-csr.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
---
 gas/config/tc-riscv.c                         |  4 ++++
 .../gas/riscv/x-thead-vector-csr-warn.d       |  3 +++
 .../gas/riscv/x-thead-vector-csr-warn.l       | 16 ++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector-csr.d  | 21 +++++++++++++++++++
 gas/testsuite/gas/riscv/x-thead-vector-csr.s  | 13 ++++++++++++
 include/opcode/riscv-opc.h                    |  7 +++++++
 opcodes/riscv-dis.c                           | 14 +++++++++++--
 7 files changed, 76 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.d
 create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-csr.s
diff mbox series

Patch

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 402c46ad753..af9a34a2185 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -91,6 +91,7 @@  enum riscv_csr_class
   CSR_CLASS_SSTC_AND_H,		/* Sstc only (with H) */
   CSR_CLASS_SSTC_32,		/* Sstc RV32 only */
   CSR_CLASS_SSTC_AND_H_32,	/* Sstc RV32 only (with H) */
+  CSR_CLASS_XTHEADVECTOR,	/* xtheadvector only */
 };
 
 /* This structure holds all restricted conditions for a CSR.  */
@@ -1104,6 +1105,9 @@  riscv_csr_address (const char *csr_name,
       break;
     case CSR_CLASS_DEBUG:
       break;
+    case CSR_CLASS_XTHEADVECTOR:
+      extension = "xtheadvector";
+      break;
     default:
       as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class);
     }
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
new file mode 100644
index 00000000000..17c707ddc7e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv64gc -mcsr-check
+#source: x-thead-vector-csr.s
+#warning_output: x-thead-vector-csr-warn.l
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
new file mode 100644
index 00000000000..4dd867ce2ee
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-csr-warn.l
@@ -0,0 +1,16 @@ 
+.*Assembler messages:
+.*Warning: invalid CSR `th.vstart', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vxsat', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vxrm', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vl', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vtype', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vlenb', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vstart', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vxsat', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vxrm', needs `xtheadvector' extension
+.*Warning: invalid CSR `th.vl', needs `xtheadvector' extension
+.*Warning: read-only CSR is written `csrw th.vl,a0'
+.*Warning: invalid CSR `th.vtype', needs `xtheadvector' extension
+.*Warning: read-only CSR is written `csrw th.vtype,a0'
+.*Warning: invalid CSR `th.vlenb', needs `xtheadvector' extension
+.*Warning: read-only CSR is written `csrw th.vlenb,a0'
\ No newline at end of file
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr.d b/gas/testsuite/gas/riscv/x-thead-vector-csr.d
new file mode 100644
index 00000000000..75357b204cc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-csr.d
@@ -0,0 +1,21 @@ 
+#as: -march=rv32if_xtheadvector
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+00802573[ 	]+csrr[ 	]+a0,th.vstart
+[ 	]+[0-9a-f]+:[ 	]+00902573[ 	]+csrr[ 	]+a0,th.vxsat
+[ 	]+[0-9a-f]+:[ 	]+00a02573[ 	]+csrr[ 	]+a0,th.vxrm
+[ 	]+[0-9a-f]+:[ 	]+c2002573[ 	]+csrr[ 	]+a0,th.vl
+[ 	]+[0-9a-f]+:[ 	]+c2102573[ 	]+csrr[ 	]+a0,th.vtype
+[ 	]+[0-9a-f]+:[ 	]+c2202573[ 	]+csrr[ 	]+a0,th.vlenb
+[ 	]+[0-9a-f]+:[ 	]+00851073[ 	]+csrw[ 	]+th.vstart,a0
+[ 	]+[0-9a-f]+:[ 	]+00951073[ 	]+csrw[ 	]+th.vxsat,a0
+[ 	]+[0-9a-f]+:[ 	]+00a51073[ 	]+csrw[ 	]+th.vxrm,a0
+[ 	]+[0-9a-f]+:[ 	]+c2051073[ 	]+csrw[ 	]+th.vl,a0
+[ 	]+[0-9a-f]+:[ 	]+c2151073[ 	]+csrw[ 	]+th.vtype,a0
+[ 	]+[0-9a-f]+:[ 	]+c2251073[ 	]+csrw[ 	]+th.vlenb,a0
diff --git a/gas/testsuite/gas/riscv/x-thead-vector-csr.s b/gas/testsuite/gas/riscv/x-thead-vector-csr.s
new file mode 100644
index 00000000000..e11f87f1a07
--- /dev/null
+++ b/gas/testsuite/gas/riscv/x-thead-vector-csr.s
@@ -0,0 +1,13 @@ 
+	csrr a0, th.vstart
+	csrr a0, th.vxsat
+	csrr a0, th.vxrm
+	csrr a0, th.vl
+	csrr a0, th.vtype
+	csrr a0, th.vlenb
+
+	csrw th.vstart, a0
+	csrw th.vxsat, a0
+	csrw th.vxrm, a0
+	csrw th.vl, a0		# read-only CSR
+	csrw th.vtype, a0	# read-only CSR
+	csrw th.vlenb, a0	# read-only CSR
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 24217062edc..ed29384e825 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -4121,4 +4121,11 @@  DECLARE_CSR_ALIAS(etrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, P
 DECLARE_CSR_ALIAS(tmexttrigger, CSR_TDATA1, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR_ALIAS(textra32, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR_ALIAS(textra64, CSR_TDATA3, CSR_CLASS_DEBUG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Unprivileged T-Head Vector CSRs.  */
+DECLARE_CSR_ALIAS(th.vstart, CSR_VSTART, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vxsat, CSR_VXSAT, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vxrm, CSR_VXRM, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vl, CSR_VL, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vtype, CSR_VTYPE, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR_ALIAS(th.vlenb, CSR_VLENB, CSR_CLASS_XTHEADVECTOR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 #endif /* DECLARE_CSR_ALIAS */
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ca328b4c997..2d7c154cc3d 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -568,8 +568,18 @@  print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	      }
 
 	    if (riscv_csr_hash[csr] != NULL)
-	      print (info->stream, dis_style_register, "%s",
-		     riscv_csr_hash[csr]);
+	      if (riscv_subset_supports (&riscv_rps_dis, "xtheadvector")
+		  && (csr == CSR_VSTART
+		      || csr == CSR_VXSAT
+		      || csr == CSR_VXRM
+		      || csr == CSR_VL
+		      || csr == CSR_VTYPE
+		      || csr == CSR_VLENB))
+		print (info->stream, dis_style_register, "%s",
+		       concat ("th.", riscv_csr_hash[csr], NULL));
+	      else
+		print (info->stream, dis_style_register, "%s",
+		       riscv_csr_hash[csr]);
 	    else
 	      print (info->stream, dis_style_immediate, "0x%x", csr);
 	    break;