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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id z5-20020a0cfec5000000b006716a905fccsi4060890qvs.69.2023.11.09.23.18.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 23:18:36 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BA3883858421 for ; Fri, 10 Nov 2023 07:18:36 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from out30-97.freemail.mail.aliyun.com (out30-97.freemail.mail.aliyun.com [115.124.30.97]) by sourceware.org (Postfix) with ESMTPS id 5362B3858D38 for ; Fri, 10 Nov 2023 07:18:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5362B3858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 5362B3858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.97 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699600713; cv=none; b=t4mAw+KH4UEqDDED8Gmdzr1cdz80DecfMxFl8kBNY5r2LkNFFXWkCZiYOZ3Zo/2FQ8IyjN5HPj86hkfZ/UC1+wlrvdug+zExqit4nFAgutfj4DcXl1M2VUL5iROgwO9rqN4egDkxh9PDrE1SR509v5DGlfMNYz9HYp4tYG+VDto= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699600713; c=relaxed/simple; bh=ix6vcjlhc1gVq3c6iBZy0Gvnz2wsnCIV9QSaxofIaxY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=JQdhbY9Ku9C8mVcpYK9RzlsaFxpUzQrzRg+EvYwifxHFlLFNdHmHgZSH1sLKeTHmXoUkKVtdXzWWyPpGokkqCRl7bqsH1E6545fd8YvDDfucT5dUKQ/trRNY1/twM3KbwtFCSiP/vJUGDCkcjcy5R6QtRNAfYVoees9qta/7YpM= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R171e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045176; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=6; SR=0; TI=SMTPD_---0Vw3j9Ew_1699600692; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3j9Ew_1699600692) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:18:13 +0800 From: Jin Ma To: binutils@sourceware.org, nelson@rivosinc.com Cc: christoph.muellner@vrull.eu, lifang_xia@linux.alibaba.com, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH 01/12] RISC-V: Add T-Head VECTOR vendor extension. Date: Fri, 10 Nov 2023 15:17:59 +0800 Message-Id: <20231110071759.1640-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-20.3 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782160521618476348 X-GMAIL-MSGID: 1782160521618476348 T-Head has a range of vendor-specific instructions. Therefore it makes sense to group them into smaller chunks in form of vendor extensions. This patch adds the "XTheadVector" extension, a collection of T-Head-specific vector instructions. The 'th' prefix and the "XTheadVector" extension are documented in a PR for the RISC-V toolchain conventions ([1]). Here are some things that need to be explained: The "XTheadVector" extension is not a custom-extension, but a non-standard non-conforming extension. The encoding space of the "TheadVector" instructions overlaps with those of the 'V' extension. This encoding space conflict is not on purpose, but the result of issues in the past that have been resolved since. Therefore, the "XTheadVector" extension and the 'V' extension are in conflict. [1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 Co-developed-by: Lifang Xia Co-developed-by: Christoph Müllner bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): The "XTheadVector" extension and the 'V' extension are in conflict. (riscv_multi_subset_supports): Likewise.. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * doc/c-riscv.texi: * testsuite/gas/riscv/x-thead-vector-fail.d: New test. * testsuite/gas/riscv/x-thead-vector-fail.l: New test. * testsuite/gas/riscv/x-thead-vector.s: New test. include/ChangeLog: * opcode/riscv.h (enum riscv_insn_class): --- bfd/elfxx-riscv.c | 12 ++++++++++++ gas/NEWS | 3 +++ gas/doc/c-riscv.texi | 5 +++++ gas/testsuite/gas/riscv/x-thead-vector-fail.d | 3 +++ gas/testsuite/gas/riscv/x-thead-vector-fail.l | 2 ++ gas/testsuite/gas/riscv/x-thead-vector.s | 0 include/opcode/riscv.h | 1 + 7 files changed, 26 insertions(+) create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.d create mode 100644 gas/testsuite/gas/riscv/x-thead-vector-fail.l create mode 100644 gas/testsuite/gas/riscv/x-thead-vector.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index c9acf124626..e2c3ffe4b4f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1373,6 +1373,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmemidx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -1984,6 +1985,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) (_("`zfinx' is conflict with the `f/d/q/zfh/zfhmin' extension")); no_conflict = false; } + if (riscv_lookup_subset (rps->subset_list, "xtheadvector", &subset) + && riscv_lookup_subset (rps->subset_list, "v", &subset)) + { + rps->error_handler + (_("`xtheadvector' is conflict with the `v' extension")); + no_conflict = false; + } bool support_zve = false; bool support_zvl = false; @@ -2580,6 +2588,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadmempair"); case INSN_CLASS_XTHEADSYNC: return riscv_subset_supports (rps, "xtheadsync"); + case INSN_CLASS_XTHEADVECTOR: + return riscv_subset_supports (rps, "xtheadvector"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); default: @@ -2824,6 +2834,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadmempair"; case INSN_CLASS_XTHEADSYNC: return "xtheadsync"; + case INSN_CLASS_XTHEADVECTOR: + return "xtheadvector"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/NEWS b/gas/NEWS index ddf48fca37b..aae0c6b71c0 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -28,6 +28,9 @@ * Add support for Cortex-X4 for AArch64. +* Add support for various T-Head extensions (XTheadVector, XTheadZvlsseg + and XTheadZvamo) from version 2.3.0 of the T-Head ISA manual. + Changes in 2.41: * Add support for the KVX instruction set. diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index b23504648bd..a7c9420bd86 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -814,6 +814,11 @@ The XTheadSync extension provides instructions for multi-processor synchronizati It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadVector +The XTheadVector extension provides instructions for thead vector. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. + @item XVentanaCondOps XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional diff --git a/gas/testsuite/gas/riscv/x-thead-vector-fail.d b/gas/testsuite/gas/riscv/x-thead-vector-fail.d new file mode 100644 index 00000000000..ac99c3f5398 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64gcv_xtheadvector +#source: x-thead-vector.s +#error_output: x-thead-vector-fail.l diff --git a/gas/testsuite/gas/riscv/x-thead-vector-fail.l b/gas/testsuite/gas/riscv/x-thead-vector-fail.l new file mode 100644 index 00000000000..7dd88e317ce --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-fail.l @@ -0,0 +1,2 @@ +Assembler messages: +Error: `xtheadvector' is conflict with the `v' extension \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/x-thead-vector.s b/gas/testsuite/gas/riscv/x-thead-vector.s new file mode 100644 index 00000000000..e69de29bb2d diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 710a9b73189..a26ef8abf12 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -467,6 +467,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, + INSN_CLASS_XTHEADVECTOR, INSN_CLASS_XVENTANACONDOPS, };