diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 25271e0f12e..827e0436136 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10268,6 +10268,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sha2",		AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
   {"sb",		AARCH64_FEATURE (SB), AARCH64_NO_FEATURES},
   {"predres",		AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES},
+  {"predres2",		AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)},
   {"aes",		AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)},
   {"sm4",		AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)},
   {"sha3",		AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index d19bc3b0030..0624c4f0bb8 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -265,6 +265,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Guarded Control Stack Extension.
 @item @code{rasv2} @tab ARMv8.8-A @tab ARMv9.3-A or later
  @tab Enable the Reliability, Availability and Serviceability extension v2.
+@item @code{predres2} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
+ @tab Enable Prediction instructions.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/illegal-predres2-1.d b/gas/testsuite/gas/aarch64/illegal-predres2-1.d
new file mode 100644
index 00000000000..f858afd34c9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-predres2-1.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: predres2.s
+#error_output: illegal-predres2-1.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/illegal-predres2-1.l b/gas/testsuite/gas/aarch64/illegal-predres2-1.l
new file mode 100644
index 00000000000..15f568030be
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-predres2-1.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cosp rctx,x1'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cfp rctx,x1'
diff --git a/gas/testsuite/gas/aarch64/predres2.d b/gas/testsuite/gas/aarch64/predres2.d
new file mode 100644
index 00000000000..cc5ea087f26
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres2.d
@@ -0,0 +1,10 @@
+#as: -march=armv8-a+predres2
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b73c1 	cosp	rctx, x1
+.*:	d50b7381 	cfp	rctx, x1
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/predres2.s b/gas/testsuite/gas/aarch64/predres2.s
new file mode 100644
index 00000000000..3f6f88cace3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres2.s
@@ -0,0 +1,4 @@
+/* File to test the +predres2 option.  */
+func:
+	cosp rctx, x1
+	cfp rctx, x1
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index bb180d30ef9..ae6457597e5 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -171,6 +171,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SME2,
   /* ARMv8.9-A RAS Extensions.  */
   AARCH64_FEATURE_RASv2,
+  /* Speculation Prediction Restriction instructions.  */
+  AARCH64_FEATURE_PREDRES2,
   DUMMY1,
   DUMMY2,
   DUMMY3,
@@ -241,7 +243,8 @@ enum aarch64_feature_bit {
 #define AARCH64_ARCH_V9_1A_FEATURES(X)	AARCH64_ARCH_V8_6A_FEATURES (X)
 #define AARCH64_ARCH_V9_2A_FEATURES(X)	AARCH64_ARCH_V8_7A_FEATURES (X)
 #define AARCH64_ARCH_V9_3A_FEATURES(X)	AARCH64_ARCH_V8_8A_FEATURES (X)
-#define AARCH64_ARCH_V9_4A_FEATURES(X)	AARCH64_ARCH_V8_9A_FEATURES (X)
+#define AARCH64_ARCH_V9_4A_FEATURES(X)	(AARCH64_ARCH_V8_9A_FEATURES (X) \
+					 | AARCH64_FEATBIT (X, PREDRES2))
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8A(X)	(AARCH64_FEATBIT (X, V8) \
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 850f4c2d2af..e07836cd668 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2516,6 +2516,8 @@ static const aarch64_feature_set aarch64_feature_sb =
   AARCH64_FEATURE (SB);
 static const aarch64_feature_set aarch64_feature_predres =
   AARCH64_FEATURE (PREDRES);
+static const aarch64_feature_set aarch64_feature_predres2 =
+  AARCH64_FEATURES (2, PREDRES, PREDRES2);
 static const aarch64_feature_set aarch64_feature_memtag =
   AARCH64_FEATURE (MEMTAG);
 static const aarch64_feature_set aarch64_feature_bfloat16 =
@@ -2609,6 +2611,7 @@ static const aarch64_feature_set aarch64_feature_rasv2 =
 #define FRINTTS		&aarch64_feature_frintts
 #define SB		&aarch64_feature_sb
 #define PREDRES		&aarch64_feature_predres
+#define PREDRES2	&aarch64_feature_predres2
 #define MEMTAG		&aarch64_feature_memtag
 #define TME		&aarch64_feature_tme
 #define SVE2		&aarch64_feature_sve2
@@ -2842,6 +2845,9 @@ static const aarch64_feature_set aarch64_feature_rasv2 =
   MOPS_SET_OP1_OP2_INSN (NAME, "n", OPCODE | 0x2000, MASK, ISA), \
   MOPS_SET_OP1_OP2_INSN (NAME, "tn", OPCODE | 0x3000, MASK, ISA)
 
+#define PREDRES2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, PREDRES2, OPS, QUALS, FLAGS, 0, 0, NULL }
+
 const struct aarch64_opcode aarch64_opcode_table[] =
 {
   /* Add/subtract (with carry).  */
@@ -4173,6 +4179,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
+  PREDRES2_INSN ("cosp", 0xd50b73c0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
   /* Armv8.4-a flag setting instruction, However this encoding has an encoding clash with the msr
      below it.  Usually we can resolve this by setting an alias condition on the flags, however that
      depends on the disassembly masks to be able to quickly find the alias.  The problem is the
