diff mbox series

[2/2] aarch64: Add 128-bit system register flags

Message ID 20231103235317.2080506-2-victor.donascimento@arm.com
State Unresolved
Headers
Series [1/2] aarch64: Add THE system register support |

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Context Check Description
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Commit Message

Victor Do Nascimento Nov. 3, 2023, 11:53 p.m. UTC 
  In preparation for the implementation of 128-bit system register
support across the toolchain, this patch adds the feature flag
F_REG_128 and adds it to relevant system registers in
`aarch64-sys-regs.def'.

Given the shared nature of this file, this change is made necessary
initially to implement argument validation in the `__arm_rsr128' and
`__armwsr128' ACLE intrinsics in GCC, but will be of subsequent use in
the binutils implementation of the corresponding `mrrs' and `msrr'
instructions.

Regression tested on aarch64-linux-gnu, no regressions.

opcodes/ChangeLog:

	* aarch64-opc.h (F_REG_128):  New flag.
	* aarch64-sys-regs.def (par_el1): Add F_REG_128 flag.
	(rcwmask_el1): Likewise.
	(rcwsmask_el1): Likewise.
	(ttbr0_el1): Likewise.
	(ttbr0_el12): Likewise.
	(ttbr0_el2): Likewise.
	(ttbr1_el1): Likewise.
	(ttbr1_el12): Likewise.
	(ttbr1_el2): Likewise.
	(vttbr_el2): Likewise.
---
 opcodes/aarch64-opc.h        |  3 +++
 opcodes/aarch64-sys-regs.def | 20 ++++++++++----------
 2 files changed, 13 insertions(+), 10 deletions(-)

Comments

Nick Clifton Nov. 7, 2023, 11:02 a.m. UTC | #1 
Hi Victor,

> In preparation for the implementation of 128-bit system register
> support across the toolchain, this patch adds the feature flag
> F_REG_128 and adds it to relevant system registers in
> `aarch64-sys-regs.def'.
> 
> Given the shared nature of this file, this change is made necessary
> initially to implement argument validation in the `__arm_rsr128' and
> `__armwsr128' ACLE intrinsics in GCC, but will be of subsequent use in
> the binutils implementation of the corresponding `mrrs' and `msrr'
> instructions.
> 
> Regression tested on aarch64-linux-gnu, no regressions.
> 
> opcodes/ChangeLog:
> 
> 	* aarch64-opc.h (F_REG_128):  New flag.
> 	* aarch64-sys-regs.def (par_el1): Add F_REG_128 flag.
> 	(rcwmask_el1): Likewise.
> 	(rcwsmask_el1): Likewise.
> 	(ttbr0_el1): Likewise.
> 	(ttbr0_el12): Likewise.
> 	(ttbr0_el2): Likewise.
> 	(ttbr1_el1): Likewise.
> 	(ttbr1_el12): Likewise.
> 	(ttbr1_el2): Likewise.
> 	(vttbr_el2): Likewise.

Approved - please apply.

Cheers
   Nick
diff mbox series

Patch

diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index fe1f882c20e..75d2feb02ea 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -295,6 +295,9 @@  verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 #undef F_REG_ALIAS
 #define F_REG_ALIAS	(1 << 6)  /* Register name aliases another.  */
 
+#undef F_REG_128
+#define F_REG_128	(1 << 7) /* System regsister implementable as 128-bit wide.  */
+
 /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
    Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
    In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index dc43126088f..96bdadb0b0f 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -594,7 +594,7 @@ 
   SYSREG ("oslar_el1",		CPENC (2,0,1,0,4),	F_REG_WRITE,		AARCH64_NO_FEATURES)
   SYSREG ("oslsr_el1",		CPENC (2,0,1,1,4),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("pan",		CPENC (3,0,4,2,3),	F_ARCHEXT,		AARCH64_FEATURE (PAN))
-  SYSREG ("par_el1",		CPENC (3,0,7,4,0),	0,			AARCH64_NO_FEATURES)
+  SYSREG ("par_el1",		CPENC (3,0,7,4,0),	F_REG_128,		AARCH64_NO_FEATURES)
   SYSREG ("pmbidr_el1",		CPENC (3,0,9,10,7),	F_REG_READ|F_ARCHEXT,	AARCH64_FEATURE (PROFILE))
   SYSREG ("pmblimitr_el1",	CPENC (3,0,9,10,0),	F_ARCHEXT,		AARCH64_FEATURE (PROFILE))
   SYSREG ("pmbptr_el1",		CPENC (3,0,9,10,1),	F_ARCHEXT,		AARCH64_FEATURE (PROFILE))
@@ -756,8 +756,8 @@ 
   SYSREG ("prlar_el2",		CPENC (3,4,6,8,1),	F_ARCHEXT,		AARCH64_FEATURE (V8R))
   SYSREG ("prselr_el1",		CPENC (3,0,6,2,1),	F_ARCHEXT,		AARCH64_FEATURE (V8R))
   SYSREG ("prselr_el2",		CPENC (3,4,6,2,1),	F_ARCHEXT,		AARCH64_FEATURE (V8R))
-  SYSREG ("rcwmask_el1",	CPENC (3,0,13,0,6),	F_ARCHEXT,		AARCH64_FEATURE (THE))
-  SYSREG ("rcwsmask_el1",	CPENC (3,0,13,0,3),	F_ARCHEXT,		AARCH64_FEATURE (THE))
+  SYSREG ("rcwmask_el1",	CPENC (3,0,13,0,6),	F_ARCHEXT|F_REG_128,	AARCH64_FEATURE (THE))
+  SYSREG ("rcwsmask_el1",	CPENC (3,0,13,0,3),	F_ARCHEXT|F_REG_128,	AARCH64_FEATURE (THE))
   SYSREG ("revidr_el1",		CPENC (3,0,0,0,6),	F_REG_READ,		AARCH64_NO_FEATURES)
   SYSREG ("rgsr_el1",		CPENC (3,0,1,0,5),	F_ARCHEXT,		AARCH64_FEATURE (MEMTAG))
   SYSREG ("rmr_el1",		CPENC (3,0,12,0,2),	0,			AARCH64_NO_FEATURES)
@@ -1046,13 +1046,13 @@ 
   SYSREG ("trfcr_el1",		CPENC (3,0,1,2,1),	F_ARCHEXT,		AARCH64_FEATURE (V8_4A))
   SYSREG ("trfcr_el12",		CPENC (3,5,1,2,1),	F_ARCHEXT,		AARCH64_FEATURE (V8_4A))
   SYSREG ("trfcr_el2",		CPENC (3,4,1,2,1),	F_ARCHEXT,		AARCH64_FEATURE (V8_4A))
-  SYSREG ("ttbr0_el1",		CPENC (3,0,2,0,0),	0,			AARCH64_NO_FEATURES)
-  SYSREG ("ttbr0_el12",		CPENC (3,5,2,0,0),	F_ARCHEXT,		AARCH64_FEATURE (V8_1A))
-  SYSREG ("ttbr0_el2",		CPENC (3,4,2,0,0),	F_ARCHEXT,		AARCH64_FEATURE (V8A))
+  SYSREG ("ttbr0_el1",		CPENC (3,0,2,0,0),	F_REG_128,		AARCH64_NO_FEATURES)
+  SYSREG ("ttbr0_el12",		CPENC (3,5,2,0,0),	F_ARCHEXT|F_REG_128,	AARCH64_FEATURE (V8_1A))
+  SYSREG ("ttbr0_el2",		CPENC (3,4,2,0,0),	F_ARCHEXT|F_REG_128,	AARCH64_FEATURE (V8A))
   SYSREG ("ttbr0_el3",		CPENC (3,6,2,0,0),	0,			AARCH64_NO_FEATURES)
-  SYSREG ("ttbr1_el1",		CPENC (3,0,2,0,1),	0,			AARCH64_NO_FEATURES)
-  SYSREG ("ttbr1_el12",		CPENC (3,5,2,0,1),	F_ARCHEXT,		AARCH64_FEATURE (V8_1A))
-  SYSREG ("ttbr1_el2",		CPENC (3,4,2,0,1),	F_ARCHEXT,		AARCH64_FEATURES (2, V8A, V8_1A))
+  SYSREG ("ttbr1_el1",		CPENC (3,0,2,0,1),	F_REG_128,		AARCH64_NO_FEATURES)
+  SYSREG ("ttbr1_el12",		CPENC (3,5,2,0,1),	F_ARCHEXT|F_REG_128,	AARCH64_FEATURE (V8_1A))
+  SYSREG ("ttbr1_el2",		CPENC (3,4,2,0,1),	F_ARCHEXT|F_REG_128,	AARCH64_FEATURES (2, V8A, V8_1A))
   SYSREG ("uao",		CPENC (3,0,4,2,4),	F_ARCHEXT,		AARCH64_FEATURE (V8_2A))
   SYSREG ("vbar_el1",		CPENC (3,0,12,0,0),	0,			AARCH64_NO_FEATURES)
   SYSREG ("vbar_el12",		CPENC (3,5,12,0,0),	F_ARCHEXT,		AARCH64_FEATURE (V8_1A))
@@ -1069,7 +1069,7 @@ 
   SYSREG ("vstcr_el2",		CPENC (3,4,2,6,2),	F_ARCHEXT,		AARCH64_FEATURE (V8_4A))
   SYSREG ("vsttbr_el2",		CPENC (3,4,2,6,0),	F_ARCHEXT,		AARCH64_FEATURES (2, V8A, V8_4A))
   SYSREG ("vtcr_el2",		CPENC (3,4,2,1,2),	0,			AARCH64_NO_FEATURES)
-  SYSREG ("vttbr_el2",		CPENC (3,4,2,1,0),	F_ARCHEXT,		AARCH64_FEATURE (V8A))
+  SYSREG ("vttbr_el2",		CPENC (3,4,2,1,0),	F_ARCHEXT|F_REG_128,	AARCH64_FEATURE (V8A))
   SYSREG ("zcr_el1",		CPENC (3,0,1,2,0),	F_ARCHEXT,		AARCH64_FEATURE (SVE))
   SYSREG ("zcr_el12",		CPENC (3,5,1,2,0),	F_ARCHEXT,		AARCH64_FEATURE (SVE))
   SYSREG ("zcr_el2",		CPENC (3,4,1,2,0),	F_ARCHEXT,		AARCH64_FEATURE (SVE))