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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j10-20020a17090686ca00b00992aa293be8si9767279ejy.204.2023.09.19.08.26.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 08:26:04 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=MNigwqmx; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CCCDC385558F for ; Tue, 19 Sep 2023 15:25:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CCCDC385558F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695137154; bh=t0uKAbLiWrrtQV+IJoH3h8tB0/tHWHwMU39DskLmiFg=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=MNigwqmxrc20mavyqSEZ7wOC8eJxRtB04r91KPcOvlk1eg7mOzMkjm4aG55A7lDO3 PgXITqjwx9rO2rXWxBDrT1Q1PSJmScZX6YAQHuZHJIAJ94ThBvs3ZKf9aMBbFHBL8q /it/JUBfa5wM4Kno0pFegSqVUqapF2bSLTeIhgic= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id 227933858404 for ; Tue, 19 Sep 2023 15:25:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 227933858404 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="370285670" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="370285670" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 08:25:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="739758919" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="739758919" Received: from scymds03.sc.intel.com ([10.148.94.166]) by orsmga007.jf.intel.com with ESMTP; 19 Sep 2023 08:25:32 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds03.sc.intel.com (Postfix) with ESMTP id AF9596F; Tue, 19 Sep 2023 08:25:31 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com Subject: [PATCH 2/8] Support APX GPR32 with extend evex prefix Date: Tue, 19 Sep 2023 15:25:21 +0000 Message-Id: <20230919152527.497773-3-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230919152527.497773-1-lili.cui@intel.com> References: <20230919152527.497773-1-lili.cui@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Cui, Lili via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Cui, Lili" Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777480146899213570 X-GMAIL-MSGID: 1777480146899213570 EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. gas/ChangeLog: * config/tc-i386.c (is_any_apx_evex_encoding): New func. Test apx evex encoding. (build_legacy_insns_with_apx_encoding): New func. (build_evex_insns_with_extend_evex_prefix): New func. Build evex insns with gpr32 use extend evex prefix. (md_assemble): Handle apx with rex2 or evex encoding. (output_insn): Handle apx evex encoding. opcode/ChangeLog: * i386-opc.h (SPACE_EVEXMAP4): New define for legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex. * i386-gen.c (process_i386_opcode_modifier): set no_egpr for VEX instructions. * i386-tbl.h: Regenerated. * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-mod.h: Handle MOD_EVEX_MAP4_65, MOD_EVEX_MAP4_66_PREFIX_0, MOD_EVEX_MAP4_8A_W_0, MOD_EVEX_MAP4_DA_PREFIX_1, MOD_EVEX_MAP4_DB_PREFIX_1, MOD_EVEX_MAP4_DC_PREFIX_1, MOD_EVEX_MAP4_DD_PREFIX_1, MOD_EVEX_MAP4_DE_PREFIX_1, MOD_EVEX_MAP4_DF_PREFIX_1, MOD_EVEX_MAP4_F8_PREFIX_1, MOD_EVEX_MAP4_F8_PREFIX_2, MOD_EVEX_MAP4_F8_PREFIX_3, MOD_EVEX_MAP4_F9, MOD_EVEX_MAP4_8B. * i386-dis-evex-w.h: Handle EVEX_W_MAP4_8A. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_MAP4_60, PREFIX_EVEX_MAP4_61, PREFIX_EVEX_MAP4_66, PREFIX_EVEX_MAP4_8B_M_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8, PREFIX_EVEX_MAP4_FC. * i386-dis-evex-reg.h: Handle REG_EVEX_MAP4_D8_PREFIX_1, REG_EVEX_0F38F3_L_0. * i386-dis-evex-x86.h: Handle X86_64_EVEX_0F90, X86_64_EVEX_0F91, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_MAP7_F8. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32, and add vex use gpr32 promote to evex. Add EVEX_MAP7. * opcodes/i386-dis.c (REG enum): Add REG_EVEX_MAP4_D8_PREFIX_1. (MOD enum): Add MOD_EVEX_MAP4_65, MOD_EVEX_MAP4_66_PREFIX_0, MOD_EVEX_MAP4_8A_W_0, MOD_EVEX_MAP4_8B, MOD_EVEX_MAP4_DA_PREFIX_1, MOD_EVEX_MAP4_DB_PREFIX_1, MOD_EVEX_MAP4_DC_PREFIX_1, MOD_EVEX_MAP4_DD_PREFIX_1, MOD_EVEX_MAP4_DE_PREFIX_1, MOD_EVEX_MAP4_DF_PREFIX_1, MOD_EVEX_MAP4_F8_PREFIX_1, MOD_EVEX_MAP4_F8_PREFIX_2, MOD_EVEX_MAP4_F8_PREFIX_3, MOD_EVEX_MAP4_F9, REG_EVEX_0F38F3_L_0. (PREFIX enum): Add PREFIX_EVEX_MAP4_60, PREFIX_EVEX_MAP4_61, PREFIX_EVEX_MAP4_66, PREFIX_EVEX_MAP4_8B_M_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8, PREFIX_EVEX_MAP4_FC. (EVEX_LEN_enum): Add EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. (EVEX_X86_enum): Add X86_64_EVEX_0F90, X86_64_EVEX_0F91, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F3849, X86_64_EVEX_0F384B, X86_64_EVEX_0F38E0, X86_64_EVEX_0F38E1, X86_64_EVEX_0F38E2, X86_64_EVEX_0F38E3, X86_64_EVEX_0F38E4, X86_64_EVEX_0F38E5, X86_64_EVEX_0F38E6, X86_64_EVEX_0F38E7, X86_64_EVEX_0F38E8, X86_64_EVEX_0F38E9, X86_64_EVEX_0F38EA, X86_64_EVEX_0F38EB, X86_64_EVEX_0F38EC, X86_64_EVEX_0F38ED, X86_64_EVEX_0F38EE, X86_64_EVEX_0F38EF, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0. (EVEX_MAP4): New define. (EVEX_MAP7): New. (evex_type): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4, Handle EVEX_MAP7. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Ditto. --- gas/config/tc-i386.c | 93 +++- opcodes/i386-dis-evex-len.h | 10 + opcodes/i386-dis-evex-mod.h | 50 ++ opcodes/i386-dis-evex-prefix.h | 83 ++++ opcodes/i386-dis-evex-reg.h | 14 + opcodes/i386-dis-evex-x86.h | 140 ++++++ opcodes/i386-dis-evex.h | 838 ++++++++++++++++++++++++++++----- opcodes/i386-dis.c | 131 +++++- opcodes/i386-gen.c | 10 + opcodes/i386-opc.h | 2 + opcodes/i386-opc.tbl | 80 ++++ 11 files changed, 1299 insertions(+), 152 deletions(-) create mode 100644 opcodes/i386-dis-evex-x86.h diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 51486985919..48916bc3846 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1945,6 +1945,30 @@ cpu_flags_match (const insn_template *t) && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) match |= CPU_FLAGS_ARCH_MATCH; } + else if (x.bitfield.cpuapx_f) + { + if (cpu.bitfield.cpuapx_f + && (!x.bitfield.cpumovbe || cpu.bitfield.cpumovbe) + && (!x.bitfield.cpuept || cpu.bitfield.cpuept) + && (!x.bitfield.cpuinvpcid || cpu.bitfield.cpuinvpcid) + && (!x.bitfield.cpusse4_2 || cpu.bitfield.cpusse4_2) + && (!x.bitfield.cpubmi2 || cpu.bitfield.cpubmi2) + && (!x.bitfield.cpubmi || cpu.bitfield.cpubmi) + && (!x.bitfield.cpuadx || cpu.bitfield.cpuadx) + && (!x.bitfield.cpusha || cpu.bitfield.cpusha) + && (!x.bitfield.cpuavx512bw || cpu.bitfield.cpuavx512bw) + && (!x.bitfield.cpuavx512dq || cpu.bitfield.cpuavx512dq) + && (!x.bitfield.cpuavx512f || cpu.bitfield.cpuavx512f) + && (!x.bitfield.cpushstk || cpu.bitfield.cpushstk) + && (!x.bitfield.cpumovdir64b || cpu.bitfield.cpumovdir64b) + && (!x.bitfield.cpumovdiri || cpu.bitfield.cpumovdiri) + && (!x.bitfield.cpuenqcmd || cpu.bitfield.cpuenqcmd) + && (!x.bitfield.cpukl || cpu.bitfield.cpukl) + && (!x.bitfield.cpuwidekl || cpu.bitfield.cpuwidekl) + && (!x.bitfield.cpucmpccxadd || cpu.bitfield.cpucmpccxadd) + && (!x.bitfield.cpurao_int || cpu.bitfield.cpurao_int)) + match |= CPU_FLAGS_ARCH_MATCH; + } else match |= CPU_FLAGS_ARCH_MATCH; } @@ -3850,7 +3874,10 @@ is_any_vex_encoding (const insn_template *t) static INLINE bool is_any_apx_encoding (void) { - return i.rex2 || i.rex2_encoding; + return i.rex2 + || i.rex2_encoding + || (i.vex.register_specifier + && i.vex.register_specifier->reg_flags & RegRex2); } static INLINE bool @@ -3859,6 +3886,12 @@ is_any_apx_rex2_encoding (void) return (i.rex2 && i.vex.length == 2) || i.rex2_encoding; } +static INLINE bool +is_any_apx_evex_encoding (void) +{ + return i.rex2 && i.vex.length == 4; +} + static unsigned int get_broadcast_bytes (const insn_template *t, bool diag) { @@ -4129,6 +4162,50 @@ build_rex2_prefix (void) | (i.rex2 << 4) | i.rex); } +/* Build the EVEX prefix (4-byte) for evex insn + | 62h | + | `R`X`B`R' | B'mmm | + | W | v`v`v`v | `x' | pp | + | z| L'L | b | `v | aaa | +*/ +static void +build_evex_insns_with_extend_evex_prefix (void) +{ + build_evex_prefix (); + if (i.rex2 & REX_R) + i.vex.bytes[1] &= 0xef; + if (i.vex.register_specifier + && register_number (i.vex.register_specifier) > 0xf) + i.vex.bytes[3] &=0xf7; + if (i.rex2 & REX_B) + i.vex.bytes[1] |= 0x08; + if (i.rex2 & REX_X) + i.vex.bytes[2] &= 0xfb; +} + +/* Build the EVEX prefix (4-byte) for legacy insn + | 62h | + | `R`X`B`R' | B'100 | + | W | v`v`v`v | `x' | pp | + | 000 | ND | `v | NF | 00 | + For legacy insn without ndd nor nf, [vvvvv] must be all zero. */ +static void +build_legacy_insns_with_apx_encoding (void) +{ + /* map{0,1} of legacy space without ndd or nf could use rex2 prefix. */ + if (i.tm.opcode_space <= SPACE_0F + && !i.vex.register_specifier && !i.has_nf && !i.has_zero_upper) + return build_rex2_prefix (); + + if (i.prefix[DATA_PREFIX] != 0) + { + i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; + i.prefix[DATA_PREFIX] = 0; + } + + build_evex_insns_with_extend_evex_prefix (); +} + static void process_immext (void) { @@ -5544,9 +5621,10 @@ md_assemble (char *line) if (is_any_apx_encoding ()) { if (!is_any_vex_encoding (&i.tm) - && i.tm.opcode_space <= SPACE_0F - && !i.vex.register_specifier && !i.has_nf && !i.has_zero_upper) - build_rex2_prefix (); + || i.tm.opcode_space == SPACE_EVEXMAP4) + build_legacy_insns_with_apx_encoding (); + else + build_evex_insns_with_extend_evex_prefix (); /* The individual REX.RXBW bits got consumed. */ i.rex &= REX_OPCODE; @@ -5616,7 +5694,7 @@ md_assemble (char *line) && (i.rex != 0 || i.rex2!=0))) { int x; - if (!i.rex2) + if (!is_any_apx_encoding ()) i.rex |= REX_OPCODE; for (x = 0; x < 2; x++) { @@ -7935,7 +8013,8 @@ process_suffix (void) if (i.suffix != QWORD_MNEM_SUFFIX && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE && !i.tm.opcode_modifier.floatmf - && !is_any_vex_encoding (&i.tm) + && (!is_any_vex_encoding (&i.tm) + || i.tm.opcode_space == SPACE_EVEXMAP4) && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) || (flag_code == CODE_64BIT && i.tm.opcode_modifier.jump == JUMP_BYTE))) @@ -10057,7 +10136,7 @@ output_insn (void) /* Since the VEX/EVEX prefix contains the implicit prefix, we don't need the explicit prefix. */ - if (!is_any_vex_encoding (&i.tm)) + if (!is_any_vex_encoding (&i.tm) && !is_any_apx_evex_encoding ()) { switch (i.tm.opcode_modifier.opcodeprefix) { diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h index a02609c50f2..1933a045822 100644 --- a/opcodes/i386-dis-evex-len.h +++ b/opcodes/i386-dis-evex-len.h @@ -62,6 +62,16 @@ static const struct dis386 evex_len_table[][3] = { { REG_TABLE (REG_EVEX_0F38C7_L_2) }, }, + /* EVEX_LEN_0F38F2 */ + { + { "andnS", { Gdq, VexGdq, Edq }, 0 }, + }, + + /* EVEX_LEN_0F38F3 */ + { + { REG_TABLE(REG_EVEX_0F38F3_L_0) }, + }, + /* EVEX_LEN_0F3A00 */ { { Bad_Opcode }, diff --git a/opcodes/i386-dis-evex-mod.h b/opcodes/i386-dis-evex-mod.h index f9f912c5094..5a1326a1b73 100644 --- a/opcodes/i386-dis-evex-mod.h +++ b/opcodes/i386-dis-evex-mod.h @@ -1 +1,51 @@ /* Nothing at present. */ + /* MOD_EVEX_MAP4_65 */ + { + { "wrussK", { M, Gdq }, PREFIX_DATA }, + }, + /* MOD_EVEX_MAP4_66_PREFIX_0 */ + { + { "wrssK", { M, Gdq }, 0 }, + }, + /* MOD_EVEX_MAP4_DA_PREFIX_1 */ + { + { Bad_Opcode }, + { "encodekey128", { Gd, Ed }, 0 }, + }, + /* MOD_EVEX_MAP4_DB_PREFIX_1 */ + { + { Bad_Opcode }, + { "encodekey256", { Gd, Ed }, 0 }, + }, + /* MOD_EVEX_MAP4_DC_PREFIX_1 */ + { + { "aesenc128kl", { XM, M }, 0 }, + }, + /* MOD_EVEX_MAP4_DD_PREFIX_1 */ + { + { "aesdec128kl", { XM, M }, 0 }, + }, + /* MOD_EVEX_MAP4_DE_PREFIX_1 */ + { + { "aesenc256kl", { XM, M }, 0 }, + }, + /* MOD_EVEX_MAP4_DF_PREFIX_1 */ + { + { "aesdec256kl", { XM, M }, 0 }, + }, + /* MOD_EVEX_MAP4_F8_PREFIX_1 */ + { + { "enqcmds", { Gva, M }, 0 }, + }, + /* MOD_EVEX_MAP4_F8_PREFIX_2 */ + { + { "movdir64b", { Gva, M }, 0 }, + }, + /* MOD_EVEX_MAP4_F8_PREFIX_3 */ + { + { "enqcmd", { Gva, M }, 0 }, + }, + /* MOD_EVEX_MAP4_F9 */ + { + { "movdiri", { Edq, Gdq }, 0 }, + }, diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h index 28da54922c7..f6f02de6c47 100644 --- a/opcodes/i386-dis-evex-prefix.h +++ b/opcodes/i386-dis-evex-prefix.h @@ -338,6 +338,89 @@ { "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 }, { "vcmps%XH", { MaskG, VexScalar, EXw, EXxEVexS, CMP }, 0 }, }, + /* PREFIX_EVEX_MAP4_60 */ + { + { "movbeS", { Gv, Ev }, 0 }, + { Bad_Opcode }, + { "movbeS", { Gv, Ev }, 0 }, + }, + /* PREFIX_EVEX_MAP4_61 */ + { + { "movbeS", { Ev, Gv }, 0 }, + { Bad_Opcode }, + { "movbeS", { Ev, Gv }, 0 }, + }, + /* PREFIX_EVEX_MAP4_66 */ + { + { MOD_TABLE (MOD_EVEX_MAP4_66_PREFIX_0) }, + { "adoxS", { Gdq, Edq }, 0 }, + { "adcxS", { Gdq, Edq }, 0 }, + }, + /* PREFIX_EVEX_MAP4_D8 */ + { + { "sha1nexte", { XM, EXxmm }, 0 }, + { REG_TABLE (REG_EVEX_MAP4_D8_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DA */ + { + { "sha1msg2", { XM, EXxmm }, 0 }, + { MOD_TABLE (MOD_EVEX_MAP4_DA_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DB */ + { + { "sha256rnds2", { XM, EXxmm, XMM0 }, 0 }, + { MOD_TABLE (MOD_EVEX_MAP4_DB_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DC */ + { + { "sha256msg1", { XM, EXxmm }, 0 }, + { MOD_TABLE (MOD_EVEX_MAP4_DC_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DD */ + { + { "sha256msg2", { XM, EXxmm }, 0 }, + { MOD_TABLE (MOD_EVEX_MAP4_DD_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DE */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP4_DE_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_DF */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP4_DF_PREFIX_1) }, + }, + /* PREFIX_EVEX_MAP4_F0 */ + { + { "crc32A", { Gdq, Eb }, 0 }, + { "invept", { Gm, Mo }, 0 }, + }, + /* PREFIX_EVEX_MAP4_F1 */ + { + { "crc32Q", { Gdq, Ev }, 0 }, + { "invvpid", { Gm, Mo }, 0 }, + { "crc32Q", { Gdq, Ev }, 0 }, + }, + /* PREFIX_EVEX_MAP4_F2 */ + { + { Bad_Opcode }, + { "invpcid", { Gm, M }, 0 }, + }, + /* PREFIX_EVEX_MAP4_F8 */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP4_F8_PREFIX_1) }, + { MOD_TABLE (MOD_EVEX_MAP4_F8_PREFIX_2) }, + { MOD_TABLE (MOD_EVEX_MAP4_F8_PREFIX_3) }, + }, + /* PREFIX_EVEX_MAP4_FC */ + { + { "aadd", { Mdq, Gdq }, 0 }, + { "axor", { Mdq, Gdq }, 0 }, + { "aand", { Mdq, Gdq }, 0 }, + { "aor", { Mdq, Gdq }, 0 }, + }, /* PREFIX_EVEX_MAP5_10 */ { { Bad_Opcode }, diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index 2885063628b..c3b4f083346 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -49,3 +49,17 @@ { "vscatterpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA }, { "vscatterpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA }, }, + /* REG_EVEX_0F38F3_L_0 */ + { + { Bad_Opcode }, + { "blsrS", { VexGdq, Edq }, 0 }, + { "blsmskS", { VexGdq, Edq }, 0 }, + { "blsiS", { VexGdq, Edq }, 0 }, + }, + /* REG_EVEX_MAP4_D8_PREFIX_1 */ + { + { "aesencwide128kl", { M }, 0 }, + { "aesdecwide128kl", { M }, 0 }, + { "aesencwide256kl", { M }, 0 }, + { "aesdecwide256kl", { M }, 0 }, + }, diff --git a/opcodes/i386-dis-evex-x86.h b/opcodes/i386-dis-evex-x86.h new file mode 100644 index 00000000000..1121223d877 --- /dev/null +++ b/opcodes/i386-dis-evex-x86.h @@ -0,0 +1,140 @@ + /* X86_64_EVEX_0F90 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F90) }, + }, + /* X86_64_EVEX_0F91 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F91) }, + }, + /* X86_64_EVEX_0F92 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F92) }, + }, + /* X86_64_EVEX_0F93 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F93) }, + }, + /* X86_64_EVEX_0F3849 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) }, + }, + /* X86_64_EVEX_0F384B */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) }, + }, + /* X86_64_EVEX_0F38E0 */ + { + { Bad_Opcode }, + { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E1 */ + { + { Bad_Opcode }, + { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E2 */ + { + { Bad_Opcode }, + { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E3 */ + { + { Bad_Opcode }, + { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E4 */ + { + { Bad_Opcode }, + { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E5 */ + { + { Bad_Opcode }, + { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E6 */ + { + { Bad_Opcode }, + { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E7 */ + { + { Bad_Opcode }, + { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E8 */ + { + { Bad_Opcode }, + { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38E9 */ + { + { Bad_Opcode }, + { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EA */ + { + { Bad_Opcode }, + { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EB */ + { + { Bad_Opcode }, + { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EC */ + { + { Bad_Opcode }, + { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38ED */ + { + { Bad_Opcode }, + { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EE */ + { + { Bad_Opcode }, + { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38EF */ + { + { Bad_Opcode }, + { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, + }, + /* X86_64_EVEX_0F38F2 */ + { + { Bad_Opcode }, + { EVEX_LEN_TABLE (EVEX_LEN_0F38F2) }, + }, + /* X86_64_EVEX_0F38F3 */ + { + { Bad_Opcode }, + { EVEX_LEN_TABLE (EVEX_LEN_0F38F3) }, + }, + /* X86_64_EVEX_0F38F5 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38F5) }, + }, + /* X86_64_EVEX_0F38F6 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38F6) }, + }, + /* X86_64_EVEX_0F38F7 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F38F7) }, + }, + /* X86_64_EVEX_0F3AF0 */ + { + { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0F3AF0) }, + }, diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index e6295119d2b..2a8c80c5200 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -164,10 +164,10 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 90 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F90) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F91) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F92) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F93) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -375,9 +375,9 @@ static const struct dis386 evex_table[][256] = { { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, /* 48 */ { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F3849) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F384B) }, { "vrcp14p%XW", { XM, EXx }, PREFIX_DATA }, { "vrcp14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, { "vrsqrt14p%XW", { XM, EXx }, 0 }, @@ -545,32 +545,32 @@ static const struct dis386 evex_table[][256] = { { "%XEvaesdecY", { XM, Vex, EXx }, PREFIX_DATA }, { "%XEvaesdeclastY", { XM, Vex, EXx }, PREFIX_DATA }, /* E0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E0) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E1) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E2) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E3) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E4) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E5) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E6) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E7) }, /* E8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E8) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38E9) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EA) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EB) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EC) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38ED) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EE) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38EF) }, /* F0 */ { Bad_Opcode }, { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F2) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F3) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F5) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F6) }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F38F7) }, /* F8 */ { Bad_Opcode }, { Bad_Opcode }, @@ -854,7 +854,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* F0 */ - { Bad_Opcode }, + { X86_64_EVEX_FROM_VEX_TABLE (X86_64_EVEX_0F3AF0) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -872,7 +872,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, - /* EVEX_MAP5_ */ + /* EVEX_MAP4_ */ { /* 00 */ { Bad_Opcode }, @@ -893,8 +893,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { PREFIX_TABLE (PREFIX_EVEX_MAP5_10) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_11) }, + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -907,7 +907,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_1D) }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 20 */ @@ -922,12 +922,12 @@ static const struct dis386 evex_table[][256] = { /* 28 */ { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2A) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2C) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2D) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2E) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_2F) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, /* 30 */ { Bad_Opcode }, { Bad_Opcode }, @@ -966,7 +966,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, /* 50 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_51) }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -974,15 +974,6 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 58 */ - { PREFIX_TABLE (PREFIX_EVEX_MAP5_58) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_59) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5C) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5D) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5E) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_5F) }, - /* 60 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -991,6 +982,15 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 60 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP4_60) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_61) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_EVEX_MAP4_65) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_66) }, + { Bad_Opcode }, /* 68 */ { Bad_Opcode }, { Bad_Opcode }, @@ -998,7 +998,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vmovwY", { XMScalar, Edw }, PREFIX_DATA }, + { Bad_Opcode }, { Bad_Opcode }, /* 70 */ { Bad_Opcode }, @@ -1010,13 +1010,13 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 78 */ - { PREFIX_TABLE (PREFIX_EVEX_MAP5_78) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_79) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7A) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7B) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7C) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D) }, - { "vmovw", { Edw, XMScalar }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, /* 80 */ { Bad_Opcode }, @@ -1113,19 +1113,19 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "sha1rnds4", { XM, EXxmm, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* D8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_D8) }, + { "sha1msg1", { XM, EXxmm }, 0 }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DA) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DB) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DC) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DD) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DE) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_DF) }, /* E0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1145,25 +1145,25 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* F0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_F0) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_F1) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_F2) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* F8 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP4_F8) }, + { MOD_TABLE (MOD_EVEX_MAP4_F9) }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP4_FC) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, }, - /* EVEX_MAP6_ */ + /* EVEX_MAP5_ */ { /* 00 */ { Bad_Opcode }, @@ -1184,11 +1184,11 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP5_10) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_11) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_13) }, - { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1198,7 +1198,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_1D) }, { Bad_Opcode }, { Bad_Opcode }, /* 20 */ @@ -1213,12 +1213,12 @@ static const struct dis386 evex_table[][256] = { /* 28 */ { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2A) }, { Bad_Opcode }, - { Bad_Opcode }, - { "vscalefp%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vscalefs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2C) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2D) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2E) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_2F) }, /* 30 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1240,39 +1240,39 @@ static const struct dis386 evex_table[][256] = { /* 40 */ { Bad_Opcode }, { Bad_Opcode }, - { "vgetexpp%XH", { XM, EXxh, EXxEVexS }, PREFIX_DATA }, - { "vgetexps%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, PREFIX_DATA }, - { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 48 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 48 */ { Bad_Opcode }, - { "vrcpp%XH", { XM, EXxh }, PREFIX_DATA }, - { "vrcps%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA }, - { "vrsqrtp%XH", { XM, EXxh }, PREFIX_DATA }, - { "vrsqrts%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA }, - /* 50 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_56) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_57) }, - /* 58 */ { Bad_Opcode }, + /* 50 */ { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_51) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 58 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP5_58) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_59) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5A) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5B) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5C) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5D) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5E) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_5F) }, /* 60 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1289,7 +1289,7 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "vmovwY", { XMScalar, Edw }, PREFIX_DATA }, { Bad_Opcode }, /* 70 */ { Bad_Opcode }, @@ -1301,7 +1301,15 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 78 */ + { PREFIX_TABLE (PREFIX_EVEX_MAP5_78) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_79) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_7A) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_7B) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_7C) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP5_7D) }, + { "vmovw", { Edw, XMScalar }, PREFIX_DATA }, { Bad_Opcode }, + /* 80 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1309,8 +1317,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 80 */ { Bad_Opcode }, + /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1318,8 +1326,8 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 88 */ { Bad_Opcode }, + /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -1327,24 +1335,16 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 90 */ + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsubadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - /* 98 */ - { "vfmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, /* A0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1352,17 +1352,17 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsubadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, /* A8 */ - { "vfmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, /* B0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1370,17 +1370,17 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsubadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, /* B8 */ - { "vfmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, - { "vfnmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, /* C0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -1406,8 +1406,590 @@ static const struct dis386 evex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_D6) }, - { PREFIX_TABLE (PREFIX_EVEX_MAP6_D7) }, + { Bad_Opcode }, + { Bad_Opcode }, + /* D8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* E0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* E8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* F0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* F8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* EVEX_MAP6_ */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_13) }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vscalefp%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vscalefs%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { "vgetexpp%XH", { XM, EXxh, EXxEVexS }, PREFIX_DATA }, + { "vgetexps%XH", { XMScalar, VexScalar, EXw, EXxEVexS }, PREFIX_DATA }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vrcpp%XH", { XM, EXxh }, PREFIX_DATA }, + { "vrcps%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA }, + { "vrsqrtp%XH", { XM, EXxh }, PREFIX_DATA }, + { "vrsqrts%XH", { XMScalar, VexScalar, EXw }, PREFIX_DATA }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_56) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_57) }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsubadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + /* 98 */ + { "vfmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub132s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + /* A0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsubadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + /* A8 */ + { "vfmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub213p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub213s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + /* B0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "vfmaddsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsubadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + /* B8 */ + { "vfmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmadd231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA }, + { "vfnmsub231s%XH", { XMScalar, VexScalar, EXw, EXxEVexR }, PREFIX_DATA }, + /* C0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* C8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* D0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_D6) }, + { PREFIX_TABLE (PREFIX_EVEX_MAP6_D7) }, + /* D8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* E0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* E8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* F0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* F8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + }, + /* EVEX_MAP7_ */ + { + /* 00 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 08 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 10 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 18 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 20 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 28 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 30 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 38 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 40 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 50 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 58 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 60 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 68 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 70 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 78 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 80 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 88 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 90 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* A0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* A8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* B0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* B8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* C0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* C8 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + /* D0 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, /* D8 */ { Bad_Opcode }, { Bad_Opcode }, diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 65bdd6f65db..c8f3cfb8149 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -132,6 +132,13 @@ enum x86_64_isa intel64 }; +enum evex_type +{ + evex_default = 0, + evex_from_legacy, + evex_from_vex, +}; + struct instr_info { enum address_mode address_mode; @@ -212,7 +219,6 @@ struct instr_info int ll; bool w; bool evex; - bool r; bool v; bool zeroing; bool b; @@ -220,6 +226,8 @@ struct instr_info } vex; + enum evex_type evex_type; + /* Remember if the current op is a jump instruction. */ bool op_is_jump; @@ -793,6 +801,7 @@ enum USE_RM_TABLE, USE_PREFIX_TABLE, USE_X86_64_TABLE, + USE_X86_64_EVEX_FROM_VEX_TABLE, USE_3BYTE_TABLE, USE_XOP_8F_TABLE, USE_VEX_C4_TABLE, @@ -811,6 +820,8 @@ enum #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) +#define X86_64_EVEX_FROM_VEX_TABLE(I) \ + DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I)) #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0) #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0) @@ -870,7 +881,9 @@ enum REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6_L_2, - REG_EVEX_0F38C7_L_2 + REG_EVEX_0F38C7_L_2, + REG_EVEX_0F38F3_L_0, + REG_EVEX_MAP4_D8_PREFIX_1 }; enum @@ -910,6 +923,19 @@ enum MOD_0F38DC_PREFIX_1, MOD_VEX_0F3849_X86_64_L_0_W_0, + + MOD_EVEX_MAP4_65, + MOD_EVEX_MAP4_66_PREFIX_0, + MOD_EVEX_MAP4_DA_PREFIX_1, + MOD_EVEX_MAP4_DB_PREFIX_1, + MOD_EVEX_MAP4_DC_PREFIX_1, + MOD_EVEX_MAP4_DD_PREFIX_1, + MOD_EVEX_MAP4_DE_PREFIX_1, + MOD_EVEX_MAP4_DF_PREFIX_1, + MOD_EVEX_MAP4_F8_PREFIX_1, + MOD_EVEX_MAP4_F8_PREFIX_2, + MOD_EVEX_MAP4_F8_PREFIX_3, + MOD_EVEX_MAP4_F9, }; enum @@ -1145,6 +1171,22 @@ enum PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3AC2, + PREFIX_EVEX_MAP4_60, + PREFIX_EVEX_MAP4_61, + PREFIX_EVEX_MAP4_66, + PREFIX_EVEX_MAP4_D8, + PREFIX_EVEX_MAP4_DA, + PREFIX_EVEX_MAP4_DB, + PREFIX_EVEX_MAP4_DC, + PREFIX_EVEX_MAP4_DD, + PREFIX_EVEX_MAP4_DE, + PREFIX_EVEX_MAP4_DF, + PREFIX_EVEX_MAP4_F0, + PREFIX_EVEX_MAP4_F1, + PREFIX_EVEX_MAP4_F2, + PREFIX_EVEX_MAP4_F8, + PREFIX_EVEX_MAP4_FC, + PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11, PREFIX_EVEX_MAP5_1D, @@ -1255,6 +1297,35 @@ enum X86_64_VEX_0F38ED, X86_64_VEX_0F38EE, X86_64_VEX_0F38EF, + + X86_64_EVEX_0F90, + X86_64_EVEX_0F91, + X86_64_EVEX_0F92, + X86_64_EVEX_0F93, + X86_64_EVEX_0F3849, + X86_64_EVEX_0F384B, + X86_64_EVEX_0F38E0, + X86_64_EVEX_0F38E1, + X86_64_EVEX_0F38E2, + X86_64_EVEX_0F38E3, + X86_64_EVEX_0F38E4, + X86_64_EVEX_0F38E5, + X86_64_EVEX_0F38E6, + X86_64_EVEX_0F38E7, + X86_64_EVEX_0F38E8, + X86_64_EVEX_0F38E9, + X86_64_EVEX_0F38EA, + X86_64_EVEX_0F38EB, + X86_64_EVEX_0F38EC, + X86_64_EVEX_0F38ED, + X86_64_EVEX_0F38EE, + X86_64_EVEX_0F38EF, + X86_64_EVEX_0F38F2, + X86_64_EVEX_0F38F3, + X86_64_EVEX_0F38F5, + X86_64_EVEX_0F38F6, + X86_64_EVEX_0F38F7, + X86_64_EVEX_0F3AF0, }; enum @@ -1282,8 +1353,10 @@ enum EVEX_0F = 0, EVEX_0F38, EVEX_0F3A, + EVEX_MAP4, EVEX_MAP5, EVEX_MAP6, + EVEX_MAP7, }; enum @@ -1436,6 +1509,8 @@ enum EVEX_LEN_0F385B, EVEX_LEN_0F38C6, EVEX_LEN_0F38C7, + EVEX_LEN_0F38F2, + EVEX_LEN_0F38F3, EVEX_LEN_0F3A00, EVEX_LEN_0F3A01, EVEX_LEN_0F3A18, @@ -4476,6 +4551,8 @@ static const struct dis386 x86_64_table[][2] = { { Bad_Opcode }, { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, }, + +#include "i386-dis-evex-x86.h" }; static const struct dis386 three_byte_table[][256] = { @@ -8665,6 +8742,9 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) dp = &prefix_table[dp->op[1].bytemode][vindex]; break; + case USE_X86_64_EVEX_FROM_VEX_TABLE: + ins->evex_type = evex_from_vex; + /* Fall through. */ case USE_X86_64_TABLE: vindex = ins->address_mode == mode_64bit ? 1 : 0; dp = &x86_64_table[dp->op[1].bytemode][vindex]; @@ -8910,9 +8990,13 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) if (!fetch_code (ins->info, ins->codep + 4)) return &err_opcode; /* The first byte after 0x62. */ + if (*ins->codep & 0x8) + ins->rex2 |= REX_B; + if (!(*ins->codep & 0x10)) + ins->rex2 |= REX_R; + ins->rex = ~(*ins->codep >> 5) & 0x7; - ins->vex.r = *ins->codep & 0x10; - switch ((*ins->codep & 0xf)) + switch ((*ins->codep & 0x7)) { default: return &bad_opcode; @@ -8925,12 +9009,19 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) case 0x3: vex_table_index = EVEX_0F3A; break; + case 0x4: + vex_table_index = EVEX_MAP4; + ins->evex_type = evex_from_legacy; + break; case 0x5: vex_table_index = EVEX_MAP5; break; case 0x6: vex_table_index = EVEX_MAP6; break; + case 0x7: + vex_table_index = EVEX_MAP7; + break; } /* The second byte after 0x62. */ @@ -8941,9 +9032,8 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; - /* The U bit. */ if (!(*ins->codep & 0x4)) - return &bad_opcode; + ins->rex2 |= REX_X; switch ((*ins->codep & 0x3)) { @@ -8973,9 +9063,12 @@ get_valid_dis386 (const struct dis386 *dp, instr_info *ins) if (ins->address_mode != mode_64bit) { + if (ins->evex_type != evex_default + || (ins->rex2 & (REX_B | REX_X))) + return &bad_opcode; /* In 16/32-bit mode silently ignore following bits. */ ins->rex &= ~REX_B; - ins->vex.r = true; + ins->rex2 &= ~REX_R; } ins->need_vex = 4; @@ -9391,6 +9484,13 @@ print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) dp = get_valid_dis386 (dp, &ins); if (dp == &err_opcode) goto fetch_error_out; + + /* For APX instructions promoted from legacy maps 0/1, prefix + 0x66 is interpreted as the operand size override. */ + if (ins.evex_type == evex_from_legacy + && ins.vex.prefix == DATA_PREFIX_OPCODE) + sizeflag ^= DFLAG; + if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0) { if (!get_sib (&ins, sizeflag)) @@ -10280,7 +10380,7 @@ putop (instr_info *ins, const char *in_template, int sizeflag) { case 'X': if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2 - || !ins->vex.r + || (ins->rex2 & REX_R) || (ins->modrm.mod == 3 && (ins->rex & REX_X)) || !ins->vex.v || ins->vex.mask_register_specifier) break; @@ -11174,7 +11274,7 @@ print_register (instr_info *ins, unsigned int reg, unsigned int rexmask, case b_swap_mode: if (reg & 4) USED_REX (0); - if (ins->rex) + if (ins->rex || ins->rex2) names = att_names8rex; else names = att_names8; @@ -11390,7 +11490,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) int riprel = 0; int shift; - if (ins->vex.evex) + if (ins->vex.evex && ins->evex_type == evex_default) { /* Zeroing-masking is invalid for memory destinations. Set the flag @@ -11737,7 +11837,7 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag) if (ins->rex & REX_R) modrm_reg += 8; - if (!ins->vex.r) + if (ins->rex2 & REX_R) modrm_reg += 16; if (vindex == modrm_reg) oappend (ins, "/(bad)"); @@ -11939,10 +12039,7 @@ OP_indirE (instr_info *ins, int bytemode, int sizeflag) static bool OP_G (instr_info *ins, int bytemode, int sizeflag) { - if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit) - oappend (ins, "(bad)"); - else - print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); + print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); return true; } @@ -12572,7 +12669,7 @@ OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) reg += 8; if (ins->vex.evex) { - if (!ins->vex.r) + if (ins->rex2 & REX_R) reg += 16; } @@ -13579,7 +13676,7 @@ DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag) /* Calc destination register number. */ if (ins->rex & REX_R) modrm_reg += 8; - if (!ins->vex.r) + if (ins->rex2 & REX_R) modrm_reg += 16; /* Calc src1 register number. */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 6b8eb729797..f43cb1ecf7c 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -1023,6 +1023,7 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, SPACE(0F), SPACE(0F38), SPACE(0F3A), + SPACE(EVEXMAP4), SPACE(EVEXMAP5), SPACE(EVEXMAP6), SPACE(XOP08), @@ -1121,6 +1122,15 @@ process_i386_opcode_modifier (FILE *table, char *mod, unsigned int space, fprintf (stderr, "%s: %d: W modifier without Word/Dword/Qword operand(s)\n", filename, lineno); + if (modifiers[Vex].value + || (space > SPACE_0F + && !(space == SPACE_EVEXMAP4 + || modifiers[EVex].value + || modifiers[Disp8MemShift].value + || modifiers[Broadcast].value + || modifiers[Masking].value + || modifiers[SAE].value))) + modifiers[No_egpr].value = 1; } if (space >= ARRAY_SIZE (spaces) || !spaces[space]) diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index a055db5ce42..9dd5625f54d 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -972,6 +972,7 @@ typedef struct insn_template 1: 0F opcode prefix / space. 2: 0F38 opcode prefix / space. 3: 0F3A opcode prefix / space. + 4: EVEXMAP4 opcode prefix / space. 5: EVEXMAP5 opcode prefix / space. 6: EVEXMAP6 opcode prefix / space. 8: XOP 08 opcode space. @@ -982,6 +983,7 @@ typedef struct insn_template #define SPACE_0F 1 #define SPACE_0F38 2 #define SPACE_0F3A 3 +#define SPACE_EVEXMAP4 4 #define SPACE_EVEXMAP5 5 #define SPACE_EVEXMAP6 6 #define SPACE_XOP08 8 diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 80248e5b72c..791a9fe0177 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -109,6 +109,7 @@ #define SpaceXOP09 OpcodeSpace=SPACE_XOP09 #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A +#define EVexMap4 OpcodeSpace=SPACE_EVEXMAP4 #define EVexMap5 OpcodeSpace=SPACE_EVEXMAP5 #define EVexMap6 OpcodeSpace=SPACE_EVEXMAP6 @@ -187,6 +188,7 @@ mov, 0xf24, i386|No64, D|RegMem|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf, { Te // Move after swapping the bytes movbe, 0x0f38f0, Movbe, D|Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movbe, 0x60, Movbe|APX_F|x64, D|Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVex128|EVexMap4, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // Move with sign extend. movsb, 0xfbe, i386, Modrm|No_bSuf|No_sSuf, { Reg8|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } @@ -300,6 +302,9 @@ sbb, 0x18, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg sbb, 0x83/3, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } sbb, 0x1c, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } sbb, 0x80/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x18, APX_F|x64, D|W|CheckOperandSize|Modrm|EVex128|EVexMap4|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x83/3, APX_F|x64, Modrm|EVex128|EVexMap4|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +sbb, 0x80/3, APX_F|x64, W|Modrm|EVex128|EVexMap4|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } cmp, 0x38, 0, D|W|CheckOperandSize|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } cmp, 0x83/7, 0, Modrm|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } @@ -332,9 +337,14 @@ adc, 0x10, 0, D|W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg adc, 0x83/2, 0, Modrm|No_bSuf|No_sSuf|HLEPrefixLock, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } adc, 0x14, 0, W|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Acc|Byte|Word|Dword|Qword } adc, 0x80/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x10, APX_F|x64, D|W|CheckOperandSize|Modrm|EVex128|EVexMap4|No_sSuf, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x83/2, APX_F|x64, Modrm|EVex128|EVexMap4|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex } +adc, 0x80/2, APX_F|x64, W|Modrm|EVex128|EVexMap4|No_sSuf, { Imm8|Imm16|Imm32|Imm32S, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } neg, 0xf6/3, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } + not, 0xf6/2, 0, W|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +not, 0xf6/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } aaa, 0x37, No64, NoSuf, {} aas, 0x3f, No64, NoSuf, {} @@ -395,11 +405,19 @@ rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword| rcl, 0xc0/2, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd2/2, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcl, 0xd0/2, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xc0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd2/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcl, 0xd0/2, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xc0/3, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd2/3, 0, W|Modrm|No_sSuf, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } rcr, 0xd0/3, 0, W|Modrm|No_sSuf, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xc0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd2/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { ShiftCount, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } +rcr, 0xd0/3, APX_F|x64, W|Modrm|No_sSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xd0/4, 0, W|Modrm|No_sSuf, { Imm1, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } sal, 0xc0/4, i186, W|Modrm|No_sSuf, { Imm8, Reg8|Reg16|Reg32|Reg64|Byte|Word|Dword|Qword|Unspecified|BaseIndex } @@ -1312,13 +1330,16 @@ getsec, 0xf37, SMX, NoSuf, {} invept, 0x660f3880, EPT|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invept, 0x660f3880, EPT|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invept, 0xf3f0, APX_F|EPT|x64, Modrm|NoSuf|NoRex64|EVex128|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } invvpid, 0x660f3881, EPT|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invvpid, 0x660f3881, EPT|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invvpid, 0xf3f1, APX_F|EPT|x64, Modrm|NoSuf|NoRex64|EVex128|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } // INVPCID instruction invpcid, 0x660f3882, INVPCID|No64, Modrm|IgnoreSize|NoSuf, { Oword|Unspecified|BaseIndex, Reg32 } invpcid, 0x660f3882, INVPCID|x64, Modrm|NoSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 } +invpcid, 0xf3f2, APX_F|INVPCID|x64, Modrm|NoSuf|NoRex64|EVex128|EVexMap4, { Oword|Unspecified|BaseIndex, Reg64 } // SSSE3 instructions. @@ -1418,7 +1439,9 @@ pcmpestrm, 0x660f3a60, SSE4_2|x64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { I pcmpistri, 0x660f3a63, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } pcmpistrm, 0x660f3a62, , Modrm||NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } crc32, 0xf20f38f0, SSE4_2, W|Modrm|No_sSuf|No_qSuf, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } +crc32, 0xf0, APX_F|x64, W|Modrm|No_sSuf|No_qSuf|EVex128|EVexMap4, { Reg8|Reg16|Reg32|Unspecified|BaseIndex, Reg32 } crc32, 0xf20f38f0, SSE4_2|x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } +crc32, 0xf0, APX_F|x64, W|Modrm|No_wSuf|No_lSuf|No_sSuf|EVex128|EVexMap4, { Reg8|Reg64|Unspecified|BaseIndex, Reg64 } // xsave/xrstor New Instructions. @@ -1822,13 +1845,21 @@ xtest, 0xf01d6, HLE|RTM, NoSuf, {} // BMI2 instructions. bzhi, 0xf5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +bzhi, 0xf5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } mulx, 0xf2f6, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +mulx, 0xf2f6, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } pdep, 0xf2f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +pdep, 0xf2f5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } pext, 0xf3f5, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +pext, 0xf3f5, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } rorx, 0xf2f0, BMI2, Modrm|CheckOperandSize|Vex128|Space0F3A|No_bSuf|No_wSuf|No_sSuf, { Imm8|Imm8S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } +rorx, 0xf2f0, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F3A|No_bSuf|No_wSuf|No_sSuf, { Imm8|Imm8S, Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex, Reg32|Reg64 } sarx, 0xf3f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +sarx, 0xf3f7, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } shlx, 0x66f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +shlx, 0x66f7, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } shrx, 0xf2f7, BMI2, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +shrx, 0xf2f7, BMI2|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } // FMA4 instructions @@ -1899,10 +1930,15 @@ lwpins, 0x12/0, LWP, Modrm|SpaceXOP0A|NoSuf|VexVVVV|Vex, { Imm32|Imm32S, Reg32|U // BMI instructions andn, 0xf2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } +andn, 0xf2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64, Reg32|Reg64 } bextr, 0xf7, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +bextr, 0xf7, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|SwapSources|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsi, 0xf3/3, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsi, 0xf3/3, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsmsk, 0xf3/2, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsmsk, 0xf3/2, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } blsr, 0xf3/1, BMI, Modrm|CheckOperandSize|Vex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +blsr, 0xf3/1, BMI|APX_F, Modrm|CheckOperandSize|EVex128|Space0F38|VexVVVV|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } tzcnt, 0xf30fbc, BMI, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // TBM instructions @@ -2007,7 +2043,9 @@ xstore, 0xfa7c0, PadLock, NoSuf|RepPrefixOk, {} // Multy-precision Add Carry, rdseed instructions. adcx, 0x660f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +adcx, 0x6666, ADX|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVex128|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } adox, 0xf30f38f6, ADX, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } +adox, 0xf366, ADX|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVex128|EVexMap4, { Reg32|Reg64|Unspecified|BaseIndex, Reg32|Reg64 } rdseed, 0xfc7/7, RdSeed, Modrm|NoSuf, { Reg16|Reg32|Reg64 } // SMAP instructions. @@ -2031,13 +2069,20 @@ bndldx, 0x0f1a, MPX, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex, RegBND } // SHA instructions. sha1rnds4, 0xf3acc, SHA, Modrm|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } +sha1rnds4, 0xd4, SHA|APX_F, Modrm|NoSuf|EVex128|EVexMap4, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } sha1nexte, 0xf38c8, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1nexte, 0xd8, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha1msg1, 0xf38c9, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1msg1, 0xd9, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha1msg2, 0xf38ca, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha1msg2, 0xda, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256rnds2, 0xdb, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha256msg1, 0xf38cc, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256msg1, 0xdc, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } sha256msg2, 0xf38cd, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } +sha256msg2, 0xdd, SHA|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { RegXMM|Unspecified|BaseIndex, RegXMM } // SHA512 instructions. @@ -2104,8 +2149,11 @@ kxnor, 0x46, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { kxor, 0x47, , Modrm|Vex256|Space0F|VexVVVV|VexW0|NoSuf, { RegMask, RegMask, RegMask } kmov, 0x90, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +kmov, 0x90, |APX_F, Modrm|EVex128|Space0F|VexW0|NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } kmov, 0x91, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, |Unspecified|BaseIndex } +kmov, 0x91, |APX_F, Modrm|EVex128|Space0F|VexW0|NoSuf, { RegMask, |Unspecified|BaseIndex } kmov, 0x92, , D|Modrm|Vex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } +kmov, 0x92, |APX_F, D|Modrm|EVex128|Space0F|VexW0|NoSuf, { Reg32, RegMask } knot, 0x44, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } kortest, 0x98, , Modrm|Vex128|Space0F|VexW0|NoSuf, { RegMask, RegMask } @@ -2626,8 +2674,11 @@ kadd, 0x4a, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1|| kand, 0x41, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } kandn, 0x42, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf|Optimize, { RegMask, RegMask, RegMask } kmov, 0x90, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } +kmov, 0x90, AVX512BW|APX_F, Modrm|EVex128|Space0F|VexW1||NoSuf, { RegMask||Unspecified|BaseIndex, RegMask } kmov, 0x91, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, |Unspecified|BaseIndex } +kmov, 0x91, AVX512BW|APX_F, Modrm|EVex128|Space0F|VexW1||NoSuf, { RegMask, |Unspecified|BaseIndex } kmov, 0xf292, AVX512BW, D|Modrm|Vex128|Space0F|||NoSuf, { , RegMask } +kmov, 0xf292, AVX512BW|APX_F, D|Modrm|EVex128|Space0F|||NoSuf, { , RegMask } knot, 0x44, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } kor, 0x45, AVX512BW, Modrm|Vex256|Space0F|VexVVVV|VexW1||NoSuf, { RegMask, RegMask, RegMask } kortest, 0x98, AVX512BW, Modrm|Vex128|Space0F|VexW1||NoSuf, { RegMask, RegMask } @@ -3046,9 +3097,13 @@ rdsspq, 0xf30f1e/1, SHSTK|x64, Modrm|NoSuf, { Reg64 } saveprevssp, 0xf30f01ea, SHSTK, NoSuf, {} rstorssp, 0xf30f01/5, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } wrssd, 0x0f38f6, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrssd, 0x66, SHSTK|APX_F|x64, Modrm|IgnoreSize|NoSuf|EVex128|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex } wrssq, 0x0f38f6, SHSTK|x64, Modrm|NoSuf|Size64, { Reg64, Qword|Unspecified|BaseIndex } +wrssq, 0x66, APX_F|SHSTK|x64, Modrm|NoSuf|Size64|EVex128|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex } wrussd, 0x660f38f5, SHSTK, Modrm|IgnoreSize|NoSuf, { Reg32, Dword|Unspecified|BaseIndex } +wrussd, 0x6665, SHSTK|APX_F|x64, Modrm|IgnoreSize|NoSuf|EVex128|EVexMap4, { Reg32, Dword|Unspecified|BaseIndex } wrussq, 0x660f38f5, SHSTK|x64, Modrm|NoSuf, { Reg64, Qword|Unspecified|BaseIndex } +wrussq, 0x6665, SHSTK|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Reg64, Qword|Unspecified|BaseIndex } setssbsy, 0xf30f01e8, SHSTK, NoSuf, {} clrssbsy, 0xf30fae/6, SHSTK, Modrm|NoSuf, { Qword|Unspecified|BaseIndex } endbr64, 0xf30f1efa, IBT, NoSuf, {} @@ -3096,7 +3151,9 @@ cldemote, 0x0f1c/0, CLDEMOTE, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex } // MOVDIR[I,64B] instructions. movdiri, 0xf38f9, MOVDIRI, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +movdiri, 0xf9, MOVDIRI|APX_F|x64, Modrm|CheckOperandSize|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } movdir64b, 0x660f38f8, MOVDIR64B, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +movdir64b, 0x66f8, MOVDIR64B|APX_F|x64, Modrm|AddrPrefixOpReg|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } // MOVEDIR instructions end. @@ -3125,7 +3182,9 @@ vcvtneps2bf16, 0xf372, AVX_NE_CONVERT, Modrm||Space0F38|VexW0|NoSu // ENQCMD instructions. enqcmd, 0xf20f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +enqcmd, 0xf2f8, ENQCMD|APX_F|x64, Modrm|AddrPrefixOpReg|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } enqcmds, 0xf30f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +enqcmds, 0xf3f8, ENQCMD|APX_F|x64, Modrm|AddrPrefixOpReg|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, Reg32|Reg64 } // ENQCMD instructions end. @@ -3187,7 +3246,9 @@ xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {} // AMX instructions. ldtilecfg, 0x49/0, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +ldtilecfg, 0x49/0, AMX_TILE|APX_F|x64, Modrm|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } sttilecfg, 0x6649/0, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } +sttilecfg, 0x6649/0, AMX_TILE|APX_F|x64, Modrm|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex } tcmmimfp16ps, 0x666c, AMX_COMPLEX|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } tcmmrlfp16ps, 0x6c, AMX_COMPLEX|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } @@ -3200,8 +3261,11 @@ tdpbusd, 0x665e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources| tdpbsud, 0xf35e, AMX_INT8|x64, Modrm|Vex128|Space0F38|VexVVVV|VexW0|SwapSources|NoSuf, { RegTMM, RegTMM, RegTMM } tileloadd, 0xf24b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tileloadd, 0xf24b, AMX_TILE|APX_F|x64, Sibmem|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } tileloaddt1, 0x664b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } +tileloaddt1, 0x664b, AMX_TILE|APX_F|x64, Sibmem|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM } tilestored, 0xf34b, AMX_TILE|x64, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } +tilestored, 0xf34b, AMX_TILE|APX_F|x64, Sibmem|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex } tilerelease, 0x49c0, AMX_TILE|x64, Vex128|Space0F38|VexW0|NoSuf, {} @@ -3213,15 +3277,25 @@ tilezero, 0xf249, AMX_TILE|x64, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM } loadiwkey, 0xf30f38dc, KL, Load|Modrm|NoSuf, { RegXMM, RegXMM } encodekey128, 0xf30f38fa, KL, Modrm|NoSuf, { Reg32, Reg32 } +encodekey128, 0xf3da, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Reg32, Reg32 } encodekey256, 0xf30f38fb, KL, Modrm|NoSuf, { Reg32, Reg32 } +encodekey256, 0xf3db, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Reg32, Reg32 } aesenc128kl, 0xf30f38dc, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesenc128kl, 0xf3dc, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, RegXMM } aesdec128kl, 0xf30f38dd, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesdec128kl, 0xf3dd, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, RegXMM } aesenc256kl, 0xf30f38de, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesenc256kl, 0xf3de, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, RegXMM } aesdec256kl, 0xf30f38df, KL, Modrm|NoSuf, { Unspecified|BaseIndex, RegXMM } +aesdec256kl, 0xf3df, KL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex, RegXMM } aesencwide128kl, 0xf30f38d8/0, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesencwide128kl, 0xf3d8/0, WideKL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex } aesdecwide128kl, 0xf30f38d8/1, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesdecwide128kl, 0xf3d8/1, WideKL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex } aesencwide256kl, 0xf30f38d8/2, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesencwide256kl, 0xf3d8/2, WideKL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex } aesdecwide256kl, 0xf30f38d8/3, WideKL, Modrm|NoSuf, { Unspecified|BaseIndex } +aesdecwide256kl, 0xf3d8/3, WideKL|APX_F|x64, Modrm|NoSuf|EVex128|EVexMap4, { Unspecified|BaseIndex } // KEYLOCKER instructions end. @@ -3370,6 +3444,7 @@ prefetchit1, 0xf18/6, PREFETCHI|x64, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex // CMPCCXADD instructions. cmpxadd, 0x66e, CMPCCXADD|x64, Modrm|Vex|Space0F38|VexVVVV|SwapSources|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +cmpxadd, 0x66e, CMPCCXADD|x64|APX_F, Modrm|EVex128|Space0F38|VexVVVV|SwapSources|CheckOperandSize|NoSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // CMPCCXADD instructions end. @@ -3389,9 +3464,13 @@ wrmsrlist, 0xf30f01c6, MSRLIST|x64, NoSuf, {} // RAO-INT instructions. aadd, 0xf38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aadd, 0xfc, RAO_INT|APX_F|x64, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aand, 0x660f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aand, 0x66fc, RAO_INT|APX_F|x64, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +aor, 0xf2fc, RAO_INT|APX_F|x64, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } +axor, 0xf3fc, RAO_INT|APX_F|x64, Modrm|IgnoreSize|CheckOperandSize|NoSuf|EVex128|EVexMap4, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // RAO-INT instructions end. @@ -3408,3 +3487,4 @@ erets, 0xf20f01ca, FRED|x64, NoSuf, {} eretu, 0xf30f01ca, FRED|x64, NoSuf, {} // FRED instructions end. +