diff --git a/gas/ChangeLog b/gas/ChangeLog
index 94e4e741c6b..147c20c460d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,17 @@
+2023-07-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+	* testsuite/gas/bpf/alu.s: Add test for NEGI and NEG32I.
+	* testsuite/gas/bpf/alu32.s: Likewise.
+	* testsuite/gas/bpf/alu-pseudoc.s: Likewise.
+	* testsuite/gas/bpf/alu32-pseudoc.s: Likewise.
+	* testsuite/gas/bpf/alu.d: Add expected results.
+	* testsuite/gas/bpf/alu-be.d: Likewise.
+	* testsuite/gas/bpf/alu-pseudoc.d: Likewise.
+	* testsuite/gas/bpf/alu-be-pseudoc.d: Likewise.
+	* testsuite/gas/bpf/alu32.d: Likewise.
+	* testsuite/gas/bpf/alu32-be.d: Likewise.
+	* testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise.
+
 2023-07-26  Jose E. Marchesi  <jose.marchesi@oracle.com>
 
 	* testsuite/gas/bpf/alu.s: The register neg instruction gets only
diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d
index b35f05d9242..0e9df07eb15 100644
--- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d
@@ -69,3 +69,4 @@ Disassembly of section .text:
  1d0:	d7 10 00 00 00 00 00 10 	r1 = bswap16 r1
  1d8:	d7 20 00 00 00 00 00 20 	r2 = bswap32 r2
  1e0:	d7 30 00 00 00 00 00 40 	r3 = bswap64 r3
+ 1e8:	b7 10 00 00 ff ff f1 00 	r1=0xfffff100
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d
index fd8bc9ceba1..b961f3fe474 100644
--- a/gas/testsuite/gas/bpf/alu-be.d
+++ b/gas/testsuite/gas/bpf/alu-be.d
@@ -69,3 +69,4 @@ Disassembly of section .text:
  1d0:	d7 10 00 00 00 00 00 10 	bswap %r1,16
  1d8:	d7 20 00 00 00 00 00 20 	bswap %r2,32
  1e0:	d7 30 00 00 00 00 00 40 	bswap %r3,64
+ 1e8:	87 10 00 00 00 00 0f 00 	neg %r1,0xf00
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d
index ce0a56d1f21..bbd222c83ae 100644
--- a/gas/testsuite/gas/bpf/alu-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu-pseudoc.d
@@ -69,3 +69,4 @@ Disassembly of section .text:
  1d0:	d7 01 00 00 10 00 00 00 	r1 = bswap16 r1
  1d8:	d7 02 00 00 20 00 00 00 	r2 = bswap32 r2
  1e0:	d7 03 00 00 40 00 00 00 	r3 = bswap64 r3
+ 1e8:	b7 01 00 00 00 f1 ff ff 	r1=0xfffff100
diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s
index 323a6522f22..abd8ddcc38e 100644
--- a/gas/testsuite/gas/bpf/alu-pseudoc.s
+++ b/gas/testsuite/gas/bpf/alu-pseudoc.s
@@ -61,3 +61,7 @@
         r1 = bswap16 r1
         r2 = bswap32 r2
         r3 = bswap64 r3
+        ;; Note that the next instruction gets processed by the GAS
+        ;; preprocessor into r1 =-0xf00, which parses into a %dr = %i32
+        ;; instruction instead of a neg :/
+	r1 = - 0xf00
diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d
index 15e817b8fc5..e4afdab0d50 100644
--- a/gas/testsuite/gas/bpf/alu.d
+++ b/gas/testsuite/gas/bpf/alu.d
@@ -69,3 +69,4 @@ Disassembly of section .text:
  1d0:	d7 01 00 00 10 00 00 00 	bswap %r1,16
  1d8:	d7 02 00 00 20 00 00 00 	bswap %r2,32
  1e0:	d7 03 00 00 40 00 00 00 	bswap %r3,64
+ 1e8:	87 01 00 00 00 0f 00 00 	neg %r1,0xf00
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s
index 2d8d22da0e1..d0bf5600209 100644
--- a/gas/testsuite/gas/bpf/alu.s
+++ b/gas/testsuite/gas/bpf/alu.s
@@ -61,3 +61,4 @@
         bswap   %r1, 16
         bswap   %r2, 32
         bswap   %r3, 64
+        neg     %r1, 0xf00
diff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
index 71c6d3aec87..7f5e70071fc 100644
--- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
@@ -60,3 +60,4 @@ Disassembly of section .text:
  188:	bc 12 00 08 00 00 00 00 	w1 = \(s8\) w2
  190:	bc 12 00 10 00 00 00 00 	w1 = \(s16\) w2
  198:	bc 12 00 20 00 00 00 00 	w1 = \(s32\) w2
+ 1a0:	b4 10 00 00 ff ff f1 00 	w1=0xfffff100
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d
index 140a7f13764..9799664b27a 100644
--- a/gas/testsuite/gas/bpf/alu32-be.d
+++ b/gas/testsuite/gas/bpf/alu32-be.d
@@ -60,3 +60,4 @@ Disassembly of section .text:
  188:	bc 12 00 08 00 00 00 00 	movs32 %r1,%r2,8
  190:	bc 12 00 10 00 00 00 00 	movs32 %r1,%r2,16
  198:	bc 12 00 20 00 00 00 00 	movs32 %r1,%r2,32
+ 1a0:	84 10 00 00 00 00 0f 00 	neg32 %r1,0xf00
diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/alu32-pseudoc.d
index 16e38ac212c..cc4e010b201 100644
--- a/gas/testsuite/gas/bpf/alu32-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d
@@ -60,3 +60,4 @@ Disassembly of section .text:
  188:	bc 21 08 00 00 00 00 00 	w1 = \(s8\) w2
  190:	bc 21 10 00 00 00 00 00 	w1 = \(s16\) w2
  198:	bc 21 20 00 00 00 00 00 	w1 = \(s32\) w2
+ 1a0:	b4 01 00 00 00 f1 ff ff 	w1=0xfffff100
diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/alu32-pseudoc.s
index 46c4e15a4b7..98d586a48e6 100644
--- a/gas/testsuite/gas/bpf/alu32-pseudoc.s
+++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s
@@ -52,3 +52,7 @@
         w1 = (s8) w2
         w1 = (s16) w2
         w1 = (s32) w2
+        ;; Note that the next instruction gets processed by the GAS
+        ;; preprocessor into w1 =-0xf00, which parses into a %dw = %i32
+        ;; instruction instead of a neg :/
+	w1 = - 0xf00
diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d
index 3bdaf1252e6..25484381aeb 100644
--- a/gas/testsuite/gas/bpf/alu32.d
+++ b/gas/testsuite/gas/bpf/alu32.d
@@ -60,3 +60,4 @@ Disassembly of section .text:
  188:	bc 21 08 00 00 00 00 00 	movs32 %r1,%r2,8
  190:	bc 21 10 00 00 00 00 00 	movs32 %r1,%r2,16
  198:	bc 21 20 00 00 00 00 00 	movs32 %r1,%r2,32
+ 1a0:	84 01 00 00 00 0f 00 00 	neg32 %r1,0xf00
\ No newline at end of file
diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s
index 291f9ced6a7..fd1d528ba21 100644
--- a/gas/testsuite/gas/bpf/alu32.s
+++ b/gas/testsuite/gas/bpf/alu32.s
@@ -52,3 +52,4 @@
         movs32  %r1,%r2,8
         movs32  %r1,%r2,16
         movs32  %r1,%r2,32
+        neg32   %r1, 0xf00
