From patchwork Fri Jul 21 18:01:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jose E. Marchesi" X-Patchwork-Id: 124045 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:9010:0:b0:3e4:2afc:c1 with SMTP id l16csp376293vqg; Fri, 21 Jul 2023 11:02:33 -0700 (PDT) X-Google-Smtp-Source: APBJJlE1Quv0z9FBGTPzdIcOEdpddaEJLSQf6Pog3bAiujKEzYvyHmFZWOO1b3vpK4ODawikrsFx X-Received: by 2002:a17:906:2208:b0:991:e815:a1ef with SMTP id s8-20020a170906220800b00991e815a1efmr2247244ejs.31.1689962553141; Fri, 21 Jul 2023 11:02:33 -0700 (PDT) Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id kg13-20020a17090776ed00b00993253791d2si2600557ejc.575.2023.07.21.11.02.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Jul 2023 11:02:33 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ZFThd80V; arc=fail (signature failed); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B8011385E017 for ; Fri, 21 Jul 2023 18:02:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B8011385E017 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1689962547; bh=6+mYrNTjfoQ2efLJCqs5wQ/lXDf4FE2lMaivJmSj9K4=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=ZFThd80VO8LJrIgiSHocRxxZSNUF08NRK6XLlL/DWwAVKcKcsBBdJ8zUVgHuSyfDa pVf8pS1+CvarlYjpCOKDUBqfhBak3iEreT1JX+mnv+PWTJJ/WYBz7HfdBSu440G/FH re1udHmUg8ioZ1PhcXZsg43B5RgZ1iv+V8guIa34= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mx0a-00069f02.pphosted.com (mx0a-00069f02.pphosted.com [205.220.165.32]) by sourceware.org (Postfix) with ESMTPS id 6BE5C3858410 for ; Fri, 21 Jul 2023 18:02:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6BE5C3858410 Received: from pps.filterd (m0246629.ppops.net [127.0.0.1]) by mx0b-00069f02.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36LEGE6R011981 for ; Fri, 21 Jul 2023 18:02:13 GMT Received: from iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (iadpaimrmta03.appoci.oracle.com [130.35.103.27]) by mx0b-00069f02.pphosted.com (PPS) with ESMTPS id 3run784e1h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 21 Jul 2023 18:02:13 +0000 Received: from pps.filterd (iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com [127.0.0.1]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (8.17.1.19/8.17.1.19) with ESMTP id 36LHZfQR023826 for ; Fri, 21 Jul 2023 18:02:12 GMT Received: from nam11-bn8-obe.outbound.protection.outlook.com (mail-bn8nam11lp2169.outbound.protection.outlook.com [104.47.58.169]) by iadpaimrmta03.imrmtpd1.prodappiadaev1.oraclevcn.com (PPS) with ESMTPS id 3ruhwaj8r8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Fri, 21 Jul 2023 18:02:12 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nx/Ue7/EsRURDAww59xsaKMn1sjFTg5Ud9bsEmPcm2avAd2uPouT9EL7gVpZUyC859cXn1+el/Uz5ZV7uGzNCp4ar9Ql0OMJbYDZ4jNgjTpXMhd2doFGlJFxpysBI36MDLr5BNk+Yh9cno+6jTUh5dAnzVvtt9c5T0DPC6WE5wMcPdvjKLvBdwW1CNfmuW3DSdtUpExP1kFC18rQU5QkheknGvMn+Jq5tm8hTflSWzd/1ojCmjYpPvaWW62jj+t5o35blPEOadRKYs4sI9IvkCrF5vlfH97CeuVcPLA5AJDSxWaxPTmu3rZlgFSz5YL+j+8xXBFPn3Swmtj2R2MKCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6+mYrNTjfoQ2efLJCqs5wQ/lXDf4FE2lMaivJmSj9K4=; b=DvcX58mpS7JWWhgqKVs61banZQsacg8u1a175vbnLCoaGVxLyTFXw/4phf1Fi9Cr3rO6XHbCDdk4Nuzsq6E911ixBo8UmNzEG5xruiiQZqmxRX80PC9dO6oR6vMpShAvb557w2H9Aho9wck6JocuK7qPK2Bkk4ptU+U2gHIUyLsiXXGzzJKUfL8WCe41N2IfxB1yYliujeSb561WziQycU4nxcSIJMtlJkP1fU4HB5TqKujDHVcGzxHXSaablX18D2mqStS2jnLhdSggZEqZMezinEb8a2o9w5ufUlrNuMa1/RK4qnU72in2xRVKlp1HtT6c6xgmZdGZmf5IWXvewA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=oracle.com; dmarc=pass action=none header.from=oracle.com; dkim=pass header.d=oracle.com; arc=none Received: from BYAPR10MB2888.namprd10.prod.outlook.com (2603:10b6:a03:88::32) by SA1PR10MB7855.namprd10.prod.outlook.com (2603:10b6:806:3a7::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6609.23; Fri, 21 Jul 2023 18:02:09 +0000 Received: from BYAPR10MB2888.namprd10.prod.outlook.com ([fe80::4d0c:9857:9b42:2f6c]) by BYAPR10MB2888.namprd10.prod.outlook.com ([fe80::4d0c:9857:9b42:2f6c%4]) with mapi id 15.20.6609.026; Fri, 21 Jul 2023 18:02:08 +0000 To: binutils@sourceware.org Subject: [COMMITTED 1/2] bpf: opcodes, gas: support for signed register move V4 instructions Date: Fri, 21 Jul 2023 20:01:58 +0200 Message-Id: <20230721180158.8573-1-jose.marchesi@oracle.com> X-Mailer: git-send-email 2.30.2 X-ClientProxiedBy: LO2P265CA0502.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:13b::9) To BYAPR10MB2888.namprd10.prod.outlook.com (2603:10b6:a03:88::32) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR10MB2888:EE_|SA1PR10MB7855:EE_ X-MS-Office365-Filtering-Correlation-Id: 6bc4c527-a1eb-4ee7-c175-08db8a14999c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: TJhTSCFGs6awKrLxScwMzANEAJDJ8TWpkxXwIoO5ASPXFd/YSenVJ8H9EUGa1qKSWxtjZc5+GDyZJCgwx05mHvg+zHx+VQvMFrCr75YnPvYhPsaI8mo6zjH5ucfwTSqwJKfngvu31MfJDsqvQvogeI7Izgogwl6BvOsLliwTrPEfgsgQ4D615+vN43nbYOup5Z0jlT7hVztSo1LWvQlj53giH6N2oMW4Qghh/6fyMnvS3Yq8YU91iOEODvSjR4Cjgvm3xnJGs7QmJ3zuVrUlRW2m0k8zcN4RuY9sLEIF+wqrr9FPgds4qZ/p8a7fbFEy9HTCvVUmqYBq+Ix3F779RiC0Kz649SnPPFBoDtKKtIxXp8ob/pXKWKzZBu63ikNBIDZRrFeENi4caBY6tdsRNa7W+cIJGf8JN/XZ3JARRH1pC8SRgZ6pULhaau9NmXaWTedCh2zRVIvMQ3dNu4JRQypdMN/AekZ6lfcRDTSnMUH/KNH7oFgXx/UtKIndyFLgNRDxPEBWLCgd4VxZkLGvYO4zzi+Lr8yM2sXT4c7Em6xOCSGFAIbbwTtn3likg8Mq X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BYAPR10MB2888.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230028)(39860400002)(136003)(366004)(346002)(376002)(396003)(451199021)(2906002)(30864003)(8936002)(8676002)(66556008)(66476007)(66946007)(316002)(41300700001)(5660300002)(6916009)(6486002)(1076003)(6512007)(36756003)(186003)(6506007)(478600001)(6666004)(83380400001)(2616005)(26005)(38100700002)(86362001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7Wmrk3aQMm+akGIczA3nQpVnhazb2BwTcKjI6/HPGM/QQn+7L09nnEMqLzyyCRnjHdEzK4eMQB1G087HH5kTBO8zPWbuKMiZLeTY3z9Ooo0e9Nb5IkpeKfr2tsk8yrAJ7FBBjRact89wqCKo2C8vZif9slOEsnM+k/RGtNfXOWik8X99VgWA9cz90pRpRCtAX9YOaYYr2HpBiyAVxAcz4G4K7+dXFurGQJLNYOexpddWBK/wRxrdSzEr0C4+Lj508YkGVPm8E9BrXyofWFJdcUZSah6pkzkOcCIogFSWtXQnlVN+dTZcDCo0AStKcK++wVuRuASn9gkMnc2iny5OTmzjDDtxLaytm7Kx573YfSkMFhwj/dn0YnijAymTD+Xrt/Lx9d+z+PfMcHTQfY2wQ5GtNYZgbd+QaPXJa9GBUSydSktAZAjSDyoVrU/n2RjDU/4aGMYmQVtzLPkWKeBJhXOkRYPfpYtjjOKy9JD1cFs6Rf3qoFnRMiYyNtFSdY+OHQ0lg7MQiWH6bWaboKSKbA7EtgDgjaooTWrXvKGz2Ea63NPALTdjthXgu9l2ZHJXnSntk3lEMOal9VaybNTmFY6F/dNWKKfDejyUKzntzmXH6TYdwQLZt9kHhh08xHzNCoE3wrw+D2IrPd2iMXZd7znjySJEj82lhkW4AtwjhTvgCKpEhL1Fw3F7OLRuMeFriFTWIuFMxGY9yW9ODRNgDv7suo7Za1cD+5JKlwaf9gkBbwrNnmDbYA7EeNHrlq05QrN1Nx9HUsRKBA4VktKgoSUyOLp3gUp2ysrFjqJkYJCZyORb1CqIt2lRusflZOlTvVdqEmFGuRFV+HM32vA0JBa6Vjny3xVMqPAKbeOAGpU7uTKz3n0BgnvItBBfM9Uve6gPfFuQFnEWtE165kpwOmzT6/XMVreFMWtJbU8PEhpcXLBC9JcyRSDNGXkwSYBz1w7g+3152tKeTn9h1TuuPf7VwTcKdhV/bA+7FSpMnF9iypXcq4Qzu7q3o4N/TAK4ZrqDHcxAYH5SMfzGyVE1HBihG6dbXXj/YcuC0RHwpPbqkYz903HXelpisnuBtXL8hT4kaNnU22MJfEeM5CnSZ1zRy1Cm4Ttx7MqVIDNeykcJYQ4voXgUtXOIoqcvONbqK6nvM8VvncAG8ePqW7ZL+CnesiV+TUfyExSDf5ZJw8dsxfjvJ5QlXDbwXSKevhN3uIEOoOUBzVO9f5ZoOip5uQViHvXKb4nBPe7Bz91fc9WDFY2EyJkWG6yiyXQ18eqt5eA4NKXZ9koQCTwHV7hBOLKC/0H9eXusifluEuwi35FxltY1bus95Ral9nJONS8Znf6nqQjuuGMCJRBv+6LRsX37Oi0WZLK8LRm2jwzHmG0AoNnn06VevPaeYVVIYvDMnsAKWV91MLX1lj2pigVBVGQzHW2gYuT6cFOqyWMgfTnkxxbQnwMwNskeNHBfjAHeEx5xKxubq35T9zMoqNVP469yr3dVgBxQ38+DytVmcigsmsnFYa+4XzZCqT8lZnn0TPxWOmbezwn4IOVyW5KHMOVZUw1yFAuSIn2QG322PO0IpF//+NSk+CAC+9vFO2gDzlXkvVdFG36lBBoqeYz7Gg== X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: cfzq/v2D9NDDpWOc3IT++f8jtWZLq1k6Pqz5XJxYP+qGVfh26Dj1mA4mg9ow4hkDYdf3nazjkL7KnxKA5ecoFtkCywRliGmLq9tH0/drOn1EujsgBOCHpZaPxnTbf2x+SZtwchSQWG+8jalRRx+eSZxUSYP4da/jhlFAm0W5AQHw1htvfFzcMJzyun65u26Yc/YitDBXO90bFuq8TMw09mhbHoH23+3/Aej1APSt8SZtXfqr7BF7/yH0OXCbK6nG9Zjotzhin8n9+7XFoS1M027/ZaLqhgSXmmD5sBCovcL5QB1cZ2hgr3UfuspYSUGAc4w6abB06h69Sn+3WR8fB9eXQjzqpumf3uNyT5IXWnWf5pdgoCqzNkd+k/qJUiHJz2ynDmdUTlZIZWFTDEoiSvXHcsPDVNXUxSBaoEoGM+tJyBaDA02gWLBrdFVkgF0JJ4ZXbvzJcZbsDHGZPnrWd1pltWehdnFZN/VuEtLiOdOhxpEFInELufbr5xWN3K126f4zSaeK9IQXwLBEEYOwADmDJ9IkUn3RIcIokE9Tgqjp7kqSHZkFkuCo+tRGnmW27WvCmQZakA4iOWV6wO4ADE+qngu9HkqPEpsts3HEh8X8zzS+cj2D2h1XyzHNIzAHyeHJC5PlZad49FNjbnixMVe1vsa51HK8Oslom3pUr2dmR2y/oPYEaODyrCotBQYE4hDXd+dvk0jbEpfJsTw8XlFvpckapWICV3nZu2xn8yQFbmP8lwi2dyCxpV9JRWH8 X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-Network-Message-Id: 6bc4c527-a1eb-4ee7-c175-08db8a14999c X-MS-Exchange-CrossTenant-AuthSource: BYAPR10MB2888.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jul 2023 18:02:08.6552 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: U8A3PRyUrTm3tc9O3VT0ko2+GtO8Omsvk7lo7rKcbJv62qjUClQ3u9EYRDd4Yq4n9Fdyuuw7SZg5I7F6GuOz0z2jtu9FTTcXlTkHJUzgkLw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR10MB7855 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-21_10,2023-07-20_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2306200000 definitions=main-2307210158 X-Proofpoint-GUID: IloLD7jvw8h1NlsnIZ33JabuVQADtvTc X-Proofpoint-ORIG-GUID: IloLD7jvw8h1NlsnIZ33JabuVQADtvTc X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Jose E. Marchesi via Binutils" From: "Jose E. Marchesi" Reply-To: "Jose E. Marchesi" Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1772054174047475879 X-GMAIL-MSGID: 1772054174047475879 This commit adds the signed register move (movs) instructions introduced in the BPF ISA version 4, including opcodes and assembler tests. Tested in bpf-unknown-none. include/ChangeLog: 2023-07-21 Jose E. Marchesi * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. (BPF_OFFSET16_MOVS16): Likewise. (BPF_OFFSET16_MOVS32): Likewise. (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R. opcodes/ChangeLog: 2023-07-21 Jose E. Marchesi * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and MOVS32{8,16,32}R instructions. and MOVS32I instructions. gas/ChangeLog: 2023-07-21 Jose E. Marchesi * testsuite/gas/bpf/alu.s: Test movs instructions. * testsuite/gas/bpf/alu-pseudoc.s: Likewise. * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. * testsuite/gas/bpf/alu.d: Add expected results. * testsuite/gas/bpf/alu32.d: Likewise. * testsuite/gas/bpf/alu-be.d: Likewise. * testsuite/gas/bpf/alu32-be.d: Likewise. * testsuite/gas/bpf/alu-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. --- gas/ChangeLog | 15 +++++++++++++++ gas/doc/c-bpf.texi | 24 ++++++++++++++++++++++++ gas/testsuite/gas/bpf/alu-be-pseudoc.d | 3 +++ gas/testsuite/gas/bpf/alu-be.d | 3 +++ gas/testsuite/gas/bpf/alu-pseudoc.d | 3 +++ gas/testsuite/gas/bpf/alu-pseudoc.s | 3 +++ gas/testsuite/gas/bpf/alu.d | 3 +++ gas/testsuite/gas/bpf/alu.s | 3 +++ gas/testsuite/gas/bpf/alu32-be-pseudoc.d | 3 +++ gas/testsuite/gas/bpf/alu32-be.d | 3 +++ gas/testsuite/gas/bpf/alu32-pseudoc.d | 3 +++ gas/testsuite/gas/bpf/alu32-pseudoc.s | 3 +++ gas/testsuite/gas/bpf/alu32.d | 3 +++ gas/testsuite/gas/bpf/alu32.s | 3 +++ include/ChangeLog | 8 ++++++++ include/opcode/bpf.h | 5 +++++ opcodes/ChangeLog | 5 +++++ opcodes/bpf-opc.c | 12 ++++++++++++ 18 files changed, 105 insertions(+) diff --git a/gas/ChangeLog b/gas/ChangeLog index 3d22461266a..66c95a1b9a5 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,18 @@ +2023-07-21 Jose E. Marchesi + + * testsuite/gas/bpf/alu.s: Test movs instructions. + * testsuite/gas/bpf/alu-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu32.s: Likewise for movs32 instruction. + * testsuite/gas/bpf/alu32-pseudoc.s: Likewise. + * testsuite/gas/bpf/alu.d: Add expected results. + * testsuite/gas/bpf/alu32.d: Likewise. + * testsuite/gas/bpf/alu-be.d: Likewise. + * testsuite/gas/bpf/alu32-be.d: Likewise. + * testsuite/gas/bpf/alu-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu-be-pseudoc.d: Likewise. + * testsuite/gas/bpf/alu32-be-pseudoc.d: Likewise. + 2023-07-03 Nick Clifton * configure: Regenerate. diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi index 4742f89ea17..a3814e95c3a 100644 --- a/gas/doc/c-bpf.texi +++ b/gas/doc/c-bpf.texi @@ -259,6 +259,18 @@ ambiguity in the pseudoc syntax. @itemx rd = imm32 Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32} in @code{rd}. + +@item movs rd, rs, 8 +@itemx rd s= (i8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 16 +@itemx rd s= (i16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item movs rd, rs, 32 +@itemx rd s= (i32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. @end table @subsection 32-bit arithmetic instructions @@ -354,6 +366,18 @@ ambiguity in the pseudoc syntax. @itemx rd = imm32 Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32} in @code{rd}. + +@item mov32s rd, rs, 8 +@itemx rd s= (i8) rs +Move the sign-extended 8-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 16 +@itemx rd s= (i16) rs +Move the sign-extended 16-bit value in @code{rs} to @code{rd}. + +@item mov32s rd, rs, 32 +@itemx rd s= (i32) rs +Move the sign-extended 32-bit value in @code{rs} to @code{rd}. @end table @subsection Endianness conversion instructions diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d index 8d8c29e91c7..486d7923478 100644 --- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 60 00 00 00 00 00 10 r6=be16 r6 1a8: dc 50 00 00 00 00 00 20 r5=be32 r5 1b0: dc 40 00 00 00 00 00 40 r4=be64 r4 + 1b8: bf 12 00 08 00 00 00 00 r1 s= \(i8\) r2 + 1c0: bf 12 00 10 00 00 00 00 r1 s= \(i16\) r2 + 1c8: bf 12 00 20 00 00 00 00 r1 s= \(i32\) r2 diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d index 170db4b853d..a082c46af1c 100644 --- a/gas/testsuite/gas/bpf/alu-be.d +++ b/gas/testsuite/gas/bpf/alu-be.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 60 00 00 00 00 00 10 endbe %r6,16 1a8: dc 50 00 00 00 00 00 20 endbe %r5,32 1b0: dc 40 00 00 00 00 00 40 endbe %r4,64 + 1b8: bf 12 00 08 00 00 00 00 movs %r1,%r2,8 + 1c0: bf 12 00 10 00 00 00 00 movs %r1,%r2,16 + 1c8: bf 12 00 20 00 00 00 00 movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d index 5d69e68a4f0..cf1ef2ac029 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu-pseudoc.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 06 00 00 10 00 00 00 r6=be16 r6 1a8: dc 05 00 00 20 00 00 00 r5=be32 r5 1b0: dc 04 00 00 40 00 00 00 r4=be64 r4 + 1b8: bf 21 08 00 00 00 00 00 r1 s= \(i8\) r2 + 1c0: bf 21 10 00 00 00 00 00 r1 s= \(i16\) r2 + 1c8: bf 21 20 00 00 00 00 00 r1 s= \(i32\) r2 diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s index a271bef977d..513c8b8f4f9 100644 --- a/gas/testsuite/gas/bpf/alu-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu-pseudoc.s @@ -55,3 +55,6 @@ r6 = be16 r6 r5 = be32 r5 r4 = be64 r4 + r1 s= (i8) r2 + r1 s= (i16) r2 + r1 s= (i32) r2 diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d index 476891b9afd..409018ddf55 100644 --- a/gas/testsuite/gas/bpf/alu.d +++ b/gas/testsuite/gas/bpf/alu.d @@ -63,3 +63,6 @@ Disassembly of section .text: 1a0: dc 06 00 00 10 00 00 00 endbe %r6,16 1a8: dc 05 00 00 20 00 00 00 endbe %r5,32 1b0: dc 04 00 00 40 00 00 00 endbe %r4,64 + 1b8: bf 21 08 00 00 00 00 00 movs %r1,%r2,8 + 1c0: bf 21 10 00 00 00 00 00 movs %r1,%r2,16 + 1c8: bf 21 20 00 00 00 00 00 movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s index bb3f9265200..6f8c30fff68 100644 --- a/gas/testsuite/gas/bpf/alu.s +++ b/gas/testsuite/gas/bpf/alu.s @@ -55,3 +55,6 @@ endbe %r6,16 endbe %r5,32 endbe %r4,64 + movs %r1,%r2,8 + movs %r1,%r2,16 + movs %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d index 6daad3b6926..79a638fb37e 100644 --- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 40 00 00 7e ad be ef w4 s>>=0x7eadbeef 178: cc 56 00 00 00 00 00 00 w5 s>>=w6 180: 8c 23 00 00 00 00 00 00 w2=-w3 + 188: bc 12 00 08 00 00 00 00 w1 s= \(i8\) w2 + 190: bc 12 00 10 00 00 00 00 w1 s= \(i16\) w2 + 198: bc 12 00 20 00 00 00 00 w1 s= \(i32\) w2 diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d index 6de8f0660d8..0549bf23131 100644 --- a/gas/testsuite/gas/bpf/alu32-be.d +++ b/gas/testsuite/gas/bpf/alu32-be.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 40 00 00 7e ad be ef arsh32 %r4,0x7eadbeef 178: cc 56 00 00 00 00 00 00 arsh32 %r5,%r6 180: 8c 23 00 00 00 00 00 00 neg32 %r2,%r3 + 188: bc 12 00 08 00 00 00 00 movs32 %r1,%r2,8 + 190: bc 12 00 10 00 00 00 00 movs32 %r1,%r2,16 + 198: bc 12 00 20 00 00 00 00 movs32 %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/alu32-pseudoc.d index f339c808d26..175dd1f1cd6 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.d +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 04 00 00 ef be ad 7e w4 s>>=0x7eadbeef 178: cc 65 00 00 00 00 00 00 w5 s>>=w6 180: 8c 32 00 00 00 00 00 00 w2=-w3 + 188: bc 21 08 00 00 00 00 00 w1 s= \(i8\) w2 + 190: bc 21 10 00 00 00 00 00 w1 s= \(i16\) w2 + 198: bc 21 20 00 00 00 00 00 w1 s= \(i32\) w2 diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/alu32-pseudoc.s index 0a0d41fdf46..5a0e442154f 100644 --- a/gas/testsuite/gas/bpf/alu32-pseudoc.s +++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s @@ -49,3 +49,6 @@ w4 s>>= 2125315823 w5 s>>= w6 w2 = - w3 + w1 s= (i8) w2 + w1 s= (i16) w2 + w1 s= (i32) w2 diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d index 712d1c7328e..68aa86fce09 100644 --- a/gas/testsuite/gas/bpf/alu32.d +++ b/gas/testsuite/gas/bpf/alu32.d @@ -57,3 +57,6 @@ Disassembly of section .text: 170: c4 04 00 00 ef be ad 7e arsh32 %r4,0x7eadbeef 178: cc 65 00 00 00 00 00 00 arsh32 %r5,%r6 180: 8c 32 00 00 00 00 00 00 neg32 %r2,%r3 + 188: bc 21 08 00 00 00 00 00 movs32 %r1,%r2,8 + 190: bc 21 10 00 00 00 00 00 movs32 %r1,%r2,16 + 198: bc 21 20 00 00 00 00 00 movs32 %r1,%r2,32 diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s index f43ea4a4d23..14f0a12de2c 100644 --- a/gas/testsuite/gas/bpf/alu32.s +++ b/gas/testsuite/gas/bpf/alu32.s @@ -49,3 +49,6 @@ arsh32 %r4, 0x7eadbeef arsh32 %r5, %r6 neg32 %r2, %r3 + movs32 %r1,%r2,8 + movs32 %r1,%r2,16 + movs32 %r1,%r2,32 diff --git a/include/ChangeLog b/include/ChangeLog index f0c8fe875ea..5872f284533 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,11 @@ +2023-07-21 Jose E. Marchesi + + * opcode/bpf.h (BPF_OFFSET16_MOVS8): Define. + (BPF_OFFSET16_MOVS16): Likewise. + (BPF_OFFSET16_MOVS32): Likewise. + (enum bpf_insn_id): Add entries for MOVS{8,16,32}R and + MOVS32{8,16,32}R. + 2023-07-03 Nick Clifton 2.41 Branch Point. diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h index f928979f86f..48f06c264ba 100644 --- a/include/opcode/bpf.h +++ b/include/opcode/bpf.h @@ -131,6 +131,9 @@ typedef uint64_t bpf_insn_word; even if these are multi-byte or infra-byte. Bleh. */ #define BPF_OFFSET16_SDIVMOD ((uint64_t)0x1 << 32) +#define BPF_OFFSET16_MOVS8 ((uint64_t)8 << 32) +#define BPF_OFFSET16_MOVS16 ((uint64_t)16 << 32) +#define BPF_OFFSET16_MOVS32 ((uint64_t)32 << 32) #define BPF_IMM32_END16 ((uint64_t)0x00000010) #define BPF_IMM32_END32 ((uint64_t)0x00000020) @@ -162,6 +165,7 @@ enum bpf_insn_id BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI, BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI, BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI, + BPF_INSN_MOVS8R, BPF_INSN_MOVS16R, BPF_INSN_MOVS32R, BPF_INSN_MOVR, BPF_INSN_MOVI, /* ALU32 instructions. */ BPF_INSN_ADD32R, BPF_INSN_ADD32I, BPF_INSN_SUB32R, BPF_INSN_SUB32I, @@ -171,6 +175,7 @@ enum bpf_insn_id BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I, BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I, BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I, + BPF_INSN_MOVS328R, BPF_INSN_MOVS3216R, BPF_INSN_MOVS3232R, BPF_INSN_MOV32R, BPF_INSN_MOV32I, /* Endianness conversion instructions. */ BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f202d1941bc..55d4e7d657f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2023-07-21 Jose E. Marchesi + + * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and + MOVS32{8,16,32}R instructions. and MOVS32I instructions. + 2023-07-21 Jose E. Marchesi * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c index f89d93a5c78..72be1d956d5 100644 --- a/opcodes/bpf-opc.c +++ b/opcodes/bpf-opc.c @@ -89,6 +89,12 @@ const struct bpf_opcode bpf_opcodes[] = BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X}, {BPF_INSN_ARSHI, "arsh%W%dr , %i32", "%dr%ws>>= %i32", BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K}, + {BPF_INSN_MOVS8R, "movs%W%dr , %sr , 8", "%dr%ws=%w( i8 )%w%sr", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8}, + {BPF_INSN_MOVS16R, "movs%W%dr , %sr , 16", "%dr%ws=%w( i16 )%w%sr", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16}, + {BPF_INSN_MOVS32R, "movs%W%dr , %sr , 32", "%dr%ws=%w( i32 )%w%sr", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32}, {BPF_INSN_MOVR, "mov%W%dr , %sr", "%dr = %sr", BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X}, {BPF_INSN_MOVI, "mov%W%dr , %i32", "%dr = %i32", @@ -151,6 +157,12 @@ const struct bpf_opcode bpf_opcodes[] = BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X}, {BPF_INSN_ARSH32I, "arsh32%W%dr , %i32", "%dw%Ws>>= %i32", BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K}, + {BPF_INSN_MOVS328R, "movs32%W%dr , %sr , 8", "%dw%ws=%w( i8 )%w%sw", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS8}, + {BPF_INSN_MOVS3216R, "movs32%W%dr , %sr , 16", "%dw%ws=%w( i16 )%w%sw", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS16}, + {BPF_INSN_MOVS3232R, "movs32%W%dr , %sr , 32", "%dw%ws=%w( i32 )%w%sw", + BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X|BPF_OFFSET16_MOVS32}, {BPF_INSN_MOV32R, "mov32%W%dr , %sr", "%dw = %sw", BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X}, {BPF_INSN_MOV32I, "mov32%W%dr , %i32", "%dw = %i32",