diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 1b9a801966c..ba7440c2768 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -7148,6 +7148,7 @@ assembler and not (currently) written to any object files.  */
 /* Linux eBPF relocations.  */
   BFD_RELOC_BPF_64,
   BFD_RELOC_BPF_DISP32,
+  BFD_RELOC_BPF_DISP16,
 
 /* Adapteva EPIPHANY - 8 bit signed pc-relative displacement  */
   BFD_RELOC_EPIPHANY_SIMM8,
diff --git a/bfd/bpf-reloc.def b/bfd/bpf-reloc.def
index b1be2eb66f6..31f761d291d 100644
--- a/bfd/bpf-reloc.def
+++ b/bfd/bpf-reloc.def
@@ -72,3 +72,18 @@
         0xffffffff,            /* src_mask */
         0xffffffff,            /* dst_mask */
         true)                  /* pcrel_offset */
+
+  /* 16-bit PC-relative address in load instructions.  */
+  BPF_HOWTO (R_BPF_GNU_64_16,      /* type */
+        0,                     /* rightshift */
+        2,                     /* size */
+        16,                    /* bitsize */
+        true,                  /* pc_relative */
+        16,                    /* bitpos */
+        complain_overflow_signed, /* complain_on_overflow */
+        bpf_elf_generic_reloc, /* special_function */
+        "R_BPF_GNU_64_16",     /* name */
+        true,                  /* partial_inplace */
+        0xffff,                /* src_mask */
+        0xffff,                /* dst_mask */
+        true)                  /* pcrel_offset */
diff --git a/bfd/elf64-bpf.c b/bfd/elf64-bpf.c
index 65418d1d740..23ede4e5d96 100644
--- a/bfd/elf64-bpf.c
+++ b/bfd/elf64-bpf.c
@@ -89,6 +89,8 @@ bpf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
       return &bpf_elf_howto_table[ (int) R_BPF_64_64_IDX];
     case BFD_RELOC_BPF_DISP32:
       return &bpf_elf_howto_table[ (int) R_BPF_64_32_IDX];
+    case BFD_RELOC_BPF_DISP16:
+      return &bpf_elf_howto_table[ (int) R_BPF_GNU_64_16_IDX];
 
     default:
       /* Pacify gcc -Wall.  */
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index d4fb3107597..5dbb0871607 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -3346,6 +3346,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
   "BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD",
   "BFD_RELOC_BPF_64",
   "BFD_RELOC_BPF_DISP32",
+  "BFD_RELOC_BPF_DISP16",
   "BFD_RELOC_EPIPHANY_SIMM8",
   "BFD_RELOC_EPIPHANY_SIMM24",
   "BFD_RELOC_EPIPHANY_HIGH",
diff --git a/bfd/reloc.c b/bfd/reloc.c
index fbc67ac7280..e71a510e26c 100644
--- a/bfd/reloc.c
+++ b/bfd/reloc.c
@@ -7753,6 +7753,8 @@ ENUM
   BFD_RELOC_BPF_64
 ENUMX
   BFD_RELOC_BPF_DISP32
+ENUMX
+  BFD_RELOC_BPF_DISP16
 ENUMDOC
   Linux eBPF relocations.
 
diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c
index 3b86f9c89cb..7a54faccb59 100644
--- a/gas/config/tc-bpf.c
+++ b/gas/config/tc-bpf.c
@@ -22,42 +22,42 @@
 #include "as.h"
 #include "subsegs.h"
 #include "symcat.h"
-#include "opcodes/bpf-desc.h"
-#include "opcodes/bpf-opc.h"
-#include "cgen.h"
+#include "opcode/bpf.h"
 #include "elf/common.h"
 #include "elf/bpf.h"
 #include "dwarf2dbg.h"
+#include "libiberty.h"
 #include <ctype.h>
 
+/* Data structure representing a parsed BPF instruction.  */
+
+struct bpf_insn
+{
+  int size; /* Instruction size in bytes.  */
+  bpf_insn_word opcode;
+  uint8_t dst;
+  uint8_t src;
+  expressionS offset16;
+  expressionS imm32;
+  expressionS imm64;
+  expressionS disp16;
+  expressionS disp32;
+
+  unsigned int has_dst : 1;
+  unsigned int has_src : 1;
+  unsigned int has_offset16 : 1;
+  unsigned int has_disp16 : 1;
+  unsigned int has_disp32 : 1;
+  unsigned int has_imm32 : 1;
+  unsigned int has_imm64 : 1;
+};
+
 const char comment_chars[]        = ";";
 const char line_comment_chars[]   = "#";
 const char line_separator_chars[] = "`";
 const char EXP_CHARS[]            = "eE";
 const char FLT_CHARS[]            = "fFdD";
 
-static const char *invalid_expression;
-static char pseudoc_lex[256];
-static const char symbol_chars[] =
-"_ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789";
-
-static const char arithm_op[] = "+-/<>%&|^";
-
-static void init_pseudoc_lex (void);
-
-#define LEX_IS_SYMBOL_COMPONENT  1
-#define LEX_IS_WHITESPACE        2
-#define LEX_IS_NEWLINE           3
-#define LEX_IS_ARITHM_OP         4
-#define LEX_IS_STAR              6
-#define LEX_IS_CLSE_BR           7
-#define LEX_IS_OPEN_BR           8
-#define LEX_IS_EQUAL             9
-#define LEX_IS_EXCLA             10
-
-#define ST_EOI        100
-#define MAX_TOKEN_SZ  100
-
 /* Like s_lcomm_internal in gas/read.c but the alignment string
    is allowed to be optional.  */
 
@@ -110,18 +110,15 @@ const pseudo_typeS md_pseudo_table[] =
 
 
 
-/* ISA handling.  */
-static CGEN_BITSET *bpf_isa;
-
-
-
 /* Command-line options processing.  */
 
 enum options
 {
   OPTION_LITTLE_ENDIAN = OPTION_MD_BASE,
   OPTION_BIG_ENDIAN,
-  OPTION_XBPF
+  OPTION_XBPF,
+  OPTION_DIALECT,
+  OPTION_ISA_SPEC,
 };
 
 struct option md_longopts[] =
@@ -129,6 +126,8 @@ struct option md_longopts[] =
   { "EL", no_argument, NULL, OPTION_LITTLE_ENDIAN },
   { "EB", no_argument, NULL, OPTION_BIG_ENDIAN },
   { "mxbpf", no_argument, NULL, OPTION_XBPF },
+  { "mdialect", required_argument, NULL, OPTION_DIALECT},
+  { "misa-spec", required_argument, NULL, OPTION_ISA_SPEC},
   { NULL,          no_argument, NULL, 0 },
 };
 
@@ -136,18 +135,34 @@ size_t md_longopts_size = sizeof (md_longopts);
 
 const char * md_shortopts = "";
 
-extern int target_big_endian;
+/* BPF supports little-endian and big-endian variants.  The following
+   global records what endianness to use.  It can be configured using
+   command-line options.  It defaults to the host endianness
+   initialized in md_begin.  */
 
-/* Whether target_big_endian has been set while parsing command-line
-   arguments.  */
 static int set_target_endian = 0;
+extern int target_big_endian;
+
+/* The ISA specification can be one of BPF_V1, BPF_V2, BPF_V3, BPF_V4
+   or BPF_XPBF.  The ISA spec to use can be configured using
+   command-line options.  It defaults to the latest BPF spec.  */
+
+static int isa_spec = BPF_V4;
 
-static int target_xbpf = 0;
+/* The assembler supports two different dialects: "normal" syntax and
+   "pseudoc" syntax.  The dialect to use can be configured using
+   command-line options.  */
 
-static int set_xbpf = 0;
+enum target_asm_dialect
+{
+  DIALECT_NORMAL,
+  DIALECT_PSEUDOC
+};
+
+static int asm_dialect = DIALECT_NORMAL;
 
 int
-md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+md_parse_option (int c, const char * arg)
 {
   switch (c)
     {
@@ -156,12 +171,36 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
       target_big_endian = 1;
       break;
     case OPTION_LITTLE_ENDIAN:
-      set_target_endian = 1;
+      set_target_endian = 0;
       target_big_endian = 0;
       break;
+    case OPTION_DIALECT:
+      if (strcmp (arg, "normal") == 0)
+        asm_dialect = DIALECT_NORMAL;
+      else if (strcmp (arg, "pseudoc") == 0)
+        asm_dialect = DIALECT_PSEUDOC;
+      else
+        as_fatal (_("-mdialect=%s is not valid.  Expected normal or pseudoc"),
+                  arg);
+      break;
+    case OPTION_ISA_SPEC:
+      if (strcmp (arg, "v1") == 0)
+        isa_spec = BPF_V1;
+      else if (strcmp (arg, "v2") == 0)
+        isa_spec = BPF_V2;
+      else if (strcmp (arg, "v3") == 0)
+        isa_spec = BPF_V3;
+      else if (strcmp (arg, "v4") == 0)
+        isa_spec = BPF_V4;
+      else if (strcmp (arg, "xbpf") == 0)
+        isa_spec = BPF_XBPF;
+      else
+        as_fatal (_("-misa-spec=%s is not valid.  Expected v1, v2, v3, v4 o xbpf"),
+                  arg);
+      break;
     case OPTION_XBPF:
-      set_xbpf = 1;
-      target_xbpf = 1;
+      /* This is an alias for -misa-spec=xbpf.  */
+      isa_spec = BPF_XBPF;
       break;
     default:
       return 0;
@@ -175,43 +214,22 @@ md_show_usage (FILE * stream)
 {
   fprintf (stream, _("\nBPF options:\n"));
   fprintf (stream, _("\
-  --EL			generate code for a little endian machine\n\
-  --EB			generate code for a big endian machine\n\
-  -mxbpf                generate xBPF instructions\n"));
+BPF options:\n\
+  -EL                         generate code for a little endian machine\n\
+  -EB                         generate code for a big endian machine\n\
+  -mdialect=DIALECT           set the assembly dialect (normal, pseudoc)\n\
+  -misa-spec                  set the BPF ISA spec (v1, v2, v3, v4, xbpf)\n\
+  -mxbpf                      alias for -misa-spec=xbpf\n"));
 }
 
 
-
-static void
-init_pseudoc_lex (void)
-{
-  const char *p;
-
-  for (p = symbol_chars; *p; ++p)
-    pseudoc_lex[(unsigned char) *p] = LEX_IS_SYMBOL_COMPONENT;
-
-  pseudoc_lex[' '] = LEX_IS_WHITESPACE;
-  pseudoc_lex['\t'] = LEX_IS_WHITESPACE;
-  pseudoc_lex['\r'] = LEX_IS_WHITESPACE;
-  pseudoc_lex['\n'] = LEX_IS_NEWLINE;
-  pseudoc_lex['*'] = LEX_IS_STAR;
-  pseudoc_lex[')'] = LEX_IS_CLSE_BR;
-  pseudoc_lex['('] = LEX_IS_OPEN_BR;
-  pseudoc_lex[']'] = LEX_IS_CLSE_BR;
-  pseudoc_lex['['] = LEX_IS_OPEN_BR;
-
-  for (p = arithm_op; *p; ++p)
-    pseudoc_lex[(unsigned char) *p] = LEX_IS_ARITHM_OP;
-
-  pseudoc_lex['='] = LEX_IS_EQUAL;
-  pseudoc_lex['!'] = LEX_IS_EXCLA;
-}
+/* This function is called once, at assembler startup time.  This
+   should set up all the tables, etc that the MD part of the assembler
+   needs.  */
 
 void
 md_begin (void)
 {
-  /* Initialize the `cgen' interface.  */
-
   /* If not specified in the command line, use the host
      endianness.  */
   if (!set_target_endian)
@@ -223,50 +241,15 @@ md_begin (void)
 #endif
     }
 
-  /* If not specified in the command line, use eBPF rather
-     than xBPF.  */
-  if (!set_xbpf)
-      target_xbpf = 0;
-
-  /* Set the ISA, which depends on the target endianness. */
-  bpf_isa = cgen_bitset_create (ISA_MAX);
-  if (target_big_endian)
-    {
-      if (target_xbpf)
-	cgen_bitset_set (bpf_isa, ISA_XBPFBE);
-      else
-	cgen_bitset_set (bpf_isa, ISA_EBPFBE);
-    }
-  else
-    {
-      if (target_xbpf)
-	cgen_bitset_set (bpf_isa, ISA_XBPFLE);
-      else
-	cgen_bitset_set (bpf_isa, ISA_EBPFLE);
-    }
-
   /* Ensure that lines can begin with '*' in BPF store pseudoc instruction.  */
   lex_type['*'] |= LEX_BEGIN_NAME;
 
-  /* Set the machine number and endian.  */
-  gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN,
-                                         target_big_endian ?
-                                         CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE,
-                                         CGEN_CPU_OPEN_INSN_ENDIAN,
-                                         CGEN_ENDIAN_LITTLE,
-                                         CGEN_CPU_OPEN_ISAS,
-                                         bpf_isa,
-                                         CGEN_CPU_OPEN_END);
-  bpf_cgen_init_asm (gas_cgen_cpu_desc);
-
-  /* This is a callback from cgen to gas to parse operands.  */
-  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
-
   /* Set the machine type. */
   bfd_default_set_arch_mach (stdoutput, bfd_arch_bpf, bfd_mach_bpf);
-  init_pseudoc_lex();
 }
 
+/* Round up a section size to the appropriate boundary.  */
+
 valueT
 md_section_align (segT segment, valueT size)
 {
@@ -310,33 +293,48 @@ md_number_to_chars (char * buf, valueT val, int n)
 }
 
 arelent *
-tc_gen_reloc (asection *sec, fixS *fix)
+tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixP)
 {
-  return gas_cgen_tc_gen_reloc (sec, fix);
-}
+  bfd_reloc_code_real_type r_type = fixP->fx_r_type;
+  arelent *reloc;
 
-/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.  This
-   is called when the operand is an expression that couldn't be fully
-   resolved.  Returns BFD_RELOC_NONE if no reloc type can be found.
-   *FIXP may be modified if desired.  */
+  reloc = XNEW (arelent);
 
-bfd_reloc_code_real_type
-md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
-		      const CGEN_OPERAND *operand,
-		      fixS *fixP)
-{
-  switch (operand->type)
+  if (fixP->fx_pcrel)
+   {
+      r_type = (r_type == BFD_RELOC_8 ? BFD_RELOC_8_PCREL
+                : r_type == BFD_RELOC_16 ? BFD_RELOC_16_PCREL
+                : r_type == BFD_RELOC_24 ? BFD_RELOC_24_PCREL
+                : r_type == BFD_RELOC_32 ? BFD_RELOC_32_PCREL
+                : r_type == BFD_RELOC_64 ? BFD_RELOC_64_PCREL
+                : r_type);
+   }
+
+  reloc->howto = bfd_reloc_type_lookup (stdoutput, r_type);
+
+  if (reloc->howto == (reloc_howto_type *) NULL)
     {
-    case BPF_OPERAND_IMM64:
-      return BFD_RELOC_BPF_64;
-    case BPF_OPERAND_DISP32:
-      fixP->fx_pcrel = 1;
-      return BFD_RELOC_BPF_DISP32;
-    default:
-      break;
+      as_bad_where (fixP->fx_file, fixP->fx_line,
+		    _("relocation is not supported"));
+      return NULL;
     }
-  return BFD_RELOC_NONE;
+
+  //XXX  gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
+
+  reloc->sym_ptr_ptr = XNEW (asymbol *);
+  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
+
+  /* Use fx_offset for these cases.  */
+  if (fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
+      || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT)
+    reloc->addend = fixP->fx_offset;
+  else
+    reloc->addend = fixP->fx_addnumber;
+
+  reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
+  return reloc;
 }
+
 
 /* *FRAGP has been relaxed to its final size, and now needs to have
    the bytes inside it modified to conform to the new size.
@@ -362,1556 +360,821 @@ md_estimate_size_before_relax (fragS *fragP ATTRIBUTE_UNUSED,
 }
 
 
+/* Apply a fixS (fixup of an instruction or data that we didn't have
+   enough info to complete immediately) to the data in a frag.  */
+
 void
-md_apply_fix (fixS *fixP, valueT *valP, segT seg)
+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 {
-  /* Some fixups for instructions require special attention.  This is
-     handled in the code block below.  */
-  if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+  char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  switch (fixP->fx_r_type)
     {
-      int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
-      const CGEN_OPERAND *operand = cgen_operand_lookup_by_num (gas_cgen_cpu_desc,
-                                                                opindex);
-      char *where;
+    case BFD_RELOC_BPF_DISP16:
+      /* Convert from bytes to number of 64-bit words to the target,
+         minus one.  */
+      *valP = (((long) (*valP)) - 8) / 8;
+      break;
+    case BFD_RELOC_BPF_DISP32:
+      /* eBPF supports two kind of CALL instructions: the so called
+         pseudo calls ("bpf to bpf") and external calls ("bpf to
+         kernel").
+
+         Both kind of calls use the same instruction (CALL).  However,
+         external calls are constructed by passing a constant argument
+         to the instruction, whereas pseudo calls result from
+         expressions involving symbols.  In practice, instructions
+         requiring a fixup are interpreted as pseudo-calls.  If we are
+         executing this code, this is a pseudo call.
+
+         The kernel expects for pseudo-calls to be annotated by having
+         BPF_PSEUDO_CALL in the SRC field of the instruction.  But
+         beware the infamous nibble-swapping of eBPF and take
+         endianness into account here.
+
+         Note that the CALL instruction has only one operand, so
+         this code is executed only once per instruction.  */
+      md_number_to_chars (where + 1, target_big_endian ? 0x01 : 0x10, 1);
+
+      /* Convert from bytes to number of 64-bit words to the target,
+         minus one.  */
+      *valP = (((long) (*valP)) - 8) / 8;
+      break;
+    case BFD_RELOC_16_PCREL:
+      /* Convert from bytes to number of 64-bit words to the target,
+         minus one.  */
+      *valP = (((long) (*valP)) - 8) / 8;
+      break;
+    default:
+      break;
+    }
 
-      switch (operand->type)
-        {
-        case BPF_OPERAND_DISP32:
-          /* eBPF supports two kind of CALL instructions: the so
-             called pseudo calls ("bpf to bpf") and external calls
-             ("bpf to kernel").
-
-             Both kind of calls use the same instruction (CALL).
-             However, external calls are constructed by passing a
-             constant argument to the instruction, whereas pseudo
-             calls result from expressions involving symbols.  In
-             practice, instructions requiring a fixup are interpreted
-             as pseudo-calls.  If we are executing this code, this is
-             a pseudo call.
-
-             The kernel expects for pseudo-calls to be annotated by
-             having BPF_PSEUDO_CALL in the SRC field of the
-             instruction.  But beware the infamous nibble-swapping of
-             eBPF and take endianness into account here.
-
-             Note that the CALL instruction has only one operand, so
-             this code is executed only once per instruction.  */
-          where = fixP->fx_frag->fr_literal + fixP->fx_where + 1;
-          where[0] = target_big_endian ? 0x01 : 0x10;
-          /* Fallthrough.  */
-        case BPF_OPERAND_DISP16:
-          /* The PC-relative displacement fields in jump instructions
-             shouldn't be in bytes.  Instead, they hold the number of
-             64-bit words to the target, _minus one_.  */ 
-          *valP = (((long) (*valP)) - 8) / 8;
+  if (fixP->fx_addsy == (symbolS *) NULL)
+    fixP->fx_done = 1;
+
+  if (fixP->fx_done)
+    {
+      /* We're finished with this fixup.  Install it because
+	 bfd_install_relocation won't be called to do it.  */
+      switch (fixP->fx_r_type)
+	{
+	case BFD_RELOC_8:
+	  md_number_to_chars (where, *valP, 1);
+	  break;
+	case BFD_RELOC_16:
+	  md_number_to_chars (where, *valP, 2);
+	  break;
+	case BFD_RELOC_32:
+	  md_number_to_chars (where, *valP, 4);
+	  break;
+	case BFD_RELOC_64:
+	  md_number_to_chars (where, *valP, 8);
+	  break;
+        case BFD_RELOC_BPF_DISP16:
+          md_number_to_chars (where + 2, (uint16_t) *valP, 2);
           break;
-        default:
+        case BFD_RELOC_BPF_DISP32:
+          md_number_to_chars (where + 4, (uint32_t) *valP, 4);
           break;
-        }
+        case BFD_RELOC_16_PCREL:
+          md_number_to_chars (where + 2, (uint32_t) *valP, 2);
+          break;
+	default:
+	  as_bad_where (fixP->fx_file, fixP->fx_line,
+			_("internal error: can't install fix for reloc type %d (`%s')"),
+			fixP->fx_r_type, bfd_get_reloc_code_name (fixP->fx_r_type));
+	  break;
+	}
     }
 
-  /* And now invoke CGEN's handler, which will eventually install
-     *valP into the corresponding operand.  */
-  gas_cgen_md_apply_fix (fixP, valP, seg);
+  /* Tuck `value' away for use by tc_gen_reloc.
+     See the comment describing fx_addnumber in write.h.
+     This field is misnamed (or misused :-).  */
+  fixP->fx_addnumber = *valP;
 }
 
-/*
-  The BPF pseudo grammar:
-
-	instruction  : bpf_alu_insn
-		     | bpf_alu32_insn
-		     | bpf_jump_insn
-		     | bpf_load_store_insn
-		     | bpf_load_store32_insn
-		     | bpf_non_generic_load
-		     | bpf_endianness_conv_insn
-		     | bpf_64_imm_load_insn
-		     | bpf_atomic_insn
-		     ;
-
-	bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32
-		     ;
-
-	bpf_alu32_insn : BPF_REG32 bpf_alu_operator register32_or_imm32
-		       ;
-
-	bpf_jump_insn  : BPF_JA offset
-		       | IF BPF_REG bpf_jump_operator register_or_imm32 BPF_JA offset
-		       | IF BPF_REG32 bpf_jump_operator register_or_imm32 BPF_JA offset
-		       | BPF_CALL offset
-		       | BPF_EXIT
-		       ;
-
-	bpf_load_store_insn  : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \
-			       register_and_offset BPF_CHR_CLSE_BR
-			     | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG
-			     ;
-
-	bpf_load_store32_insn  : BPF_REG CHR_EQUAL bpf_size_cast BPF_CHR_OPEN_BR \
-				 register32_and_offset BPF_CHR_CLSE_BR
-			       | bpf_size_cast register_and_offset CHR_EQUAL BPF_REG32
-			     ;
-
-	bpf_non_generic_load : BPF_REG_R0 CHR_EQUAL bpf_size_cast BPF_LD BPF_CHR_OPEN_BR \
-			       imm32 BPF_CHR_CLSE_BR
-			     ;
-
-	bpf_endianness_conv_insn : BPF_REG_N bpf_endianness_mnem BPF_REG_N
-				 ;
-
-	bpf_64_imm_load_insn : BPF_REG imm64 BPF_LL
-			     ;
-
-	bpf_atomic_insn : BPF_LOCK bpf_size_cast_32_64 register_and_offset BPF_ADD BPF_REG
-
-	register_and_offset : BPF_CHR_OPEN_BR BPF_REG offset BPF_CHR_CLSE_BR
-			    ;
-
-	register32_and_offset : BPF_CHR_OPEN_BR BPF_REG32 offset BPF_CHR_CLSE_BR
-			      ;
-
-	bpf_size_cast : CHR_START BPF_CHR_OPEN_BR bpf_size CHR_START BPF_CHR_CLSE_BR
-		      ;
-
-	bpf_size_cast_32_64 : CHR_START BPF_CHR_OPEN_BR bpf_size_cast_32_64 CHR_STAR BPF_CHR_CLSE_BR
-			    ;
-
-	bpf_size_32_64 : BPF_CAST_U32
-		       | BPF_CAST_U64
-		       ;
-
-	bpf_size  : BPF_CAST_U8
-		  | BPF_CAST_U16
-		  | BPF_CAST_U32
-		  | BPF_CAST_U64
-		  ;
-
-	bpf_jump_operator : BPF_JEQ
-			  | BPF_JGT
-			  | BPF_JGE
-			  | BPF_JNE
-			  | BPF_JSGT
-			  | BPF_JSGE
-			  | BPF_JLT
-			  | BPF_JLE
-			  | BPF_JSLT
-			  | BPF_JSLE
-			  ;
-
-	bpf_alu_operator : BPF_ADD
-			 | BPF_SUB
-			 | BPF_MUL
-			 | BPF_DIV
-			 | BPF_OR
-			 | BPF_AND
-			 | BPF_LSH
-			 | BPF_RSH
-			 | BPF_NEG
-			 | BPF_MOD
-			 | BPF_XOR
-			 | BPF_ARSH
-			 | CHR_EQUAL
-			 ;
-
-	bpf_endianness_mnem : BPF_LE16
-			    | BPF_LE32
-			    | BPF_LE64
-			    | BPF_BE16
-			    | BPF_BE32
-			    | BPF_BE64
-			    ;
-
-	offset : BPF_EXPR
-	       | BPF_SYMBOL
-	       ;
-
-	register_or_imm32 : BPF_REG
-			  | expression
-			  ;
-
-	register32_or_imm32 : BPF_REG32
-			    | expression
-			    ;
-
-	imm32 : BPF_EXPR
-	      | BPF_SYMBOL
-	      ;
-
-	imm64 : BPF_EXPR
-	      | BPF_SYMBOL
-	      ;
-
-	register_or_expression : BPF_EXPR
-			       | BPF_REG
-			       ;
-
-	BPF_EXPR : GAS_EXPR
-
-*/
-
-enum bpf_token_type
-  {
-    /* Keep grouped to quickly access. */
-    BPF_ADD,
-    BPF_SUB,
-    BPF_MUL,
-    BPF_DIV,
-    BPF_OR,
-    BPF_AND,
-    BPF_LSH,
-    BPF_RSH,
-    BPF_MOD,
-    BPF_XOR,
-    BPF_MOV,
-    BPF_ARSH,
-    BPF_NEG,
-
-    BPF_REG,
-
-    BPF_IF,
-    BPF_GOTO,
-
-    /* Keep grouped to quickly access.  */
-    BPF_JEQ,
-    BPF_JGT,
-    BPF_JGE,
-    BPF_JLT,
-    BPF_JLE,
-    BPF_JSET,
-    BPF_JNE,
-    BPF_JSGT,
-    BPF_JSGE,
-    BPF_JSLT,
-    BPF_JSLE,
-
-    BPF_SYMBOL,
-    BPF_CHR_CLSE_BR,
-    BPF_CHR_OPEN_BR,
-
-    /* Keep grouped to quickly access.  */
-    BPF_CAST_U8,
-    BPF_CAST_U16,
-    BPF_CAST_U32,
-    BPF_CAST_U64,
-
-    /* Keep grouped to quickly access.  */
-    BPF_LE16,
-    BPF_LE32,
-    BPF_LE64,
-    BPF_BE16,
-    BPF_BE32,
-    BPF_BE64,
-
-    BPF_LOCK,
-
-    BPF_IND_CALL,
-    BPF_LD,
-    BPF_LL,
-    BPF_EXPR,
-    BPF_UNKNOWN,
-  };
-
-static int
-valid_expr (const char *e, const char **end_expr)
-{
-  invalid_expression = NULL;
-  char *hold = input_line_pointer;
-  expressionS exp;
-
-  input_line_pointer = (char *) e;
-  deferred_expression  (&exp);
-  *end_expr = input_line_pointer;
-  input_line_pointer = hold;
+/* Parse an operand expression.  Returns the first character that is
+   not part of the expression, or NULL in case of parse error.
 
-  return invalid_expression == NULL;
-}
+   See md_operand below to see how exp_parse_failed is used.  */
 
-static char *
-build_bpf_non_generic_load (char *src, enum bpf_token_type cast,
-			    const char *imm32)
-{
-  char *bpf_insn;
-  static const char *cast_rw[] = {"b", "h", "w", "dw"};
-
-  bpf_insn = xasprintf ("%s%s%s %s%s%s%s",
-			"ld",
-			src ? "ind" : "abs",
-			cast_rw[cast - BPF_CAST_U8],
-			src ? "%" : "",
-			src ? src : "",
-			src ? "," : "",
-			imm32);
-  return bpf_insn;
-}
+static int exp_parse_failed = 0;
 
 static char *
-build_bpf_atomic_insn (char *dst, char *src,
-		       enum bpf_token_type atomic_insn,
-		       enum bpf_token_type cast,
-		       const char *offset)
+parse_expression (char *s, expressionS *exp)
 {
-  char *bpf_insn;
-  static const char *cast_rw[] = {"w", "dw"};
-  static const char *mnem[] = {"xadd"};
-
-  bpf_insn = xasprintf ("%s%s [%%%s%s%s],%%%s", mnem[atomic_insn - BPF_ADD],
-			cast_rw[cast - BPF_CAST_U32], dst,
-			*offset != '+' ? "+" : "",
-			offset, src);
-  return bpf_insn;
-}
+  char *saved_input_line_pointer = input_line_pointer;
+  char *saved_s = s;
 
-static char *
-build_bpf_jmp_insn (char *dst, char *src,
-		    char *imm32, enum bpf_token_type op,
-		    const char *sym, const char *offset)
-{
-  char *bpf_insn;
-  static const char *mnem[] =
-    {
-      "jeq", "jgt", "jge", "jlt",
-      "jle", "jset", "jne", "jsgt",
-      "jsge", "jslt", "jsle"
-    };
-
-  const char *in32 = (*dst == 'w' ? "32" : "");
-
-  *dst = 'r';
-  if (src)
-    *src = 'r';
-
-  bpf_insn = xasprintf ("%s%s %%%s,%s%s,%s",
-			mnem[op - BPF_JEQ], in32, dst,
-			src ? "%" : "",
-			src ? src : imm32,
-			offset ? offset : sym);
-  return bpf_insn;
-}
+  exp_parse_failed = 0;
+  input_line_pointer = s;
+  expression (exp);
+  s = input_line_pointer;
+  input_line_pointer = saved_input_line_pointer;
 
-static char *
-build_bpf_arithm_insn (char *dst, char *src,
-		       int load64, const char *imm32,
-		       enum bpf_token_type type)
-{
-  char *bpf_insn;
-  static const char *mnem[] =
-    {
-      "add", "sub", "mul", "div",
-      "or", "and", "lsh", "rsh",
-      "mod", "xor", "mov", "arsh",
-      "neg",
-    };
-  const char *in32 = (*dst == 'w' ? "32" : "");
-
-  *dst = 'r';
-  if (src)
-    *src = 'r';
-
-  if (type == BPF_NEG)
-    bpf_insn = xasprintf ("%s%s %%%s", mnem[type - BPF_ADD], in32, dst);
-  else if (load64)
-    bpf_insn = xasprintf ("%s %%%s,%s", "lddw", dst, imm32);
-  else
-    bpf_insn = xasprintf ("%s%s %%%s,%s%s", mnem[type - BPF_ADD],
-			  in32, dst,
-			  src ? "%" : "",
-			  src ? src: imm32);
-  return bpf_insn;
-}
+  switch (exp->X_op == O_absent || exp_parse_failed)
+    return NULL;
 
-static char *
-build_bpf_endianness (char *dst, enum bpf_token_type endianness)
-{
-  char *bpf_insn;
-  static const char *size[] = {"16", "32", "64"};
-  int be = 1;
-
-  if (endianness == BPF_LE16
-      || endianness == BPF_LE32
-      || endianness == BPF_LE64)
-    be = 0;
-  else
-    gas_assert (endianness == BPF_BE16 || endianness == BPF_BE32 || endianness == BPF_BE64);
+  /* The expression parser may consume trailing whitespaces.  We have
+     to undo that since the instruction templates may be expecting
+     these whitespaces.  */
+  {
+    char *p;
+    for (p = s - 1; p >= saved_s && *p == ' '; --p)
+      --s;
+  }
 
-  bpf_insn = xasprintf ("%s %%%s,%s", be ? "endbe" : "endle",
-			dst, be ? size[endianness - BPF_BE16] : size[endianness - BPF_LE16]);
-  return bpf_insn;
+  return s;
 }
 
-static char *
-build_bpf_load_store_insn (char *dst, char *src,
-			   enum bpf_token_type cast,
-			   const char *offset, int isload)
-{
-  char *bpf_insn;
-  static const char *cast_rw[] = {"b", "h", "w", "dw"};
-
-  *dst = *src = 'r';
-  if (isload)
-    bpf_insn = xasprintf ("%s%s %%%s,[%%%s%s%s]", "ldx",
-			  cast_rw[cast - BPF_CAST_U8], dst, src,
-			  *offset != '+' ? "+" : "",
-			  offset);
-  else
-    bpf_insn = xasprintf ("%s%s [%%%s%s%s],%%%s", "stx",
-			  cast_rw[cast - BPF_CAST_U8], dst,
-			  *offset != '+' ? "+" : "",
-			  offset, src);
-  return bpf_insn;
-}
+/* Parse a BPF register name and return the corresponding register
+   number.  Return NULL in case of parse error, or a pointer to the
+   first character in S that is not part of the register name.  */
 
-static int
-look_for_reserved_word (const char *token, enum bpf_token_type *type)
+static char *
+parse_bpf_register (char *s, char rw, uint8_t *regno)
 {
-  int i;
-  static struct
-  {
-    const char *name;
-    enum bpf_token_type type;
-  } reserved_words[] =
+  if (asm_dialect == DIALECT_NORMAL)
     {
-      {
-	.name = "if",
-	.type = BPF_IF
-      },
-      {
-	.name = "goto",
-	.type = BPF_GOTO
-      },
-      {
-	.name = "le16",
-	.type = BPF_LE16
-      },
-      {
-	.name = "le32",
-	.type = BPF_LE32
-      },
-      {
-	.name = "le64",
-	.type = BPF_LE64
-      },
-      {
-	.name = "be16",
-	.type = BPF_BE16
-      },
-      {
-	.name = "be32",
-	.type = BPF_BE32
-      },
-      {
-	.name = "be64",
-	.type = BPF_BE64
-	},
-      {
-	.name = "lock",
-	.type = BPF_LOCK
-      },
-      {
-	.name = "callx",
-	.type = BPF_IND_CALL
-      },
-      {
-	.name = "skb",
-	.type = BPF_LD
-      },
-      {
-	.name = "ll",
-	.type = BPF_LL
-      },
-      {
-	.name = NULL,
-      }
-    };
+      rw = 'r';
+      if (*s != '%')
+	return NULL;
+      s += 1;
 
-  for (i = 0; reserved_words[i].name; ++i)
-    if (*reserved_words[i].name == *token
-	&& !strcmp (reserved_words[i].name, token))
-      {
-	*type = reserved_words[i].type;
-	return 1;
-      }
+      if (*s == 'f' && *(s + 1) == 'p')
+	{
+	  *regno = 10;
+	  s += 2;
+	  return s;
+	}
+    }
 
-  return 0;
-}
+  if (*s != rw)
+    return NULL;
+  s += 1;
 
-static int
-is_register (const char *token, int len)
-{
-  if (token[0] == 'r' || token[0] == 'w')
-    if ((len == 2 && isdigit (token[1]))
-	|| (len == 3 && token[1] == '1' && token[2] == '0'))
-      return 1;
+  if (*s == '1')
+    {
+      if (*(s + 1) == '0')
+        {
+          *regno = 10;
+          s += 2;
+        }
+      else
+        {
+          *regno = 1;
+          s += 1;
+        }
+    }
+  else if (*s >= '0' && *s <= '9')
+    {
+      *regno = *s - '0';
+      s += 1;
+    }
 
-  return 0;
+  return s;
 }
 
-static enum bpf_token_type
-is_cast (const char *token)
-{
-  static const char *cast_rw[] = {"u8", "u16", "u32", "u64"};
-  unsigned int i;
-
-  for (i = 0; i < ARRAY_SIZE (cast_rw); ++i)
-    if (!strcmp (token, cast_rw[i]))
-      return BPF_CAST_U8 + i;
+/* Collect a parse error message.  */
 
-  return BPF_UNKNOWN;
-}
+static int partial_match_length = 0;
+static char *errmsg = NULL;
 
-static enum bpf_token_type
-get_token (const char **insn, char *token, size_t *tlen)
+static void
+parse_error (int length, const char *fmt, ...)
 {
-#define GET()					\
-  (*str == '\0'					\
-   ? EOF					\
-   : *(unsigned char *)(str++))
-
-#define UNGET() (--str)
-
-#define START_EXPR()			       \
-  do					       \
-    {					       \
-      if (expr == NULL)			       \
-	expr = str - 1;			       \
-    } while (0)
-
-#define SCANNER_SKIP_WHITESPACE()		\
-  do						\
-    {						\
-      do					\
-	ch = GET ();				\
-      while (ch != EOF				\
-	     && ((ch) == ' ' || (ch) == '\t'));	\
-      if (ch != EOF)				\
-	UNGET ();				\
-    } while (0)
-
-  const char *str = *insn;
-  int ch, ch2 = 0;
-  enum bpf_token_type ttype = BPF_UNKNOWN;
-  size_t len = 0;
-  const char *expr = NULL;
-  const char *end_expr = NULL;
-  int state = 0;
-  int return_token = 0;
-
-  while (1)
+  if (length > partial_match_length)
     {
-      ch = GET ();
-
-      if (ch == EOF || len > MAX_TOKEN_SZ)
-	break;
-
-      switch (pseudoc_lex[(unsigned char) ch])
-	{
-	case LEX_IS_WHITESPACE:
-	  SCANNER_SKIP_WHITESPACE ();
-	  return_token = 1;
-
-	  switch (state)
-	    {
-	    case 12: /* >' ' */
-	      ttype = BPF_JGT;
-	      break;
-
-	    case 17: /* ==' ' */
-	      ttype = BPF_JEQ;
-	      break;
-
-	    case 18: /* <' ' */
-	      ttype = BPF_JLT;
-	      break;
-
-	    case 20: /* &' ' */
-	      ttype = BPF_JSET;
-	      break;
-
-	    case 22:  /* s<' '*/
-	      ttype = BPF_JSLT;
-	      break;
-
-	    case 14: /* s> ' ' */
-	      ttype = BPF_JSGT;
-	      break;
-
-	    case 16: /* =' ' */
-	      ttype = BPF_MOV;
-	      break;
-
-	    default:
-	      return_token = 0;
-	    }
-	  break;
-
-	case LEX_IS_EXCLA:
-	  token[len++] = ch;
-	  state = 21;
-	  break;
-
-	case LEX_IS_ARITHM_OP:
-	  if (state == 16)
-	    {
-	      /* ='-' is handle as '=' */
-	      UNGET ();
-	      ttype = BPF_MOV;
-	      return_token = 1;
-	      break;
-	    }
-
-	  START_EXPR();
-	  token[len++] = ch;
-	  switch (ch)
-	    {
-#define BPF_ARITHM_OP(op, type)			\
-	      case (op):			\
-		state = 6;			\
-		ttype = (type);			\
-		break;
-
-	      BPF_ARITHM_OP('+', BPF_ADD);
-	      BPF_ARITHM_OP('-', BPF_SUB);
-	      BPF_ARITHM_OP('*', BPF_MUL);
-	      BPF_ARITHM_OP('/', BPF_DIV);
-	      BPF_ARITHM_OP('|', BPF_OR);
-	      BPF_ARITHM_OP('%', BPF_MOD);
-	      BPF_ARITHM_OP('^', BPF_XOR);
-
-	    case '&':
-	      state = 20; /* '&' */
-	      break;
-
-	    case '<':
-	      switch (state)
-		{
-		case 0:
-		  state = 18; /* '<' */
-		  break;
-
-		case 18:
-		  state = 19; /* <'<' */
-		  break;
-
-		case 8:
-		  state = 22; /* s'<' */
-		  break;
-		}
-	      break;
-
-	    case '>':
-	      switch (state)
-		{
-		case 0:
-		  state = 12; /* '>' */
-		  break;
-
-		case 12:
-		  state = 13; /* >'>' */
-		  break;
-
-		case 8:
-		  state = 14; /* s'>' */
-		  break;
-
-		case 14:
-		  state = 15; /* s>'>' */
-		  break;
-		}
-	      break;
-	    }
-	  break;
-
-	case LEX_IS_STAR:
-	  switch (state)
-	    {
-	    case 0:
-	      token[len++] = ch;
-	      START_EXPR ();
-	      state = 2; /* '*', It could be the fist cast char.  */
-	      break;
-
-	    case 16: /* ='*' Not valid token.  */
-	      ttype = BPF_MOV;
-	      return_token = 1;
-	      UNGET ();
-	      break;
-
-	    case 4: /* *(uXX'*' */
-	      token[len++] = ch;
-	      state = 5;
-	      break;
-	    }
-	  break;
-
-	case LEX_IS_OPEN_BR:
-	  START_EXPR ();
-	  token[len++] = ch;
-	  return_token = 1;
-
-	  switch (state)
-	    {
-	    case 2:
-	      state = 3; /* *'(' second char of a cast or expr.  */
-	      return_token = 0;
-	      break;
-
-	    case 6:
-	      if (valid_expr (expr, &end_expr))
-		{
-		  len = end_expr - expr;
-		  memcpy (token, expr, len);
-		  ttype = BPF_EXPR;
-		  str = end_expr;
-		}
-	      else
-		{
-		  len = 0;
-		  while (*invalid_expression)
-		    token[len++] = *invalid_expression++;
-
-		  token[len] = 0;
-		  ttype = BPF_UNKNOWN;
-		}
-	      break;
-
-	    default:
-	      ttype = BPF_CHR_OPEN_BR;
-	      SCANNER_SKIP_WHITESPACE ();
-	      ch2 = GET ();
-
-	      if ((isdigit (ch2) || ch2 == '(')
-		  && valid_expr (expr, &end_expr))
-		{
-		  len = end_expr - expr;
-		  memcpy (token, expr, len);
-		  ttype = BPF_EXPR;
-		  str = end_expr;
-		}
-	      else
-		UNGET ();
-	    }
-	  break;
-
-	case LEX_IS_CLSE_BR:
-	  token[len++] = ch;
-
-	  if (state == 0)
-	    {
-	      ttype = BPF_CHR_CLSE_BR;
-	      return_token = 1;
-	    }
-	  else if (state == 5) /* *(uXX*')'  */
-	    return_token = 1;
-	  break;
-
-	case LEX_IS_EQUAL:
-	  token[len++] = ch;
-	  return_token = 1;
-
-	  switch (state)
-	    {
-	    case 0:
-	      state = 16; /* '=' */
-	      return_token = 0;
-	      break;
-
-	    case 16:
-	      state = 17; /* ='=' */
-	      return_token = 0;
-	      break;
-
-	    case 2: /* *'=' */
-	      ttype = BPF_MUL;
-	      break;
-
-	    case 10: /* s>>'=' */
-	      ttype = BPF_ARSH;
-	      break;
-
-	    case 12: /* >'=' */
-	      ttype = BPF_JGE;
-	      break;
-
-	    case 13: /* >>'=' */
-	      ttype = BPF_RSH;
-	      break;
-
-	    case 14: /* s>'=' */
-	      ttype = BPF_JSGE;
-	      break;
-
-	    case 15: /* s>>'=' */
-	      ttype = BPF_ARSH;
-	      break;
-
-	    case 18: /* <'=' */
-	      ttype = BPF_JLE;
-	      break;
-
-	    case 19: /* <<'=' */
-	      ttype = BPF_LSH;
-	      break;
-
-	    case 20: /* &'=' */
-	      ttype = BPF_AND;
-	      break;
-
-	    case 21: /* !'=' */
-	      ttype = BPF_JNE;
-	      break;
-
-	    case 22: /* s<'=' */
-	      ttype = BPF_JSLE;
-	      break;
-	    }
-	  break;
-
-	case LEX_IS_SYMBOL_COMPONENT:
-	  return_token = 1;
-
-	  switch (state)
-	    {
-	    case 17: /* =='sym' */
-	      ttype = BPF_JEQ;
-	      break;
-
-	    case 12: /* >'sym' */
-	      ttype = BPF_JGT;
-	      break;
-
-	    case 18: /* <'sym' */
-	      ttype = BPF_JLT;
-	      break;
-
-	    case 20: /* &'sym' */
-	      ttype = BPF_JSET;
-	      break;
-
-	    case 14: /*s>'sym' */
-	      ttype = BPF_JSGT;
-	      break;
-
-	    case 22:  /* s<'sym' */
-	      ttype = BPF_JSLT;
-	      break;
-
-	    case 16: /* ='sym' */
-	      ttype = BPF_MOV;
-	      break;
-
-	    default:
-	      return_token = 0;
-	    }
-
-	  if (return_token)
-	    {
-	      UNGET ();
-	      break;
-	    }
-
-	  START_EXPR ();
-	  token[len++] = ch;
-
-	  while ((ch2 = GET ()) != EOF)
-	    {
-	      int type;
-
-	      type = pseudoc_lex[(unsigned char) ch2];
-	      if (type != LEX_IS_SYMBOL_COMPONENT)
-		break;
-	      token[len++] = ch2;
-	    }
-
-	  if (ch2 != EOF)
-	    UNGET ();
-
-	  if (state == 0)
-	    {
-	      if (len == 1 && ch == 's')
-		state = 8; /* signed instructions: 's' */
-	      else
-		{
-		  ttype = BPF_SYMBOL;
-		  if (is_register (token, len))
-		    ttype = BPF_REG;
-		  else if (look_for_reserved_word (token, &ttype))
-		    ;
-		  else if ((pseudoc_lex[(unsigned char) *token] == LEX_IS_ARITHM_OP
-			    || *token == '(' || isdigit(*token))
-			   && valid_expr (expr, &end_expr))
-		    {
-		      len = end_expr - expr;
-		      token[len] = '\0';
-		      ttype = BPF_EXPR;
-		      str = end_expr;
-		    }
-
-		  return_token = 1;
-		}
-	    }
-	  else if (state == 3) /* *('sym' */
-	    {
-	      if ((ttype = is_cast (&token[2])) != BPF_UNKNOWN)
-		state = 4; /* *('uXX' */
-	      else
-		{
-		  ttype = BPF_EXPR;
-		  return_token = 1;
-		}
-	    }
-	  else if (state == 6)
-	    {
-	      if (ttype == BPF_SUB) /* neg */
-		{
-		  if (is_register (&token[1], len - 1))
-		    ttype =  BPF_NEG;
-		  else if (valid_expr(expr, &end_expr))
-		    {
-		      len = end_expr - expr;
-		      memcpy(token, expr, len);
-		      ttype = BPF_EXPR;
-		      str = end_expr;
-		    }
-		  else
-		    {
-		      len = 0;
-		      while (*invalid_expression)
-			token[len++] = *invalid_expression++;
-		      token[len] = 0;
-		      ttype = BPF_UNKNOWN;
-		    }
-		}
-	      else if (valid_expr (expr, &end_expr))
-		{
-		  len = end_expr - expr;
-		  memcpy(token, expr, len);
-		  ttype = BPF_EXPR;
-		  str = end_expr;
-		}
-	      else
-		ttype = BPF_UNKNOWN;
-
-	      return_token = 1;
-	    }
-	  break;
-	}
+      va_list args;
 
-      if (return_token)
-	{
-	  *tlen = len;
-	  *insn = str;
-	  break;
-	}
+      free (errmsg);
+      va_start (args, fmt);
+      errmsg = xvasprintf (fmt, args);
+      va_end (args);
+      partial_match_length = length;
     }
-
-  return ttype;
-
-#undef GET
-#undef UNGET
-#undef START_EXPR
-#undef SCANNER_SKIP_WHITESPACE
-#undef BPF_ARITHM_OP
 }
 
-/*
-  The parser represent a FSM for the grammar described above. So for example
-  the following rule:
-
-     ` bpf_alu_insn : BPF_REG bpf_alu_operator register_or_imm32'
-
-  Is parser as follows:
-
-      1. It starts in state 0.
+/* Assemble a machine instruction in STR and emit the frags/bytes it
+   assembles to.  */
 
-      2. Consumes next token, e.g: `BPF_REG' and set `state' variable to a
-      particular state to helps to identify, in this case, that a register
-      token has been read, a comment surrounded by a single quote in the
-      pseudo-c token is added along with the new `state' value to indicate
-      what the scanner has read, e.g.:
-
-          state = 6; // dst_reg = str_cast ( 'src_reg'
-
-      So, in `state 6' the scanner has consumed: a destination register
-      (BPF_REG), an equal character (BPF_MOV), a cast token (BPF_CAST), an
-      open parenthesis (BPF_CHR_OPEN_BR) and the source register (BPF_REG).
-
-      3. If the accumulated tokens represent a complete BPF pseudo-c syntax
-      instruction then, a validation of the terms is made, for example: if
-      the registers have the same sizes (32/64 bits), if a specific
-      destination register must be used, etc., after that, a builder:
-      build_bfp_{non_generic_load,atomic_insn,jmp_insn,arithm_insn,endianness,load_store_insn}
-      is invoked, internally, it translates the BPF pseudo-c instruction to
-      a BPF GAS instruction using the previous terms recollected by the
-      scanner.
-
-      4. If a successful build of BPF GAS instruction was done, a final
-      state is set to `ST_EOI' (End Of Instruction) meaning that is not
-      expecting for more tokens in such instruction.  Otherwise if the
-      conditions to calling builder are not satisfied an error is emitted
-      and `parse_err' is set.
-*/
-
-static char *
-bpf_pseudoc_to_normal_syntax (const char *str, char **errmsg)
+void
+md_assemble (char *str ATTRIBUTE_UNUSED)
 {
-#define syntax_err(format, ...)						\
-  do									\
-    {									\
-      if (! parse_err)							\
-	{								\
-	  parse_err = 1;						\
-	  errbuf = xasprintf (format, ##__VA_ARGS__);			\
-	}								\
-    } while (0)
-
-  enum bpf_token_type ttype;
-  enum bpf_token_type bpf_endianness = BPF_UNKNOWN,
-		      bpf_atomic_insn;
-  enum bpf_token_type bpf_jmp_op = BPF_JEQ; /* Arbitrary.  */
-  enum bpf_token_type bpf_cast = BPF_CAST_U8; /* Arbitrary.  */
-  enum bpf_token_type bpf_arithm_op = BPF_ADD; /* Arbitrary.  */
-  char *bpf_insn = NULL;
-  char *errbuf = NULL;
-  char src_reg[3] = {0};
-  char dst_reg[3] = {0};
-  char str_imm32[40] = {0};
-  char str_offset[40] = {0};
-  char str_symbol[MAX_TOKEN_SZ] = {0};
-  char token[MAX_TOKEN_SZ] = {0};
-  int state = 0;
-  int parse_err = 0;
-  size_t tlen;
-
-  while (*str)
+  /* There are two different syntaxes that can be used to write BPF
+     instructions.  One is very conventional and like any other
+     assembly language where each instruction is conformed by an
+     instruction mnemonic followed by its operands.  This is what we
+     call the "normal" syntax.  The other syntax tries to look like C
+     statements. We have to support both syntaxes in this assembler.
+
+     One of the many nuisances introduced by this eccentricity is that
+     in the pseudo-c syntax it is not possible to hash the opcodes
+     table by instruction mnemonic, because there is none.  So we have
+     no other choice than to try to parse all instruction opcodes
+     until one matches.  This is slow.
+
+     Another problem is that emitting detailed diagnostics becomes
+     tricky, since the lack of mnemonic means it is not clear what
+     instruction was intended by the user, and we cannot emit
+     diagnostics for every attempted template.  So if an instruction
+     is not parsed, we report the diagnostic corresponding to the
+     partially parsed instruction that was matched further.  */
+
+  unsigned int idx = 0;
+  struct bpf_insn insn;
+  const struct bpf_opcode *opcode;
+
+  /* Initialize the global diagnostic variables.  See the parse_error
+     function above.  */
+  partial_match_length = 0;
+  errmsg = NULL;
+
+#define PARSE_ERROR(...) parse_error (s - str, __VA_ARGS__)
+
+  while ((opcode = bpf_get_opcode (idx++)) != NULL)
     {
-      ttype = get_token (&str, token, &tlen);
-      if (ttype == BPF_UNKNOWN || state == ST_EOI)
-	{
-	  syntax_err ("unexpected token: '%s'", token);
-	  break;
-	}
-
-      switch (ttype)
-	{
-	case BPF_UNKNOWN:
-	case BPF_LL:
-	  break;
-
-	case BPF_REG:
-	  switch (state)
-	    {
-	    case 0:
-	      memcpy (dst_reg, token, tlen);
-	      state = 1; /* 'dst_reg' */
-	      break;
-
-	    case 3:
-	      /* dst_reg bpf_op 'src_reg' */
-	      memcpy (src_reg, token, tlen);
-	      if (*dst_reg == *src_reg)
-		bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0,
-						  NULL, bpf_arithm_op);
-	      else
-		{
-		  syntax_err ("different register sizes: '%s', '%s'",
-			      dst_reg, src_reg);
-		  break;
-		}
-	      state = ST_EOI;
-	      break;
-
-	    case 5:
-	      memcpy (src_reg, token, tlen);
-	      state = 6; /* dst_reg = str_cast ( 'src_reg' */
-	      break;
-
-	    case 9:
-	      memcpy (dst_reg, token, tlen);
-	      state = 10; /* str_cast ( 'dst_reg' */
-	      break;
-
-	    case 11:
-	      /* str_cast ( dst_reg offset ) = 'src_reg' */
-	      memcpy (src_reg, token, tlen);
-	      bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,
-						    bpf_cast, str_offset, 0);
-	      state = ST_EOI;
-	      break;
-
-	    case 14:
-	      memcpy (dst_reg, token, tlen);
-	      state = 15; /* if 'dst_reg' */
-	      break;
-
-	    case 16:
-	      memcpy (src_reg, token, tlen);
-	      state = 17; /* if dst_reg jmp_op 'src_reg' */
-	      break;
-
-	    case 24:
-	      /* dst_reg = endianness src_reg */
-	      memcpy (src_reg, token, tlen);
-	      if (*dst_reg == 'r' && !strcmp (dst_reg, src_reg))
-		bpf_insn = build_bpf_endianness (dst_reg, bpf_endianness);
-	      else
-		syntax_err ("invalid operand for instruction: '%s'", token);
-
-	      state = ST_EOI;
-	      break;
-
-	    case 28:
-	      memcpy (dst_reg, token, tlen);
-	      state = 29; /* lock str_cast ( 'dst_reg'  */
-	      break;
-
-	    case 32:
-	      {
-		/* lock str_cast ( dst_reg offset ) atomic_insn 'src_reg' */
-		int with_offset = *str_offset != '\0';
-
-		memcpy (src_reg, token, tlen);
-		if ((bpf_cast != BPF_CAST_U32
-		     && bpf_cast != BPF_CAST_U64)
-		    || *dst_reg != 'r'
-		    || *src_reg != 'r')
-		  syntax_err ("invalid wide atomic instruction");
-		else
-		  bpf_insn = build_bpf_atomic_insn (dst_reg, src_reg, bpf_atomic_insn,
-						    bpf_cast, with_offset ? str_offset : str_symbol);
-	      }
-
-	      state = ST_EOI;
-	      break;
-
-	    case 33:
-	      /* callx 'dst_reg' */
-	      bpf_insn = xasprintf ("%s %%%s", "call", token);
-	      state = ST_EOI;
-	      break;
-
-	    case 35:
-	      memcpy (src_reg, token, tlen);
-	      state = 36; /* dst_reg = str_cast skb [ 'src_reg' */
-	      break;
-	    }
-	  break;
-
-	case BPF_MOV:
-	case BPF_ADD:
-	case BPF_SUB:
-	case BPF_MUL:
-	case BPF_DIV:
-	case BPF_OR:
-	case BPF_AND:
-	case BPF_LSH:
-	case BPF_RSH:
-	case BPF_MOD:
-	case BPF_XOR:
-	case BPF_ARSH:
-	case BPF_NEG:
-	  switch (state)
-	    {
-	    case 1:
-	      state = 3;  /* dst_reg 'arith_op' */
-	      bpf_arithm_op = ttype;
-	      break;
-
-	    case 3:
-	      if (ttype == BPF_NEG)
-		{
-		  /* reg = -reg */
-		  bpf_arithm_op = ttype;
-		  memcpy (src_reg, token + 1, tlen - 1);
-		  if (strcmp (dst_reg, src_reg))
-		    {
-		      syntax_err ("found: '%s', expected: -%s", token, dst_reg);
-		      break;
-		    }
-
-		  bpf_insn = build_bpf_arithm_insn (dst_reg, src_reg, 0,
-						    NULL, bpf_arithm_op);
-		  state = ST_EOI;
-		}
-	      break;
-
-	    case 23:
-	      memcpy (src_reg, token, tlen);
-	      state = 11; /* str_cast ( dst_reg offset ) '=' */
-	      break;
-
-	    case 12:
-	      if (ttype == BPF_MOV)
-		state = 13; /* str_cast ( dst_reg offset ) '=' */
-	      break;
-
-	    case 31:
-	      bpf_atomic_insn = ttype;
-	      state = 32; /* lock str_cast ( dst_reg offset ) 'atomic_insn' */
-	      break;
-
-	    default:
-	      syntax_err ("unexpected '%s'", token);
-	      state = ST_EOI;
-	    }
-	  break;
-
-	case BPF_CAST_U8:
-	case BPF_CAST_U16:
-	case BPF_CAST_U32:
-	case BPF_CAST_U64:
-	  bpf_cast = ttype;
-	  switch (state)
-	    {
-	    case 3:
-	      state = 4; /* dst_reg = 'str_cast' */
-	      break;
-
-	    case 0:
-	      state = 8;  /* 'str_cast' */
-	      break;
-
-	    case 26:
-	      state = 27; /* lock 'str_cast' */
-	      break;
-	    }
-	  break;
-
-	case BPF_CHR_OPEN_BR:
-	  switch (state)
-	    {
-	    case 4:
-	      state = 5; /* dst_reg = str_cast '(' */
-	      break;
-
-	    case 8:
-	      state = 9; /* str_cast '(' */
-	      break;
-
-	    case 27:
-	      state = 28; /* lock str_cast '(' */
-	      break;
-
-	    case 34:
-	      state = 35; /* dst_reg = str_cast skb '[' */
-	      break;
-	    }
-	  break;
+      const char *p;
+      char *s;
+      const char *template
+        = (asm_dialect == DIALECT_PSEUDOC ? opcode->pseudoc : opcode->normal);
+
+      /* Do not try to match opcodes with a higher version than the
+         selected ISA spec.  */
+      if (opcode->version > isa_spec)
+        continue;
+
+      memset (&insn, 0, sizeof (struct bpf_insn));
+      insn.size = 8;
+      for (s = str, p = template; *p != '\0';)
+        {
+          if (*p == ' ')
+            {
+              /* Expect zero or more spaces.  */
+              while (*s != '\0' && (*s == ' ' || *s == '\t'))
+                s += 1;
+              p += 1;
+            }
+          else if (*p == '%')
+            {
+              if (*(p + 1) == '%')
+                {
+                  if (*s != '%')
+                    {
+                      PARSE_ERROR ("expected '%%'");
+                      break;
+                    }
+                  p += 2;
+                  s += 1;
+                }
+              else if (*(p + 1) == 'w')
+                {
+                  /* Expect zero or more spaces.  */
+                  while (*s != '\0' && (*s == ' ' || *s == '\t'))
+                    s += 1;
+                  p += 2;
+                }
+              else if (*(p + 1) == 'W')
+                {
+                  /* Expect one or more spaces.  */
+                  if (*s != ' ' && *s != '\t')
+                    {
+                      PARSE_ERROR ("expected white space, got '%s'",
+                                   s);
+                      break;
+                    }
+                  while (*s != '\0' && (*s == ' ' || *s == '\t'))
+                    s += 1;
+                  p += 2;
+                }
+              else if (strncmp (p, "%dr", 3) == 0)
+                {
+                  uint8_t regno;
+                  char *news = parse_bpf_register (s, 'r', &regno);
+
+                  if (news == NULL || (insn.has_dst && regno != insn.dst))
+                    {
+                      if (news != NULL)
+                        PARSE_ERROR ("expected register r%d, got r%d",
+                                     insn.dst, regno);
+                      else
+                        PARSE_ERROR ("expected register name, got '%s'", s);
+                      break;
+                    }
+                  s = news;
+                  insn.dst = regno;
+                  insn.has_dst = 1;
+                  p += 3;
+                }
+              else if (strncmp (p, "%sr", 3) == 0)
+                {
+                  uint8_t regno;
+                  char *news = parse_bpf_register (s, 'r', &regno);
+
+                  if (news == NULL || (insn.has_src && regno != insn.src))
+                    {
+                      if (news != NULL)
+                        PARSE_ERROR ("expected register r%d, got r%d",
+                                     insn.dst, regno);
+                      else
+                        PARSE_ERROR ("expected register name, got '%s'", s);
+                      break;
+                    }
+                  s = news;
+                  insn.src = regno;
+                  insn.has_src = 1;
+                  p += 3;
+                }
+              else if (strncmp (p, "%dw", 3) == 0)
+                {
+                  uint8_t regno;
+                  char *news = parse_bpf_register (s, 'w', &regno);
+
+                  if (news == NULL || (insn.has_dst && regno != insn.dst))
+                    {
+                      if (news != NULL)
+                        PARSE_ERROR ("expected register r%d, got r%d",
+                                     insn.dst, regno);
+                      else
+                        PARSE_ERROR ("expected register name, got '%s'", s);
+                      break;
+                    }
+                  s = news;
+                  insn.dst = regno;
+                  insn.has_dst = 1;
+                  p += 3;
+                }
+              else if (strncmp (p, "%sw", 3) == 0)
+                {
+                  uint8_t regno;
+                  char *news = parse_bpf_register (s, 'w', &regno);
+
+                  if (news == NULL || (insn.has_src && regno != insn.src))
+                    {
+                      if (news != NULL)
+                        PARSE_ERROR ("expected register r%d, got r%d",
+                                     insn.dst, regno);
+                      else
+                        PARSE_ERROR ("expected register name, got '%s'", s);
+                      break;
+                    }
+                  s = news;
+                  insn.src = regno;
+                  insn.has_src = 1;
+                  p += 3;
+                }
+              else if (strncmp (p, "%i32", 4) == 0
+                       || strncmp (p, "%I32", 4) == 0)
+                {
+                  if (p[1] == 'I')
+                    {
+                      while (*s == ' ' || *s == '\t')
+                        s += 1;
+                      if (*s != '+' && *s != '-')
+                        {
+                          PARSE_ERROR ("expected `+' or `-', got `%c'", *s);
+                          break;
+                        }
+                    }
+
+                  s = parse_expression (s, &insn.imm32);
+                  if (s == NULL)
+                    {
+                      PARSE_ERROR ("expected signed 32-bit immediate");
+                      break;
+                    }
+                  insn.has_imm32 = 1;
+                  p += 4;
+                }
+              else if (strncmp (p, "%o16", 4) == 0)
+                {
+                  while (*s == ' ' || *s == '\t')
+                    s += 1;
+                  if (*s != '+' && *s != '-')
+                    {
+                      PARSE_ERROR ("expected `+' or `-', got `%c'", *s);
+                      break;
+                    }
+
+                  s = parse_expression (s, &insn.offset16);
+                  if (s == NULL)
+                    {
+                      PARSE_ERROR ("expected signed 16-bit offset");
+                      break;
+                    }
+                  insn.has_offset16 = 1;
+                  p += 4;
+                }
+              else if (strncmp (p, "%d16", 4) == 0)
+                {
+                  s = parse_expression (s, &insn.disp16);
+                  if (s == NULL)
+                    {
+                      PARSE_ERROR ("expected signed 16-bit displacement");
+                      break;
+                    }
+                  insn.has_disp16 = 1;
+                  p += 4;
+                }
+              else if (strncmp (p, "%d32", 4) == 0)
+                {
+                  s = parse_expression (s, &insn.disp32);
+                  if (s == NULL)
+                    {
+                      PARSE_ERROR ("expected signed 32-bit displacement");
+                      break;
+                    }
+                  insn.has_disp32 = 1;
+                  p += 4;
+                }
+              else if (strncmp (p, "%i64", 4) == 0)
+                {
+                  s = parse_expression (s, &insn.imm64);
+                  if (s == NULL)
+                    {
+                      PARSE_ERROR ("expected signed 64-bit immediate");
+                      break;
+                    }
+                  insn.has_imm64 = 1;
+                  insn.size = 16;
+                  p += 4;
+                }
+              else
+                as_fatal (_("invalid %%-tag in BPF opcode '%s'\n"), template);
+            }
+          else
+            {
+              /* Match a literal character.  */
+              if (*s != *p)
+                {
+                  if (*s == '\0')
+                    PARSE_ERROR ("expected '%c'", *p);
+                  else if (*s == '%')
+                    {
+                      /* This is to workaround a bug in as_bad. */
+                      char tmp[3];
+
+                      tmp[0] = '%';
+                      tmp[1] = '%';
+                      tmp[2] = '\0';
+
+                      PARSE_ERROR ("expected '%c', got '%s'", *p, tmp);
+                    }
+                  else
+                    PARSE_ERROR ("expected '%c', got '%c'", *p, *s);
+                  break;
+                }
+              p += 1;
+              s += 1;
+            }
+        }
 
-	case BPF_CHR_CLSE_BR:
-	  switch (state)
-	    {
-	    case 7:
-	      /* dst_reg = str_cast ( imm32 ')' */
-	      bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,
-						    bpf_cast, str_imm32, 1);
-	      state = ST_EOI;
-	      break;
-
-	    case 11:
-	      state = 12; /* str_cast ( dst_reg imm32 ')' */
-	      break;
-
-	    case 21:
-	      /* dst_reg = str_cast ( src_reg  offset ')' */
-	      bpf_insn = build_bpf_load_store_insn (dst_reg, src_reg,
-						    bpf_cast, str_offset, 1);
-	      state = ST_EOI;
-	      break;
-
-	    case 22:
-	      state = 23; /* str_cast ( dst_reg offset ')' */
-	      break;
-
-	    case 30:
-	      state = 31; /* lock str_cast ( dst_reg offset ')' */
-	      break;
-
-	    case 37:
-	      /* dst_reg = str_cast skb [ src_reg imm32 ']' */
-	      if (*dst_reg != 'w' && !strcmp ("r0", dst_reg))
-		bpf_insn = build_bpf_non_generic_load (*src_reg != '\0' ? src_reg : NULL,
-						       bpf_cast, str_imm32);
-	      else
-		syntax_err ("invalid register operand: '%s'", dst_reg);
-
-	      state = ST_EOI;
-	      break;
-	    }
-	  break;
+      if (*p == '\0')
+        {
+          /* Allow white spaces at the end of the line.  */
+          while (*s != '\0' && (*s == ' ' || *s == '\t'))
+            s += 1;
+          if (*s == '\0')
+            /* We parsed an instruction successfully.  */
+            break;
+          PARSE_ERROR ("extra junk at end of line");
+        }
+    }
 
-	case BPF_EXPR:
-	  switch (state)
-	    {
-	    case 3:
-	      {
-		/* dst_reg bpf_arithm_op 'imm32' */
-		int load64 = 0;
-
-		memcpy (str_imm32, token, tlen);
-		memset (token, 0, tlen);
-
-		if ((ttype = get_token (&str, token, &tlen)) == BPF_LL
-		    && bpf_arithm_op == BPF_MOV)
-		  load64 = 1;
-		else if (ttype != BPF_UNKNOWN)
-		  syntax_err ("unexpected token: '%s'", token);
-
-		if (load64 && *dst_reg == 'w')
-		  syntax_err ("unexpected register size: '%s'", dst_reg);
-
-		if (! parse_err)
-		  bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64,
-						    str_imm32, bpf_arithm_op);
-		state = ST_EOI;
-	      }
-	      break;
-
-	    case 18:
-	      {
-		/* if dst_reg jmp_op src_reg goto 'offset' */
-		int with_src = *src_reg != '\0';
-
-		memcpy (str_offset, token, tlen);
-		if (with_src && *dst_reg != *src_reg)
-		  syntax_err ("different register size: '%s', '%s'",
-			      dst_reg, src_reg);
-		else
-		  bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL,
-						 with_src ? NULL: str_imm32,
-						 bpf_jmp_op, NULL, str_offset);
-		state = ST_EOI;
-	      }
-	      break;
-
-	    case 19:
-	      /* goto 'offset' */
-	      memcpy (str_offset, token, tlen);
-	      bpf_insn = xasprintf ("%s %s", "ja", str_offset);
-	      state = ST_EOI;
-	      break;
-
-	    case 6:
-	      memcpy (str_offset, token, tlen);
-	      state = 21; /* dst_reg = str_cast ( src_reg  'offset' */
-	      break;
-
-	    case 10:
-	      memcpy (str_offset, token, tlen);
-	      state = 22; /* str_cast ( dst_reg 'offset' */
-	      break;
-
-	    case 16:
-	      memcpy (str_imm32, token, tlen);
-	      state = 25; /* if dst_reg jmp_op 'imm32' */
-	      break;
-
-	    case 29:
-	      memcpy (str_offset, token, tlen);
-	      state = 30; /* lock str_cast ( dst_reg 'offset' */
-	      break;
-
-	    case 34:
-	      /* dst_reg = str_cast skb 'imm32' */
-	      if (*dst_reg != 'w' && !strcmp ("r0", dst_reg))
-		{
-		  memcpy (str_imm32, token, tlen);
-		  bpf_insn = build_bpf_non_generic_load (*src_reg != '\0' ? src_reg : NULL,
-							 bpf_cast, str_imm32);
-		}
-	      else
-		syntax_err ("invalid register operand: '%s'", dst_reg);
-
-	      state = ST_EOI;
-	      break;
-
-	    case 36:
-	      memcpy (str_imm32, token, tlen);
-	      state = 37; /* dst_reg = str_cast skb [ src_reg 'imm32' */
-	      break;
-	    }
-	  break;
+  if (opcode == NULL)
+    {
+      as_bad (_("unrecognized instruction `%s'"), str);
+      if (errmsg != NULL)
+        {
+          as_bad (errmsg);
+          free (errmsg);
+        }
 
-	case BPF_IF:
-	  if (state == 0)
-	    state = 14;
-	  break;
+      return;
+    }
+  insn.opcode = opcode->opcode;
 
-	case BPF_JSGT:
-	case BPF_JSLT:
-	case BPF_JSLE:
-	case BPF_JSGE:
-	case BPF_JGT:
-	case BPF_JGE:
-	case BPF_JLE:
-	case BPF_JSET:
-	case BPF_JNE:
-	case BPF_JLT:
-	case BPF_JEQ:
-	  if (state == 15)
-	    {
-	      bpf_jmp_op = ttype;
-	      state = 16; /* if dst_reg 'jmp_op' */
-	    }
-	  break;
+#undef PARSE_ERROR
 
-	case BPF_GOTO:
-	  switch (state)
-	    {
-	    case 17:
-	    case 25:
-	      state = 18; /* if dst_reg jmp_op src_reg|imm32 'goto' */
-	      break;
-
-	    case 0:
-	      state = 19;
-	      break;
-	    }
-	  break;
+  /* Generate the frags and fixups for the parsed instruction.  */
+  {
+    char *this_frag = frag_more (insn.size);
+    char bytes[16];
+    uint8_t src, dst;
+    int i;
+
+    /* Zero all the bytes.  */
+    memset (bytes, 0, 16);
+
+    /* First encode the opcodes.  Note that we have to handle the
+       endianness groups of the BPF instructions: 8 | 4 | 4 | 16 |
+       32. */
+    if (target_big_endian)
+      {
+        /* code */
+        bytes[0] = (insn.opcode >> 56) & 0xff;
+        /* regs */
+        bytes[1] = (insn.opcode >> 48) & 0xff;
+        /* offset16 */
+        bytes[2] = (insn.opcode >> 40) & 0xff;
+        bytes[3] = (insn.opcode >> 32) & 0xff;
+        /* imm32 */
+        bytes[4] = (insn.opcode >> 24) & 0xff;
+        bytes[5] = (insn.opcode >> 16) & 0xff;
+        bytes[6] = (insn.opcode >> 8) & 0xff;
+        bytes[7] = insn.opcode & 0xff;
+      }
+    else
+      {
+        /* code */
+        bytes[0] = (insn.opcode >> 56) & 0xff;
+        /* regs */
+        bytes[1] = (((((insn.opcode >> 48) & 0xff) & 0xf) << 4)
+                    | (((insn.opcode >> 48) & 0xff) & 0xf));
+        /* offset16 */
+        bytes[3] = (insn.opcode >> 40) & 0xff;
+        bytes[2] = (insn.opcode >> 32) & 0xff;
+        /* imm32 */
+        bytes[7] = (insn.opcode >> 24) & 0xff;
+        bytes[6] = (insn.opcode >> 16) & 0xff;
+        bytes[5] = (insn.opcode >> 8) & 0xff;
+        bytes[4] = insn.opcode & 0xff;
+      }
 
-	case BPF_SYMBOL:
-	  switch (state)
-	    {
-	    case 18:
-	      {
-		/* if dst_reg jmp_op src_reg goto 'sym' */
-		int with_src = *src_reg != '\0';
-
-		memcpy (str_symbol, token, tlen);
-		if (with_src && *dst_reg != *src_reg)
-		  syntax_err ("different register size: '%s', '%s'",
-			      dst_reg, src_reg);
-		else
-		  bpf_insn = build_bpf_jmp_insn (dst_reg, with_src ? src_reg : NULL,
-						 with_src ? NULL: str_imm32,
-						 bpf_jmp_op, str_symbol, NULL);
-		state = ST_EOI;
-	      }
-	      break;
-
-	    case 19:
-	      /* goto 'sym' */
-	      memcpy (str_symbol, token, tlen);
-	      bpf_insn = xasprintf ("%s %s", "ja", str_symbol);
-	      state = ST_EOI;
-	      break;
-
-	    case 0:
-	      state = ST_EOI;
-	      break;
-
-	    case 3:
-	      {
-		/* dst_reg arithm_op 'sym' */
-		int load64 = 0;
-		
-		memcpy (str_symbol, token, tlen);
-		memset (token, 0, tlen);
-
-		if ((ttype = get_token (&str, token, &tlen)) == BPF_LL
-		    && bpf_arithm_op == BPF_MOV)
-		  load64 = 1;
-		else if (ttype != BPF_UNKNOWN)
-		  syntax_err ("unexpected token: '%s'", token);
-
-		if (load64 && *dst_reg == 'w')
-		  syntax_err ("unexpected register size: '%s'", dst_reg);
-
-		if (! parse_err)
-		  bpf_insn = build_bpf_arithm_insn (dst_reg, NULL, load64,
-						    str_symbol, bpf_arithm_op);
-		state = ST_EOI;
-	      }
-	      break;
-	    }
-	  break;
+    /* Now the registers.  */
+    src = insn.has_src ? insn.src : 0;
+    dst = insn.has_dst ? insn.dst : 0;
 
-	case BPF_LE16:
-	case BPF_LE32:
-	case BPF_LE64:
-	case BPF_BE16:
-	case BPF_BE32:
-	case BPF_BE64:
-	  bpf_endianness = ttype;
-	  state = 24; /* dst_reg = 'endianness' */
-	  break;
+    if (target_big_endian)
+      bytes[1] = ((dst & 0xf) << 4) | (src & 0xf);
+    else
+      bytes[1] = ((src & 0xf) << 4) | (dst & 0xf);
 
-	case BPF_LOCK:
-	  state = 26;
-	  break;
+    /* Now the immediates.  */
+    if (insn.has_imm64)
+      {
+        switch (insn.imm64.X_op)
+          {
+          case O_constant:
+            {
+              uint64_t imm64 = insn.imm64.X_add_number;
+
+              if (target_big_endian)
+                {
+                  bytes[12] = (imm64 >> 56) & 0xff;
+                  bytes[13] = (imm64 >> 48) & 0xff;
+                  bytes[14] = (imm64 >> 40) & 0xff;
+                  bytes[15] = (imm64 >> 32) & 0xff;
+                  bytes[4] = (imm64 >> 24) & 0xff;
+                  bytes[5] = (imm64 >> 16) & 0xff;
+                  bytes[6] = (imm64 >> 8) & 0xff;
+                  bytes[7] = imm64 & 0xff;
+                }
+              else
+                {
+                  bytes[15] = (imm64 >> 56) & 0xff;
+                  bytes[14] = (imm64 >> 48) & 0xff;
+                  bytes[13] = (imm64 >> 40) & 0xff;
+                  bytes[12] = (imm64 >> 32) & 0xff;
+                  bytes[7] = (imm64 >> 24) & 0xff;
+                  bytes[6] = (imm64 >> 16) & 0xff;
+                  bytes[5] = (imm64 >> 8) & 0xff;
+                  bytes[4] = imm64 & 0xff;
+                }
+              break;
+            }
+          case O_symbol:
+          case O_subtract:
+          case O_add:
+            {
+              reloc_howto_type *reloc_howto;
+              int size;
+
+              reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_64);
+              if (!reloc_howto)
+                abort ();
+
+              size = bfd_get_reloc_size (reloc_howto);
+
+              fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+                           size, &insn.imm64, reloc_howto->pc_relative,
+                           BFD_RELOC_BPF_64);
+              break;
+            }
+          default:
+            abort ();
+          }
+      }
 
-	case BPF_IND_CALL:
-	  state = 33;
-	  break;
+    if (insn.has_imm32)
+      {
+        switch (insn.imm32.X_op)
+          {
+          case O_constant:
+            {
+              uint32_t imm32 = insn.imm32.X_add_number;
+
+              if (target_big_endian)
+                {
+                  bytes[4] = (imm32 >> 24) & 0xff;
+                  bytes[5] = (imm32 >> 16) & 0xff;
+                  bytes[6] = (imm32 >> 8) & 0xff;
+                  bytes[7] = imm32 & 0xff;
+                }
+              else
+                {
+                  bytes[7] = (imm32 >> 24) & 0xff;
+                  bytes[6] = (imm32 >> 16) & 0xff;
+                  bytes[5] = (imm32 >> 8) & 0xff;
+                  bytes[4] = imm32 & 0xff;
+                }
+              break;
+            }
+          case O_symbol:
+          case O_subtract:
+          case O_add:
+          case O_uminus:
+            {
+              reloc_howto_type *reloc_howto;
+              int size;
+
+              reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
+              if (!reloc_howto)
+                abort ();
+
+              size = bfd_get_reloc_size (reloc_howto);
+
+              fix_new_exp (frag_now, this_frag - frag_now->fr_literal + 4,
+                           size, &insn.imm32, reloc_howto->pc_relative,
+                           BFD_RELOC_32);
+              break;
+            }
+          default:
+            abort ();
+          }
+      }
 
-	case BPF_LD:
-	  state = 34; /* dst_reg = str_cast 'skb' */
-	  break;
-	}
+    if (insn.has_disp32)
+      {
+        switch (insn.disp32.X_op)
+          {
+          case O_constant:
+            {
+              uint32_t disp32 = insn.disp32.X_add_number;
+
+              if (target_big_endian)
+                {
+                  bytes[4] = (disp32 >> 24) & 0xff;
+                  bytes[5] = (disp32 >> 16) & 0xff;
+                  bytes[6] = (disp32 >> 8) & 0xff;
+                  bytes[7] = disp32 & 0xff;
+                }
+              else
+                {
+                  bytes[7] = (disp32 >> 24) & 0xff;
+                  bytes[6] = (disp32 >> 16) & 0xff;
+                  bytes[5] = (disp32 >> 8) & 0xff;
+                  bytes[4] = disp32 & 0xff;
+                }
+              break;
+            }
+          case O_symbol:
+          case O_subtract:
+          case O_add:
+            {
+              reloc_howto_type *reloc_howto;
+              int size;
+
+              reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP32);
+              if (!reloc_howto)
+                abort ();
+
+              size = bfd_get_reloc_size (reloc_howto);
+
+              fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+                           size, &insn.disp32, reloc_howto->pc_relative,
+                           BFD_RELOC_BPF_DISP32);
+              break;
+            }
+          default:
+            abort ();
+          }
+      }
 
-      memset (token, 0, tlen);
-    }
+    if (insn.has_offset16)
+      {
+        switch (insn.offset16.X_op)
+          {
+          case O_constant:
+            {
+              uint32_t offset16 = insn.offset16.X_add_number;
+
+              if (target_big_endian)
+                {
+                  bytes[2] = (offset16 >> 8) & 0xff;
+                  bytes[3] = offset16 & 0xff;
+                }
+              else
+                {
+                  bytes[3] = (offset16 >> 8) & 0xff;
+                  bytes[2] = offset16 & 0xff;
+                }
+              break;
+            }
+          case O_symbol:
+          case O_subtract:
+          case O_add:
+            {
+              reloc_howto_type *reloc_howto;
+              int size;
+
+              reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16);
+              if (!reloc_howto)
+                abort ();
+
+              size = bfd_get_reloc_size (reloc_howto);
+
+              fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+                           size, &insn.offset16, reloc_howto->pc_relative,
+                           BFD_RELOC_BPF_DISP16);
+              break;
+            }
+          default:
+            abort ();
+          }
+      }
 
-  if (state != ST_EOI)
-    syntax_err ("incomplete instruction");
+    if (insn.has_disp16)
+      {
+        switch (insn.disp16.X_op)
+          {
+          case O_constant:
+            {
+              uint32_t disp16 = insn.disp16.X_add_number;
+
+              if (target_big_endian)
+                {
+                  bytes[2] = (disp16 >> 8) & 0xff;
+                  bytes[3] = disp16 & 0xff;
+                }
+              else
+                {
+                  bytes[3] = (disp16 >> 8) & 0xff;
+                  bytes[2] = disp16 & 0xff;
+                }
+              break;
+            }
+          case O_symbol:
+          case O_subtract:
+          case O_add:
+            {
+              reloc_howto_type *reloc_howto;
+              int size;
+
+              reloc_howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_BPF_DISP16);
+              if (!reloc_howto)
+                abort ();
+
+              size = bfd_get_reloc_size (reloc_howto);
+
+              fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
+                           size, &insn.disp16, reloc_howto->pc_relative,
+                           BFD_RELOC_BPF_DISP16);
+              break;
+            }
+          default:
+            abort ();
+          }
+      }
 
-  *errmsg = errbuf;
-  return bpf_insn;
+    /* Emit bytes.  */
+    for (i = 0; i < insn.size; ++i)
+      {
+        md_number_to_chars (this_frag, (valueT) bytes[i], 1);
+        this_frag += 1;
+      }
+  }
 
-#undef syntax_err
+  /* Emit DWARF2 debugging information.  */
+  dwarf2_emit_insn (insn.size);
 }
 
-void
-md_assemble (char *str)
-{
-  const CGEN_INSN *insn;
-  char *errmsg;
-  char *a_errmsg;
-  CGEN_FIELDS fields;
-  char *normal;
-
-#if CGEN_INT_INSN_P
-  CGEN_INSN_INT buffer[CGEN_MAX_INSN_SIZE / sizeof (CGEN_INT_INSN_P)];
-#else
-  unsigned char buffer[CGEN_MAX_INSN_SIZE];
-#endif
-
-  gas_cgen_init_parse ();
-  insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, str, &fields,
-                                  buffer, &errmsg);
-  if (insn == NULL)
-    {
-      normal = bpf_pseudoc_to_normal_syntax (str, &a_errmsg);
-      if (normal)
-	{
-	  insn = bpf_cgen_assemble_insn (gas_cgen_cpu_desc, normal, &fields,
-					 buffer, &a_errmsg);
-	  xfree (normal);
-	}
-
-      if (insn == NULL)
-	{
-	  as_bad ("%s", errmsg);
-	  if (a_errmsg)
-	    {
-	      as_bad ("%s", a_errmsg);
-	      xfree (a_errmsg);
-	    }
-	  return;
-	}
-    }
-
-  gas_cgen_finish_insn (insn, buffer, CGEN_FIELDS_BITSIZE (&fields),
-                        0, /* zero to ban relaxable insns.  */
-                        NULL); /* NULL so results not returned here.  */
-}
+/* Parse an operand that is machine-specific.  */
 
 void
 md_operand (expressionS *expressionP)
 {
-  invalid_expression = input_line_pointer - 1;
-  gas_cgen_md_operand (expressionP);
+  /* If this hook is invoked it means GAS failed to parse a generic
+  expression.  We should inhibit the as_bad in expr.c, so we can fail
+  while parsing instruction alternatives.  To do that, we change the
+  expression to not have an O_absent.  But then we also need to set
+  exp_parse_failed to parse_expression above does the right thing.  */
+  ++input_line_pointer;
+  expressionP->X_op = O_constant;
+  expressionP->X_add_number = 0;
+  exp_parse_failed = 1;
 }
 
-
 symbolS *
 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
@@ -1929,3 +1192,29 @@ md_atof (int type, char *litP, int *sizeP)
 {
   return ieee_md_atof (type, litP, sizeP, false);
 }
+
+
+/* Determine whether the equal sign in the given string corresponds to
+   a BPF instruction, i.e. when it is not to be considered a symbol
+   assignment.  */
+
+bool
+bpf_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char *str ATTRIBUTE_UNUSED)
+{
+  uint8_t regno;
+
+  /* Only pseudo-c instructions can have equal signs, and of these,
+     all that could be confused with a symbol assignment all start
+     with a register name.  */
+  if (asm_dialect == DIALECT_PSEUDOC)
+    {
+      char *w = parse_bpf_register (str, 'w', &regno);
+      char *r = parse_bpf_register (str, 'r', &regno);
+
+      if ((w != NULL && *w == '\0')
+          || (r != NULL && *r == '\0'))
+        return 1;
+    }
+
+  return 0;
+}
diff --git a/gas/config/tc-bpf.h b/gas/config/tc-bpf.h
index db604dbe8bc..d57a66fe460 100644
--- a/gas/config/tc-bpf.h
+++ b/gas/config/tc-bpf.h
@@ -37,7 +37,6 @@
 
 /* .-foo gets turned into PC relative relocs.  */
 #define DIFF_EXPR_OK    1
-#define GAS_CGEN_PCREL_R_TYPE(R_TYPE) gas_cgen_pcrel_r_type (R_TYPE)
 
 /* Call md_pcrel_from_section(), not md_pcrel_from().  */
 #define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
@@ -52,4 +51,5 @@
    a jump to offset 0 means jump to the next instruction.  */
 #define md_single_noop_insn "ja 0"
 
-#define TC_EQUAL_IN_INSN(c, s) 1
+#define TC_EQUAL_IN_INSN(c, s) bpf_tc_equal_in_insn ((c), (s))
+extern bool bpf_tc_equal_in_insn (int, char *);
diff --git a/gas/configure b/gas/configure
index 86d90abf4e6..dbb3425b678 100755
--- a/gas/configure
+++ b/gas/configure
@@ -12301,7 +12301,6 @@ cat >>confdefs.h <<_ACEOF
 _ACEOF
 
 	fi
-        using_cgen=yes
         ;;
       epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
 	using_cgen=yes
diff --git a/gas/configure.ac b/gas/configure.ac
index 96eeb78db76..13adaad6123 100644
--- a/gas/configure.ac
+++ b/gas/configure.ac
@@ -454,7 +454,6 @@ changequote([,])dnl
       	if test $this_target = $target ; then
 	  AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
 	fi
-        using_cgen=yes
         ;;
       epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k)
 	using_cgen=yes
diff --git a/gas/doc/c-bpf.texi b/gas/doc/c-bpf.texi
index 0756796adc9..4742f89ea17 100644
--- a/gas/doc/c-bpf.texi
+++ b/gas/doc/c-bpf.texi
@@ -15,15 +15,15 @@
 
 @cindex BPF support
 @menu
-* BPF Options::                 Options
-* BPF Syntax::		        Syntax
-* BPF Directives::		Machine Directives
-* BPF Opcodes::			Opcodes
-* BPF Pseudo-C Syntax::         Alternative Pseudo-C Assembly Syntax
+* BPF Options::                 BPF specific command-line options.
+* BPF Special Characters::      Comments and statements.
+* BPF Registers::               Register names.
+* BPF Directives::		Machine directives.
+* BPF Instructions::            Machine instructions.
 @end menu
 
 @node BPF Options
-@section Options
+@section BPF Options
 @cindex BPF options (none)
 @cindex options for BPF (none)
 
@@ -38,22 +38,29 @@ This option specifies that the assembler should emit big-endian eBPF.
 @item -EL
 This option specifies that the assembler should emit little-endian
 eBPF.
+
+@cindex @option{-mdialect} command-line options, BPF
+@item -mdialect=@var{dialect}
+This option specifies the assembly language dialect to recognize while
+assembling.  The assembler supports @option{normal} and
+@option{pseudoc}.
+
+@cindex @option{-misa-spec} command-line options, BPF
+@item -misa-spec=@var{spec}
+This option specifies the version of the BPF instruction set to use
+when assembling.  The BPF ISA versions supported are @option{v1} @option{v2}, @option{v3} and @option{v4}.
+
+The value @option{xbpf} can be specified to recognize extra
+instructions that are used by GCC for testing purposes.  But beware
+this is not valid BPF.
 @end table
 
 Note that if no endianness option is specified in the command line,
 the host endianness is used.
 @c man end
 
-@node BPF Syntax
-@section Syntax
-@menu
-* BPF-Chars::                Special Characters
-* BPF-Regs::                 Register Names
-* BPF-Pseudo-Maps::	     Pseudo map fds
-@end menu
-
-@node BPF-Chars
-@subsection Special Characters
+@node BPF Special Characters
+@section BPF Special Characters
 
 @cindex line comment character, BPF
 @cindex BPF line comment character
@@ -64,50 +71,49 @@ the first character of a line, the whole line is treated as a comment.
 @cindex statement separator, BPF
 Statements and assembly directives are separated by newlines.
 
-@node BPF-Regs
-@subsection Register Names
+@node BPF Registers
+@section BPF Registers
 
 @cindex BPF register names
 @cindex register names, BPF
 The eBPF processor provides ten general-purpose 64-bit registers,
 which are read-write, and a read-only frame pointer register:
 
+@noindent
+In normal syntax:
+
 @table @samp
 @item %r0 .. %r9
 General-purpose registers.
 @item %r10
-Frame pointer register.
+@itemx %fp
+Read-only frame pointer register.
 @end table
 
-Some registers have additional names, to reflect their role in the
-eBPF ABI:
+All BPF registers are 64-bit long.  However, in the Pseudo-C syntax
+registers can be referred using different names, which actually
+reflect the kind of instruction they appear on:
+
+@noindent
+In pseudoc syntax:
 
 @table @samp
-@item %a
-This is @samp{%r0}.
-@item %ctx
-This is @samp{%r6}.
-@item %fp
-This is @samp{%r10}.
+@item r0..r9
+General-purpose register in an instruction that operates on its value
+as if it was a 64-bit value.
+@item w0..w9
+General-purpose register in an instruction that operates on its value
+as if it was a 32-bit value.
+@item r10
+Read-only frame pointer register.
 @end table
 
-@node BPF-Pseudo-Maps
-@subsection Pseudo Maps
-
-@cindex pseudo map fd, BPF
-The @samp{LDDW} instruction can take a literal pseudo map file
-descriptor as its second argument.  This uses the syntax
-@samp{%map_fd(N)} where @samp{N} is a signed number.
-
-For example, to load the address of the pseudo map with file
-descriptor @samp{2} in register @samp{r1} we would do:
-
-@smallexample
-        lddw %r1, %map_fd(2)
-@end smallexample
+@noindent
+Note that in the Pseudo-C syntax register names are not preceded by
+@code{%} characters.
 
 @node BPF Directives
-@section Machine Directives
+@section BPF Directives
 
 @cindex machine directives, BPF
 
@@ -128,8 +134,8 @@ The @code{.word} directive produces a 32 bit value.
 The @code{.dword} directive produces a 64 bit value.
 @end table
 
-@node BPF Opcodes
-@section Opcodes
+@node BPF Instructions
+@section BPF Instructions
 
 @cindex BPF opcodes
 @cindex opcodes for BPF
@@ -137,10 +143,10 @@ In the instruction descriptions below the following field descriptors
 are used:
 
 @table @code
-@item %d
-Destination general-purpose register whose role is to be destination
-of an operation.
-@item %s
+@item rd
+Destination general-purpose register whose role is to be the
+destination of an operation.
+@item rs
 Source general-purpose register whose role is to be the source of an
 operation.
 @item disp16
@@ -150,104 +156,237 @@ minus one.
 32-bit signed PC-relative offset, measured in number of 64-bit words,
 minus one.
 @item offset16
-Signed 16-bit immediate.
+Signed 16-bit immediate representing an offset in bytes.
+@item disp16
+Signed 16-bit immediate representing a displacement to a target,
+measured in number of 64-bit words @emph{minus one}.
 @item imm32
 Signed 32-bit immediate.
 @item imm64
 Signed 64-bit immediate.
 @end table
 
-@subsubsection Arithmetic instructions
+@subsection Arithmetic instructions
 
 The destination register in these instructions act like an
 accumulator.
 
+Note that in pseudoc syntax these instructions should use @code{r}
+registers.
+
 @table @code
-@item add %d, (%s|imm32)
+@item add rd, rs
+@itemx add rd, imm32
+@itemx rd += rs
+@itemx rd += imm32
 64-bit arithmetic addition.
-@item sub %d, (%s|imm32)
+
+@item sub rd, rs
+@itemx sub rd, rs
+@itemx rd -= rs
+@itemx rd -= imm32
 64-bit arithmetic subtraction.
-@item mul %d, (%s|imm32)
+
+@item mul rd, rs
+@itemx mul rd, imm32
+@itemx rd *= rs
+@itemx rd *= imm32
 64-bit arithmetic multiplication.
-@item div %d, (%s|imm32)
+
+@item div rd, rs
+@itemx div rd, imm32
+@itemx rd /= rs
+@itemx rd /= imm32
 64-bit arithmetic integer division.
-@item mod %d, (%s|imm32)
+
+@item mod rd, rs
+@itemx mod rd, imm32
+@itemx rd %= rs
+@itemx rd %= imm32
 64-bit integer remainder.
-@item and %d, (%s|imm32)
+
+@item and rd, rs
+@itemx and rd, imm32
+@itemx rd &= rs
+@itemx rd &= imm32
 64-bit bit-wise ``and'' operation.
-@item or %d, (%s|imm32)
+
+@item or rd, rs
+@itemx or rd, imm32
+@itemx rd |= rs
+@itemx rd |= imm32
 64-bit bit-wise ``or'' operation.
-@item xor %d, (%s|imm32)
+
+@item xor rd, imm32
+@itemx xor rd, rs
+@itemx rd ^= rs
+@itemx rd ^= imm32
 64-bit bit-wise exclusive-or operation.
-@item lsh %d, (%s|imm32)
-64-bit left shift, by @code{%s} or @code{imm32} bits.
-@item rsh %d, (%s|imm32)
-64-bit right logical shift, by @code{%s} or @code{imm32} bits.
-@item arsh %d, (%s|imm32)
-64-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
-@item neg %d
+
+@item lsh rd, rs
+@itemx ldh rd, imm32
+@itemx rd <<= rs
+@itemx rd <<= imm32
+64-bit left shift, by @code{rs} or @code{imm32} bits.
+
+@item rsh %d, %s
+@itemx rsh rd, imm32
+@itemx rd >>= rs
+@itemx rd >>= imm32
+64-bit right logical shift, by @code{rs} or @code{imm32} bits.
+
+@item arsh rd, rs
+@itemx arsh rd, imm32
+@itemx rd s>>= rs
+@itemx rd s>>= imm32
+64-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
+
+@item neg rd, rs
+@itemx neg rd, imm32
+@itemx rd = - rs
+@itemx rd = - imm32
 64-bit arithmetic negation.
-@item mov %d, (%s|imm32)
-Move the 64-bit value of @code{%s} in @code{%d}, or load @code{imm32}
-in @code{%d}.
+
+Note that in the @code{rd = - imm32} syntax there must be at least
+one white space between @code{-} and @code{imm32}.  Otherwise the
+instruction is parsed as a @code{mov rd, imm32} instruction with a
+negative 32-bit immediate.  This is a consequence of a syntactic
+ambiguity in the pseudoc syntax.
+
+@item mov rd, rs
+@itemx mov rd, imm32
+@itemx rd = rs
+@itemx rd = imm32
+Move the 64-bit value of @code{rs} in @code{rd}, or load @code{imm32}
+in @code{rd}.
 @end table
 
-@subsubsection 32-bit arithmetic instructions
+@subsection 32-bit arithmetic instructions
 
 The destination register in these instructions act as an accumulator.
 
+Note that in pseudoc syntax these instructions should use @code{w}
+registers.  It is not allowed to mix @code{w} and @code{r} registers
+in the same instruction.
+
 @table @code
-@item add32 %d, (%s|imm32)
+@item add32 rd, rs
+@itemx add32 rd, imm32
+@itemx rd += rs
+@itemx rd += imm32
 32-bit arithmetic addition.
-@item sub32 %d, (%s|imm32)
+
+@item sub32 rd, rs
+@itemx sub32 rd, imm32
+@itemx rd -= rs
+@itemx rd += imm32
 32-bit arithmetic subtraction.
-@item mul32 %d, (%s|imm32)
+
+@item mul32 rd, rs
+@itemx mul32 rd, imm32
+@itemx rd *= rs
+@itemx rd *= imm32
 32-bit arithmetic multiplication.
-@item div32 %d, (%s|imm32)
+
+@item div32 rd, rs
+@itemx div32 rd, imm32
+@itemx rd /= rs
+@itemx rd /= imm32
 32-bit arithmetic integer division.
-@item mod32 %d, (%s|imm32)
+
+@item mod32 rd, rs
+@itemx mod32 rd, imm32
+@itemx rd %= rs
+@itemx rd %= imm32
 32-bit integer remainder.
-@item and32 %d, (%s|imm32)
+
+@item and32 rd, rs
+@itemx and32 rd, imm32
+@itemx rd &= rs
+@itemx rd &= imm32
 32-bit bit-wise ``and'' operation.
-@item or32 %d, (%s|imm32)
+
+@item or32 rd, rs
+@itemx or32 rd, imm32
+@itemx rd |= rs
+@itemx rd |= imm32
 32-bit bit-wise ``or'' operation.
-@item xor32 %d, (%s|imm32)
+
+@item xor32 rd, rs
+@itemx xor32 rd, imm32
+@itemx rd ^= rs
+@itemx rd ^= imm32
 32-bit bit-wise exclusive-or operation.
-@item lsh32 %d, (%s|imm32)
-32-bit left shift, by @code{%s} or @code{imm32} bits.
-@item rsh32 %d, (%s|imm32)
-32-bit right logical shift, by @code{%s} or @code{imm32} bits.
-@item arsh32 %d, (%s|imm32)
-32-bit right arithmetic shift, by @code{%s} or @code{imm32} bits.
-@item neg32 %d
+
+@item lsh32 rd, rs
+@itemx lsh32 rd, imm32
+@itemx rd <<= rs
+@itemx rd <<= imm32
+32-bit left shift, by @code{rs} or @code{imm32} bits.
+
+@item rsh32 rd, rs
+@itemx rsh32 rd, imm32
+@itemx rd >>= rs
+@itemx rd >>= imm32
+32-bit right logical shift, by @code{rs} or @code{imm32} bits.
+
+@item arsh32 rd, rs
+@itemx arsh32 rd, imm32
+@itemx rd s>>= rs
+@itemx rd s>>= imm32
+32-bit right arithmetic shift, by @code{rs} or @code{imm32} bits.
+
+@item neg32 rd, rs
+@itemx neg32 rd, imm32
+@itemx rd = - rs
+@itemx rd = - imm32
 32-bit arithmetic negation.
-@item mov32 %d, (%s|imm32)
-Move the 32-bit value of @code{%s} in @code{%d}, or load @code{imm32}
-in @code{%d}.
+
+Note that in the @code{rd = - imm32} syntax there must be at least
+one white space between @code{-} and @code{imm32}.  Otherwise the
+instruction is parsed as a @code{mov32 rd, imm32} instruction with a
+negative 32-bit immediate.  This is a consequence of a syntactic
+ambiguity in the pseudoc syntax.
+
+@item mov32 rd, rs
+@itemx mov32 rd, imm32
+@itemx rd = rs
+@itemx rd = imm32
+Move the 32-bit value of @code{rs} in @code{rd}, or load @code{imm32}
+in @code{rd}.
 @end table
 
-@subsubsection Endianness conversion instructions
+@subsection Endianness conversion instructions
 
 @table @code
-@item endle %d, (16|32|64)
-Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to
-little-endian.
-@item endbe %d, (16|32|64)
-Convert the 16-bit, 32-bit or 64-bit value in @code{%d} to big-endian.
+@item endle rd, 16
+@itemx endle rd, 32
+@itemx endle rd, 64
+@itemx rd = le16 rd
+@itemx rd = le32 rd
+@itemx rd = le64 rd
+Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to
+little-endian and store it back in @code{rd}.
+@item endbe %d, 16
+@itemx endbe %d, 32
+@itemx endbe %d, 64
+@itemx rd = be16 rd
+@itemx rd = be32 rd
+@itemx rd = be64 rd
+Convert the 16-bit, 32-bit or 64-bit value in @code{rd} to big-endian
+and store it back in @code{rd}.
 @end table
 
-@subsubsection 64-bit load and pseudo maps
+@subsection 64-bit load and pseudo maps
 
 @table @code
-@item lddw %d, imm64
-Load the given signed 64-bit immediate, or pseudo map descriptor, to
-the destination register @code{%d}.
-@item lddw %d, %map_fd(N)
-Load the address of the given pseudo map fd @emph{N} to the
-destination register @code{%d}.
+@item lddw rd, imm64
+@itemx rd = imm64 ll
+Load the given signed 64-bit immediate to the destination register
+@code{rd}.
 @end table
 
-@subsubsection Load instructions for socket filters
+@subsection Load instructions for socket filters
 
 The following instructions are intended to be used in socket filters,
 and are therefore not general-purpose: they make assumptions on the
@@ -259,29 +398,43 @@ Absolute loads:
 
 @table @code
 @item ldabsdw imm32
+@itemx r0 = *(u64 *) skb[imm32]
 Absolute 64-bit load.
+
 @item ldabsw imm32
+@itemx r0 = *(u32 *) skb[imm32]
 Absolute 32-bit load.
+
 @item ldabsh imm32
+@itemx r0 = *(u16 *) skb[imm32]
 Absolute 16-bit load.
+
 @item ldabsb imm32
+@itemx r0 = *(u8 *) skb[imm32]
 Absolute 8-bit load.
 @end table
 
 Indirect loads:
 
 @table @code
-@item ldinddw %s, imm32
+@item ldinddw rs, imm32
+@itemx r0 = *(u64 *) skb[rs + imm32]
 Indirect 64-bit load.
-@item ldindw %s, imm32
+
+@item ldindw rs, imm32
+@itemx r0 = *(u32 *) skb[rs + imm32]
 Indirect 32-bit load.
-@item ldindh %s, imm32
+
+@item ldindh rs, imm32
+@itemx r0 = *(u16 *) skb[rs + imm32]
 Indirect 16-bit load.
+
 @item ldindb %s, imm32
+@itemx r0 = *(u8 *) skb[rs + imm32]
 Indirect 8-bit load.
 @end table
 
-@subsubsection Generic load/store instructions
+@subsection Generic load/store instructions
 
 General-purpose load and store instructions are provided for several
 word sizes.
@@ -289,43 +442,64 @@ word sizes.
 Load to register instructions:
 
 @table @code
-@item ldxdw %d, [%s+offset16]
+@item ldxdw rd, [rs + offset16]
+@itemx rd = *(u64 *) (rs + offset16)
 Generic 64-bit load.
-@item ldxw %d, [%s+offset16]
+
+@item ldxw rd, [rs + offset16]
+@itemx rd = *(u32 *) (rs + offset16)
 Generic 32-bit load.
-@item ldxh %d, [%s+offset16]
+
+@item ldxh rd, [rs + offset16]
+@itemx rd = *(u16 *) (rs + offset16)
 Generic 16-bit load.
-@item ldxb %d, [%s+offset16]
+
+@item ldxb rd, [rs + offset16]
+@itemx rd = *(u8 *) (rs + offset16)
 Generic 8-bit load.
 @end table
 
 Store from register instructions:
 
 @table @code
-@item stxdw [%d+offset16], %s
+@item stxdw [rd + offset16], %s
+@itemx *(u64 *) (rd + offset16)
 Generic 64-bit store.
-@item stxw [%d+offset16], %s
+
+@item stxw [rd + offset16], %s
+@itemx *(u32 *) (rd + offset16)
 Generic 32-bit store.
-@item stxh [%d+offset16], %s
+
+@item stxh [rd + offset16], %s
+@itemx *(u16 *) (rd + offset16)
 Generic 16-bit store.
-@item stxb [%d+offset16], %s
+
+@item stxb [rd + offset16], %s
+@itemx *(u8 *) (rd + offset16)
 Generic 8-bit store.
 @end table
 
 Store from immediates instructions:
 
 @table @code
-@item stddw [%d+offset16], imm32
+@item stdw [rd + offset16], imm32
+@itemx *(u64 *) (rd + offset16) = imm32
 Store immediate as 64-bit.
-@item stdw [%d+offset16], imm32
+
+@item stw [rd + offset16], imm32
+@itemx *(u32 *) (rd + offset16) = imm32
 Store immediate as 32-bit.
-@item stdh [%d+offset16], imm32
+
+@item sth [rd + offset16], imm32
+@itemx *(u16 *) (rd + offset16) = imm32
 Store immediate as 16-bit.
-@item stdb [%d+offset16], imm32
+
+@item stb [rd + offset16], imm32
+@itemx *(u8 *) (rd + offset16) = imm32
 Store immediate as 8-bit.
 @end table
 
-@subsubsection Jump instructions
+@subsection Jump instructions
 
 eBPF provides the following compare-and-jump instructions, which
 compare the values of the two given registers, or the values of a
@@ -333,29 +507,74 @@ register and an immediate, and perform a branch in case the comparison
 holds true.
 
 @table @code
-@item ja %d,(%s|imm32),disp16
+@item ja disp16
+@itemx goto disp16
 Jump-always.
-@item jeq %d,(%s|imm32),disp16
+
+@item jeq rd, rs, disp16
+@itemx jeq rd, imm32, disp16
+@itemx if rd == rs goto disp16
+@itemx if rd == imm32 goto disp16
 Jump if equal, unsigned.
-@item jgt %d,(%s|imm32),disp16
+
+@item jgt rd, rs, disp16
+@itemx jgt rd, imm32, disp16
+@itemx if rd > rs goto disp16
+@itemx if rd > imm32 goto disp16
 Jump if greater, unsigned.
-@item jge %d,(%s|imm32),disp16
+
+@item jge rd, rs, disp16
+@itemx jge rd, imm32, disp16
+@itemx if rd >= rs goto disp16
+@itemx if rd >= imm32 goto disp16
 Jump if greater or equal.
-@item jlt %d,(%s|imm32),disp16
+
+@item jlt rd, rs, disp16
+@itemx jlt rd, imm32, disp16
+@itemx if rd < rs goto disp16
+@itemx if rd < imm32 goto disp16
 Jump if lesser.
-@item jle %d,(%s|imm32),disp16
+
+@item jle rd , rs, disp16
+@itemx jle rd, imm32, disp16
+@itemx if rd <= rs goto disp16
+@itemx if rd <= imm32 goto disp16
 Jump if lesser or equal.
-@item jset %d,(%s|imm32),disp16
+
+@item jset rd, rs, disp16
+@itemx jset rd, imm32, disp16
+@itemx if rd & rs goto disp16
+@itemx if rd & imm32 goto disp16
 Jump if signed equal.
-@item jne %d,(%s|imm32),disp16
+
+@item jne rd, rs, disp16
+@itemx jne rd, imm32, disp16
+@itemx if rd != rs goto disp16
+@itemx if rd != imm32 goto disp16
 Jump if not equal.
-@item jsgt %d,(%s|imm32),disp16
+
+@item jsgt rd, rs, disp16
+@itemx jsgt rd, imm32, disp16
+@itemx if rd s> rs goto disp16
+@itemx if rd s> imm32 goto disp16
 Jump if signed greater.
-@item jsge %d,(%s|imm32),disp16
+
+@item jsge rd, rs, disp16
+@itemx jsge rd, imm32, disp16
+@itemx if rd s>= rd goto disp16
+@itemx if rd s>= imm32 goto disp16
 Jump if signed greater or equal.
-@item jslt %d,(%s|imm32),disp16
+
+@item jslt rd, rs, disp16
+@itemx jslt rd, imm32, disp16
+@itemx if rd s< rs goto disp16
+@itemx if rd s< imm32 goto disp16
 Jump if signed lesser.
-@item jsle %d,(%s|imm32),disp16
+
+@item jsle rd, rs, disp16
+@itemx jsle rd, imm32, disp16
+@itemx if rd s<= rs goto disp16
+@itemx if rd s<= imm32 goto disp16
 Jump if signed lesser or equal.
 @end table
 
@@ -363,7 +582,8 @@ A call instruction is provided in order to perform calls to other eBPF
 functions, or to external kernel helpers:
 
 @table @code
-@item call (disp32|imm32)
+@item call disp32
+@item call imm32
 Jump and link to the offset @emph{disp32}, or to the kernel helper
 function identified by @emph{imm32}.
 @end table
@@ -375,203 +595,187 @@ Finally:
 Terminate the eBPF program.
 @end table
 
-@subsubsection Atomic instructions
+@subsection 32-bit jump instructions
 
-Atomic exchange-and-add instructions are provided in two flavors: one
-for swapping 64-bit quantities and another for 32-bit quantities.
+eBPF provides the following compare-and-jump instructions, which
+compare the 32-bit values of the two given registers, or the values of
+a register and an immediate, and perform a branch in case the
+comparison holds true.
 
-@table @code
-@item xadddw [%d+offset16],%s
-Exchange-and-add a 64-bit value at the specified location.
-@item xaddw [%d+offset16],%s
-Exchange-and-add a 32-bit value at the specified location.
-@end table
+These instructions are only available in BPF v3 or later.
 
-@node BPF Pseudo-C Syntax
-@section BPF Pseudo-C Syntax
+@table @code
+@item jeq32 rd, rs, disp16
+@itemx jeq32 rd, imm32, disp16
+@itemx if rd == rs goto disp16
+@itemx if rd == imm32 goto disp16
+Jump if equal, unsigned.
 
-This assembler supports another syntax to denote BPF instructions,
-which is an alternative to the normal looking syntax documented above.
-This alternatative syntax, which we call @dfn{pseudo-C syntax}, is
-supported by the LLVM/clang integrated assembler.
+@item jgt32 rd, rs, disp16
+@itemx jgt32 rd, imm32, disp16
+@itemx if rd > rs goto disp16
+@itemx if rd > imm32 goto disp16
+Jump if greater, unsigned.
 
-This syntax is very unconventional, but we need to support it in order
-to support inline assembly in existing BPF programs.
+@item jge32 rd, rs, disp16
+@itemx jge32 rd, imm32, disp16
+@itemx if rd >= rs goto disp16
+@itemx if rd >= imm32 goto disp16
+Jump if greater or equal.
 
-Note that the assembler is able to parse sources in which both
-syntaxes coexist: some instructions can use the usual assembly like
-syntax, whereas some other instructions in the same file can use the
-pseudo-C syntax.
+@item jlt32 rd, rs, disp16
+@itemx jlt32 rd, imm32, disp16
+@itemx if rd < rs goto disp16
+@itemx if rd < imm32 goto disp16
+Jump if lesser.
 
-@subsubsection Pseudo-C Register Names
+@item jle32 rd , rs, disp16
+@itemx jle32 rd, imm32, disp16
+@itemx if rd <= rs goto disp16
+@itemx if rd <= imm32 goto disp16
+Jump if lesser or equal.
 
-All BPF registers are 64-bit long.  However, in the Pseudo-C syntax
-registers can be referred using different names, which actually
-reflect the kind of instruction they appear on:
+@item jset32 rd, rs, disp16
+@itemx jset32 rd, imm32, disp16
+@itemx if rd & rs goto disp16
+@itemx if rd & imm32 goto disp16
+Jump if signed equal.
 
-@table @samp
-@item r0..r9
-General-purpose register in an instruction that operates on its value
-as if it was a 64-bit value.
-@item w0..w9
-General-purpose register in an instruction that operates on its value
-as if it was a 32-bit value.
-@end table
+@item jne32 rd, rs, disp16
+@itemx jne32 rd, imm32, disp16
+@itemx if rd != rs goto disp16
+@itemx if rd != imm32 goto disp16
+Jump if not equal.
 
-@noindent
-Note that in the Pseudo-C syntax register names are not preceded by
-@code{%} characters.
+@item jsgt32 rd, rs, disp16
+@itemx jsgt32 rd, imm32, disp16
+@itemx if rd s> rs goto disp16
+@itemx if rd s> imm32 goto disp16
+Jump if signed greater.
 
-@subsubsection Arithmetic instructions
+@item jsge32 rd, rs, disp16
+@itemx jsge32 rd, imm32, disp16
+@itemx if rd s>= rd goto disp16
+@itemx if rd s>= imm32 goto disp16
+Jump if signed greater or equal.
 
-In all the instructions below, the operations are 64-bit or 32-bit
-depending on the names used to refer to the registers.  For example
-@code{r3 += r2} will perform 64-bit addition, whereas @code{w3 += w2}
-will perform 32-bit addition.  Mixing register prefixes is an error,
-for example @code{r3 += w2}.
+@item jslt32 rd, rs, disp16
+@itemx jslt32 rd, imm32, disp16
+@itemx if rd s< rs goto disp16
+@itemx if rd s< imm32 goto disp16
+Jump if signed lesser.
 
-@table @code
-@item dst_reg += (imm32|src_reg)
-Arithmetic addition.
-@item dst_reg -= (imm32|src_reg)
-Arithmetic subtraction.
-@item dst_reg *= (imm32|src_reg)
-Arithmetic multiplication.
-@item dst_reg /= (imm32|src_reg)
-Arithmetic integer unsigned division.
-@item dst_reg %= (imm32|src_reg)
-Arithmetic integer unsigned remainder.
-@item dst_reg &= (imm32|src_reg)
-Bit-wise ``and'' operation.
-@item dst_reg |= (imm32|src_reg)
-Bit-wise ``or'' operation.
-@item dst_reg ^= (imm32|src_reg)
-Bit-wise exclusive-or operation.
-@item dst_reg <<= (imm32|src_reg)
-Left shift, by whatever specified number of bits.
-@item dst_reg >>= (imm32|src_reg)
-Right logical shift, by whatever specified number of bits.
-@item dst_reg s>>= (imm32|src_reg)
-Right arithmetic shift, by whatever specified number of bits.
-@item dst_reg = (imm32|src_reg)
-Move the value in @code{imm32} or @code{src_reg} in @code{dst_reg}.
-@item dst_reg = -dst_reg
-Arithmetic negation.
+@item jsle32 rd, rs, disp16
+@itemx jsle32 rd, imm32, disp16
+@itemx if rd s<= rs goto disp16
+@itemx if rd s<= imm32 goto disp16
+Jump if signed lesser or equal.
 @end table
 
-@subsubsection Endianness conversion instructions
+@subsection Atomic instructions
+
+Atomic exchange-and-add instructions are provided in two flavors: one
+for swapping 64-bit quantities and another for 32-bit quantities.
 
 @table @code
-@item dst_reg = le16 src_reg
-Convert the 16-bit value in @code{src_reg} to little-endian.
-@item dst_reg = le32 src_reg
-Convert the 32-bit value in @code{src_reg} to little-endian.
-@item dst_reg = le64 src_reg
-Convert the 64-bit value in @code{src_reg} to little-endian.
-@item dst_reg = be16 src_reg
-Convert the 16-bit value in @code{src_reg} to big-endian.
-@item dst_reg = be32 src_reg
-Convert the 32-bit value in @code{src_reg} to big-endian.
-@item dst_reg = be64 src_reg
-Convert the 64-bit value in @code{src_reg} to big-endian.
+@item aadd [rd + offset16], rs
+@itemx *(u64 *)(rd + offset16) = rs
+Atomic add instruction.
+
+@item aor [rd + offset16], rs
+@itemx *(u64 *) (rd + offset16) |= rs
+Atomic or instruction.
+
+@item aand [rd + offset16], rs
+@itemx *(u64 *) (rd + offset16) &= rs
+Atomic and instruction.
+
+@item axor [rd + offset16], rs
+@itemx *(u64 *) (rd + offset16) ^= rs
+Atomic xor instruction
+@item xaddw [%d+offset16],%s
+Exchange-and-add a 32-bit value at the specified location.
 @end table
 
-@subsubsection 64-bit load and pseudo maps
+@noindent
+The following variants perform fetching before the atomic operation.
 
 @table @code
-@item dst_reg = imm64 ll
-Load the given signed 64-bit immediate, or pseudo map descriptor, to
-the destination register @code{dst_reg}.
+@item afadd [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-add instruction.
+
+@item afor [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-or instruction.
+
+@item afand [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-and instruction.
+
+@item afxor [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-or instruction
 @end table
 
-@subsubsection Load instructions for socket filters
+The above instructions were introduced in the V3 of the BPF
+instruction set.  The following instruction is supported for backwards
+compatibility:
 
 @table @code
-@item r0 = *(u8 *)skb[imm32]
-Absolute 8-bit load.
-@item r0 = *(u16 *)skb[imm32]
-Absolute 16-bit load.
-@item r0 = *(u32 *)skb[imm32]
-Absolute 32-bit load.
-@item r0 = *(u64 *)skb[imm32]
-Absolute 64-bit load.
-@item r0 = *(u8 *)skb[src_reg + imm32]
-Indirect 8-bit load.
-@item r0 = *(u16 *)skb[src_reg + imm32]
-Indirect 16-bit load.
-@item r0 = *(u32 *)skb[src_reg + imm32]
-Indirect 32-bit load.
-@item r0 = *(u64 *)skb[src_reg + imm32]
-Indirect 64-bit load.
+@item xadddw [rd + offset16], rs
+Alias to @code{aadd}.
 @end table
 
-@subsubsection Generic load/store instructions
+@subsection 32-bit atomic instructions
+
+Atomic exchange-and-add instructions are provided in two flavors: one
+for swapping 32-bit quantities and another for 32-bit quantities.
 
 @table @code
-@item dst_reg = *(u8 *)(src_reg + offset16)
-Generic 8-bit load.
-@item dst_reg = *(u16 *)(src_reg + offset16)
-Generic 16-bit load.
-@item dst_reg = *(u32 *)(src_reg + offset16)
-Generic 32-bit load.
-@item dst_reg = *(u64 *)(src_reg + offset16)
-Generic 64-bit load.
-@c XXX stb
-@c NO PSEUDOC-SYNTAX
-@c XXX sth
-@c NO PSEUDOC-SYNTAX
-@c XXX stw
-@c NO PSEUDOC-SYNTAX
-@c XXX stdw
-@c NO PSEUDOC-SYNTAX
-@item *(u8 *)(dst_reg + offset16) = src_reg
-Generic 8-bit store.
-@item *(u16 *)(dst_reg + offset16) = src_reg
-Generic 16-bit store.
-@item *(u32 *)(dst_reg + offset16) = src_reg
-Generic 32-bit store.
-@item *(u64 *)(dst_reg + offset16) = src_reg
-Generic 64-bit store.
+@item aadd32 [rd + offset16], rs
+@itemx *(u32 *)(rd + offset16) = rs
+Atomic add instruction.
+
+@item aor32 [rd + offset16], rs
+@itemx *(u32 *) (rd + offset16) |= rs
+Atomic or instruction.
+
+@item aand32 [rd + offset16], rs
+@itemx *(u32 *) (rd + offset16) &= rs
+Atomic and instruction.
+
+@item axor32 [rd + offset16], rs
+@itemx *(u32 *) (rd + offset16) ^= rs
+Atomic xor instruction
 @end table
 
-@subsubsection Jump instructions
+@noindent
+The following variants perform fetching before the atomic operation.
 
 @table @code
-@item goto disp16
-Jump-always.
-@item if dst_reg == (imm32|src_reg) goto disp16
-Jump if equal.
-@item if dst_reg & (imm32|src_reg) goto disp16
-Jump if signed equal.
-@item if dst_reg != (imm32|src_reg) goto disp16
-Jump if not equal.
-@item if dst_reg > (imm32|src_reg) goto disp16
-Jump if bigger, unsigned.
-@item if dst_reg < (imm32|src_reg) goto disp16
-Jump if smaller, unsigned.
-@item if dst_reg >= (imm32|src_reg) goto disp16
-Jump if bigger or equal, unsigned.
-@item if dst_reg <= (imm32|src_reg) goto disp16
-Jump if smaller or equal, unsigned.
-@item if dst_reg s> (imm32|src_reg) goto disp16
-Jump if bigger, signed.
-@item if dst_reg s< (imm32|src_reg) goto disp16
-Jump if smaller, signed.
-@item if dst_reg s>= (imm32|src_reg) goto disp16
-Jump if bigger or equal, signed.
-@item if dst_reg s<= (imm32|src_reg) goto disp16
-Jump if smaller or equal, signed.
-@item call imm32
-Jump and link.
-@item exit
-Terminate the eBPF program.
+@item afadd32 [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-add instruction.
+
+@item afor32 [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-or instruction.
+
+@item afand32 [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-and instruction.
+
+@item afxor32 [dr + offset16], rs
+@itemx ???
+Atomic fetch-and-or instruction
 @end table
 
-@subsubsection Atomic instructions
+The above instructions were introduced in the V3 of the BPF
+instruction set.  The following instruction is supported for backwards
+compatibility:
 
 @table @code
-@item lock *(u64 *)(dst_reg + offset16) += src_reg
-Exchange-and-add a 64-bit value at the specified location.
-@item lock *(u32 *)(dst_reg + offset16) += src_reg
-Exchange-and-add a 32-bit value at the specified location.
+@item xaddw [rd + offset16], rs
+Alias to @code{aadd32}.
 @end table
diff --git a/gas/testsuite/gas/all/assign-bad-recursive.d b/gas/testsuite/gas/all/assign-bad-recursive.d
index 678be3e7c9f..aeec5d55f8a 100644
--- a/gas/testsuite/gas/all/assign-bad-recursive.d
+++ b/gas/testsuite/gas/all/assign-bad-recursive.d
@@ -1,5 +1,4 @@
 #name: bad recursive assignments
 #source: assign-bad-recursive.s
 #xfail: bfin-*-*
-#notarget: *bpf-*-*
 #error_output: assign-bad-recursive.l
diff --git a/gas/testsuite/gas/all/eqv-dot.d b/gas/testsuite/gas/all/eqv-dot.d
index d97db14995e..fc40b09f217 100644
--- a/gas/testsuite/gas/all/eqv-dot.d
+++ b/gas/testsuite/gas/all/eqv-dot.d
@@ -2,7 +2,7 @@
 #name: eqv involving dot
 # bfin doesn't support 'symbol = expression'
 # tic30 and tic4x have 4 octets per byte, tic54x has 2 octets per byte
-#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-* *bpf-*-*
+#notarget: bfin-*-* *c30-*-* *c4x-*-* *c54x-*-*
 # linkrelax targets don't handle equivalence expressions well (nor any
 # other forward expression).  mep uses complex relocs
 #xfail: am33_2.0-*-* crx-*-* h8300-*-* mn10200-*-* mn10300-*-* mep-*-*
diff --git a/gas/testsuite/gas/all/gas.exp b/gas/testsuite/gas/all/gas.exp
index bab5a6c7ba5..007408f03d8 100644
--- a/gas/testsuite/gas/all/gas.exp
+++ b/gas/testsuite/gas/all/gas.exp
@@ -105,7 +105,7 @@ if { [istarget "pdp11-*-*"] } then {
     run_dump_test eqv-dot
 }
 
-if { ![istarget "bfin-*-*"] && ![istarget "bpf-*-*"]  } then {
+if { ![istarget "bfin-*-*"] } then {
     gas_test "assign-ok.s" "" "" "== assignment support"
 }
 gas_test_error "assign-bad.s" "" "== assignment for symbol already set"
@@ -403,8 +403,7 @@ if {  ([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-openbsd*"]) \
   gas_test "fastcall.s" ""   "" "fastcall labels"
 }
 
-if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] \
-    && ![istarget "bpf-*-*"] } then {
+if { ![istarget "bfin-*-*"] && ![istarget "nds32*-*-*"] } then {
     run_dump_test assign
 }
 run_dump_test sleb128
diff --git a/gas/testsuite/gas/bpf/alu-be-pseudoc.d b/gas/testsuite/gas/bpf/alu-be-pseudoc.d
index 0355d196d77..8d8c29e91c7 100644
--- a/gas/testsuite/gas/bpf/alu-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu-be-pseudoc.d
@@ -1,5 +1,65 @@
-#as: --EB
+#as: -EB -mdialect=pseudoc
 #source: alu-pseudoc.s
-#objdump: -dr
-#dump: alu-be.dump
+#objdump: -dr -M hex,pseudoc
 #name: eBPF ALU64 instructions, big endian, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	07 20 00 00 00 00 02 9a 	r2\+=0x29a
+   8:	07 30 00 00 ff ff fd 66 	r3\+=0xfffffd66
+  10:	07 40 00 00 7e ad be ef 	r4\+=0x7eadbeef
+  18:	0f 56 00 00 00 00 00 00 	r5\+=r6
+  20:	17 20 00 00 00 00 02 9a 	r2-=0x29a
+  28:	17 30 00 00 ff ff fd 66 	r3-=0xfffffd66
+  30:	17 40 00 00 7e ad be ef 	r4-=0x7eadbeef
+  38:	1f 56 00 00 00 00 00 00 	r5-=r6
+  40:	27 20 00 00 00 00 02 9a 	r2\*=0x29a
+  48:	27 30 00 00 ff ff fd 66 	r3\*=0xfffffd66
+  50:	27 40 00 00 7e ad be ef 	r4\*=0x7eadbeef
+  58:	2f 56 00 00 00 00 00 00 	r5\*=r6
+  60:	37 20 00 00 00 00 02 9a 	r2/=0x29a
+  68:	37 30 00 00 ff ff fd 66 	r3/=0xfffffd66
+  70:	37 40 00 00 7e ad be ef 	r4/=0x7eadbeef
+  78:	3f 56 00 00 00 00 00 00 	r5/=r6
+  80:	47 20 00 00 00 00 02 9a 	r2|=0x29a
+  88:	47 30 00 00 ff ff fd 66 	r3|=0xfffffd66
+  90:	47 40 00 00 7e ad be ef 	r4|=0x7eadbeef
+  98:	4f 56 00 00 00 00 00 00 	r5|=r6
+  a0:	57 20 00 00 00 00 02 9a 	r2&=0x29a
+  a8:	57 30 00 00 ff ff fd 66 	r3&=0xfffffd66
+  b0:	57 40 00 00 7e ad be ef 	r4&=0x7eadbeef
+  b8:	5f 56 00 00 00 00 00 00 	r5&=r6
+  c0:	67 20 00 00 00 00 02 9a 	r2<<=0x29a
+  c8:	67 30 00 00 ff ff fd 66 	r3<<=0xfffffd66
+  d0:	67 40 00 00 7e ad be ef 	r4<<=0x7eadbeef
+  d8:	6f 56 00 00 00 00 00 00 	r5<<=r6
+  e0:	77 20 00 00 00 00 02 9a 	r2>>=0x29a
+  e8:	77 30 00 00 ff ff fd 66 	r3>>=0xfffffd66
+  f0:	77 40 00 00 7e ad be ef 	r4>>=0x7eadbeef
+  f8:	7f 56 00 00 00 00 00 00 	r5>>=r6
+ 100:	97 20 00 00 00 00 02 9a 	r2%=0x29a
+ 108:	97 30 00 00 ff ff fd 66 	r3%=0xfffffd66
+ 110:	97 40 00 00 7e ad be ef 	r4%=0x7eadbeef
+ 118:	9f 56 00 00 00 00 00 00 	r5%=r6
+ 120:	a7 20 00 00 00 00 02 9a 	r2\^=0x29a
+ 128:	a7 30 00 00 ff ff fd 66 	r3\^=0xfffffd66
+ 130:	a7 40 00 00 7e ad be ef 	r4\^=0x7eadbeef
+ 138:	af 56 00 00 00 00 00 00 	r5\^=r6
+ 140:	b7 20 00 00 00 00 02 9a 	r2=0x29a
+ 148:	b7 30 00 00 ff ff fd 66 	r3=0xfffffd66
+ 150:	b7 40 00 00 7e ad be ef 	r4=0x7eadbeef
+ 158:	bf 56 00 00 00 00 00 00 	r5=r6
+ 160:	c7 20 00 00 00 00 02 9a 	r2 s>>=0x29a
+ 168:	c7 30 00 00 ff ff fd 66 	r3 s>>=0xfffffd66
+ 170:	c7 40 00 00 7e ad be ef 	r4 s>>=0x7eadbeef
+ 178:	cf 56 00 00 00 00 00 00 	r5 s>>=r6
+ 180:	8f 23 00 00 00 00 00 00 	r2=-r3
+ 188:	d4 90 00 00 00 00 00 10 	r9=le16 r9
+ 190:	d4 80 00 00 00 00 00 20 	r8=le32 r8
+ 198:	d4 70 00 00 00 00 00 40 	r7=le64 r7
+ 1a0:	dc 60 00 00 00 00 00 10 	r6=be16 r6
+ 1a8:	dc 50 00 00 00 00 00 20 	r5=be32 r5
+ 1b0:	dc 40 00 00 00 00 00 40 	r4=be64 r4
diff --git a/gas/testsuite/gas/bpf/alu-be.d b/gas/testsuite/gas/bpf/alu-be.d
index afd2a6cfd6d..170db4b853d 100644
--- a/gas/testsuite/gas/bpf/alu-be.d
+++ b/gas/testsuite/gas/bpf/alu-be.d
@@ -1,5 +1,65 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: alu.s
-#objdump: -dr
-#dump: alu-be.dump
-#name: eBPF ALU64 instructions, big endian, normal syntax
+#objdump: -dr -M hex
+#name: eBPF ALU instructions, big endian, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	07 20 00 00 00 00 02 9a 	add %r2,0x29a
+   8:	07 30 00 00 ff ff fd 66 	add %r3,0xfffffd66
+  10:	07 40 00 00 7e ad be ef 	add %r4,0x7eadbeef
+  18:	0f 56 00 00 00 00 00 00 	add %r5,%r6
+  20:	17 20 00 00 00 00 02 9a 	sub %r2,0x29a
+  28:	17 30 00 00 ff ff fd 66 	sub %r3,0xfffffd66
+  30:	17 40 00 00 7e ad be ef 	sub %r4,0x7eadbeef
+  38:	1f 56 00 00 00 00 00 00 	sub %r5,%r6
+  40:	27 20 00 00 00 00 02 9a 	mul %r2,0x29a
+  48:	27 30 00 00 ff ff fd 66 	mul %r3,0xfffffd66
+  50:	27 40 00 00 7e ad be ef 	mul %r4,0x7eadbeef
+  58:	2f 56 00 00 00 00 00 00 	mul %r5,%r6
+  60:	37 20 00 00 00 00 02 9a 	div %r2,0x29a
+  68:	37 30 00 00 ff ff fd 66 	div %r3,0xfffffd66
+  70:	37 40 00 00 7e ad be ef 	div %r4,0x7eadbeef
+  78:	3f 56 00 00 00 00 00 00 	div %r5,%r6
+  80:	47 20 00 00 00 00 02 9a 	or %r2,0x29a
+  88:	47 30 00 00 ff ff fd 66 	or %r3,0xfffffd66
+  90:	47 40 00 00 7e ad be ef 	or %r4,0x7eadbeef
+  98:	4f 56 00 00 00 00 00 00 	or %r5,%r6
+  a0:	57 20 00 00 00 00 02 9a 	and %r2,0x29a
+  a8:	57 30 00 00 ff ff fd 66 	and %r3,0xfffffd66
+  b0:	57 40 00 00 7e ad be ef 	and %r4,0x7eadbeef
+  b8:	5f 56 00 00 00 00 00 00 	and %r5,%r6
+  c0:	67 20 00 00 00 00 02 9a 	lsh %r2,0x29a
+  c8:	67 30 00 00 ff ff fd 66 	lsh %r3,0xfffffd66
+  d0:	67 40 00 00 7e ad be ef 	lsh %r4,0x7eadbeef
+  d8:	6f 56 00 00 00 00 00 00 	lsh %r5,%r6
+  e0:	77 20 00 00 00 00 02 9a 	rsh %r2,0x29a
+  e8:	77 30 00 00 ff ff fd 66 	rsh %r3,0xfffffd66
+  f0:	77 40 00 00 7e ad be ef 	rsh %r4,0x7eadbeef
+  f8:	7f 56 00 00 00 00 00 00 	rsh %r5,%r6
+ 100:	97 20 00 00 00 00 02 9a 	mod %r2,0x29a
+ 108:	97 30 00 00 ff ff fd 66 	mod %r3,0xfffffd66
+ 110:	97 40 00 00 7e ad be ef 	mod %r4,0x7eadbeef
+ 118:	9f 56 00 00 00 00 00 00 	mod %r5,%r6
+ 120:	a7 20 00 00 00 00 02 9a 	xor %r2,0x29a
+ 128:	a7 30 00 00 ff ff fd 66 	xor %r3,0xfffffd66
+ 130:	a7 40 00 00 7e ad be ef 	xor %r4,0x7eadbeef
+ 138:	af 56 00 00 00 00 00 00 	xor %r5,%r6
+ 140:	b7 20 00 00 00 00 02 9a 	mov %r2,0x29a
+ 148:	b7 30 00 00 ff ff fd 66 	mov %r3,0xfffffd66
+ 150:	b7 40 00 00 7e ad be ef 	mov %r4,0x7eadbeef
+ 158:	bf 56 00 00 00 00 00 00 	mov %r5,%r6
+ 160:	c7 20 00 00 00 00 02 9a 	arsh %r2,0x29a
+ 168:	c7 30 00 00 ff ff fd 66 	arsh %r3,0xfffffd66
+ 170:	c7 40 00 00 7e ad be ef 	arsh %r4,0x7eadbeef
+ 178:	cf 56 00 00 00 00 00 00 	arsh %r5,%r6
+ 180:	8f 23 00 00 00 00 00 00 	neg %r2,%r3
+ 188:	d4 90 00 00 00 00 00 10 	endle %r9,16
+ 190:	d4 80 00 00 00 00 00 20 	endle %r8,32
+ 198:	d4 70 00 00 00 00 00 40 	endle %r7,64
+ 1a0:	dc 60 00 00 00 00 00 10 	endbe %r6,16
+ 1a8:	dc 50 00 00 00 00 00 20 	endbe %r5,32
+ 1b0:	dc 40 00 00 00 00 00 40 	endbe %r4,64
diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.d b/gas/testsuite/gas/bpf/alu-pseudoc.d
index df130699b4f..5d69e68a4f0 100644
--- a/gas/testsuite/gas/bpf/alu-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu-pseudoc.d
@@ -1,5 +1,65 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
 #source: alu-pseudoc.s
-#dump: alu.dump
-#name: eBPF ALU64 instructions, pseudo-c syntax
+#name: eBPF ALU instructions, pseudo-c syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	07 02 00 00 9a 02 00 00 	r2\+=0x29a
+   8:	07 03 00 00 66 fd ff ff 	r3\+=0xfffffd66
+  10:	07 04 00 00 ef be ad 7e 	r4\+=0x7eadbeef
+  18:	0f 65 00 00 00 00 00 00 	r5\+=r6
+  20:	17 02 00 00 9a 02 00 00 	r2-=0x29a
+  28:	17 03 00 00 66 fd ff ff 	r3-=0xfffffd66
+  30:	17 04 00 00 ef be ad 7e 	r4-=0x7eadbeef
+  38:	1f 65 00 00 00 00 00 00 	r5-=r6
+  40:	27 02 00 00 9a 02 00 00 	r2\*=0x29a
+  48:	27 03 00 00 66 fd ff ff 	r3\*=0xfffffd66
+  50:	27 04 00 00 ef be ad 7e 	r4\*=0x7eadbeef
+  58:	2f 65 00 00 00 00 00 00 	r5\*=r6
+  60:	37 02 00 00 9a 02 00 00 	r2/=0x29a
+  68:	37 03 00 00 66 fd ff ff 	r3/=0xfffffd66
+  70:	37 04 00 00 ef be ad 7e 	r4/=0x7eadbeef
+  78:	3f 65 00 00 00 00 00 00 	r5/=r6
+  80:	47 02 00 00 9a 02 00 00 	r2|=0x29a
+  88:	47 03 00 00 66 fd ff ff 	r3|=0xfffffd66
+  90:	47 04 00 00 ef be ad 7e 	r4|=0x7eadbeef
+  98:	4f 65 00 00 00 00 00 00 	r5|=r6
+  a0:	57 02 00 00 9a 02 00 00 	r2&=0x29a
+  a8:	57 03 00 00 66 fd ff ff 	r3&=0xfffffd66
+  b0:	57 04 00 00 ef be ad 7e 	r4&=0x7eadbeef
+  b8:	5f 65 00 00 00 00 00 00 	r5&=r6
+  c0:	67 02 00 00 9a 02 00 00 	r2<<=0x29a
+  c8:	67 03 00 00 66 fd ff ff 	r3<<=0xfffffd66
+  d0:	67 04 00 00 ef be ad 7e 	r4<<=0x7eadbeef
+  d8:	6f 65 00 00 00 00 00 00 	r5<<=r6
+  e0:	77 02 00 00 9a 02 00 00 	r2>>=0x29a
+  e8:	77 03 00 00 66 fd ff ff 	r3>>=0xfffffd66
+  f0:	77 04 00 00 ef be ad 7e 	r4>>=0x7eadbeef
+  f8:	7f 65 00 00 00 00 00 00 	r5>>=r6
+ 100:	97 02 00 00 9a 02 00 00 	r2%=0x29a
+ 108:	97 03 00 00 66 fd ff ff 	r3%=0xfffffd66
+ 110:	97 04 00 00 ef be ad 7e 	r4%=0x7eadbeef
+ 118:	9f 65 00 00 00 00 00 00 	r5%=r6
+ 120:	a7 02 00 00 9a 02 00 00 	r2\^=0x29a
+ 128:	a7 03 00 00 66 fd ff ff 	r3\^=0xfffffd66
+ 130:	a7 04 00 00 ef be ad 7e 	r4\^=0x7eadbeef
+ 138:	af 65 00 00 00 00 00 00 	r5\^=r6
+ 140:	b7 02 00 00 9a 02 00 00 	r2=0x29a
+ 148:	b7 03 00 00 66 fd ff ff 	r3=0xfffffd66
+ 150:	b7 04 00 00 ef be ad 7e 	r4=0x7eadbeef
+ 158:	bf 65 00 00 00 00 00 00 	r5=r6
+ 160:	c7 02 00 00 9a 02 00 00 	r2 s>>=0x29a
+ 168:	c7 03 00 00 66 fd ff ff 	r3 s>>=0xfffffd66
+ 170:	c7 04 00 00 ef be ad 7e 	r4 s>>=0x7eadbeef
+ 178:	cf 65 00 00 00 00 00 00 	r5 s>>=r6
+ 180:	8f 32 00 00 00 00 00 00 	r2=-r3
+ 188:	d4 09 00 00 10 00 00 00 	r9=le16 r9
+ 190:	d4 08 00 00 20 00 00 00 	r8=le32 r8
+ 198:	d4 07 00 00 40 00 00 00 	r7=le64 r7
+ 1a0:	dc 06 00 00 10 00 00 00 	r6=be16 r6
+ 1a8:	dc 05 00 00 20 00 00 00 	r5=be32 r5
+ 1b0:	dc 04 00 00 40 00 00 00 	r4=be64 r4
diff --git a/gas/testsuite/gas/bpf/alu-pseudoc.s b/gas/testsuite/gas/bpf/alu-pseudoc.s
index 0f79929ea0d..a271bef977d 100644
--- a/gas/testsuite/gas/bpf/alu-pseudoc.s
+++ b/gas/testsuite/gas/bpf/alu-pseudoc.s
@@ -48,4 +48,10 @@
 	r3 s>>= -666
 	r4 s>>= 2125315823
 	r5 s>>= r6
-	r2 = -r2
+	r2 = - r3
+	r9 = le16 r9
+	r8 = le32 r8
+	r7 = le64 r7
+	r6 = be16 r6
+	r5 = be32 r5
+	r4 = be64 r4
diff --git a/gas/testsuite/gas/bpf/alu.d b/gas/testsuite/gas/bpf/alu.d
index 764ae440d8f..476891b9afd 100644
--- a/gas/testsuite/gas/bpf/alu.d
+++ b/gas/testsuite/gas/bpf/alu.d
@@ -1,5 +1,65 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
 #source: alu.s
-#dump: alu.dump
-#name: eBPF ALU64 instructions, normal syntax
+#name: eBPF ALU instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	07 02 00 00 9a 02 00 00 	add %r2,0x29a
+   8:	07 03 00 00 66 fd ff ff 	add %r3,0xfffffd66
+  10:	07 04 00 00 ef be ad 7e 	add %r4,0x7eadbeef
+  18:	0f 65 00 00 00 00 00 00 	add %r5,%r6
+  20:	17 02 00 00 9a 02 00 00 	sub %r2,0x29a
+  28:	17 03 00 00 66 fd ff ff 	sub %r3,0xfffffd66
+  30:	17 04 00 00 ef be ad 7e 	sub %r4,0x7eadbeef
+  38:	1f 65 00 00 00 00 00 00 	sub %r5,%r6
+  40:	27 02 00 00 9a 02 00 00 	mul %r2,0x29a
+  48:	27 03 00 00 66 fd ff ff 	mul %r3,0xfffffd66
+  50:	27 04 00 00 ef be ad 7e 	mul %r4,0x7eadbeef
+  58:	2f 65 00 00 00 00 00 00 	mul %r5,%r6
+  60:	37 02 00 00 9a 02 00 00 	div %r2,0x29a
+  68:	37 03 00 00 66 fd ff ff 	div %r3,0xfffffd66
+  70:	37 04 00 00 ef be ad 7e 	div %r4,0x7eadbeef
+  78:	3f 65 00 00 00 00 00 00 	div %r5,%r6
+  80:	47 02 00 00 9a 02 00 00 	or %r2,0x29a
+  88:	47 03 00 00 66 fd ff ff 	or %r3,0xfffffd66
+  90:	47 04 00 00 ef be ad 7e 	or %r4,0x7eadbeef
+  98:	4f 65 00 00 00 00 00 00 	or %r5,%r6
+  a0:	57 02 00 00 9a 02 00 00 	and %r2,0x29a
+  a8:	57 03 00 00 66 fd ff ff 	and %r3,0xfffffd66
+  b0:	57 04 00 00 ef be ad 7e 	and %r4,0x7eadbeef
+  b8:	5f 65 00 00 00 00 00 00 	and %r5,%r6
+  c0:	67 02 00 00 9a 02 00 00 	lsh %r2,0x29a
+  c8:	67 03 00 00 66 fd ff ff 	lsh %r3,0xfffffd66
+  d0:	67 04 00 00 ef be ad 7e 	lsh %r4,0x7eadbeef
+  d8:	6f 65 00 00 00 00 00 00 	lsh %r5,%r6
+  e0:	77 02 00 00 9a 02 00 00 	rsh %r2,0x29a
+  e8:	77 03 00 00 66 fd ff ff 	rsh %r3,0xfffffd66
+  f0:	77 04 00 00 ef be ad 7e 	rsh %r4,0x7eadbeef
+  f8:	7f 65 00 00 00 00 00 00 	rsh %r5,%r6
+ 100:	97 02 00 00 9a 02 00 00 	mod %r2,0x29a
+ 108:	97 03 00 00 66 fd ff ff 	mod %r3,0xfffffd66
+ 110:	97 04 00 00 ef be ad 7e 	mod %r4,0x7eadbeef
+ 118:	9f 65 00 00 00 00 00 00 	mod %r5,%r6
+ 120:	a7 02 00 00 9a 02 00 00 	xor %r2,0x29a
+ 128:	a7 03 00 00 66 fd ff ff 	xor %r3,0xfffffd66
+ 130:	a7 04 00 00 ef be ad 7e 	xor %r4,0x7eadbeef
+ 138:	af 65 00 00 00 00 00 00 	xor %r5,%r6
+ 140:	b7 02 00 00 9a 02 00 00 	mov %r2,0x29a
+ 148:	b7 03 00 00 66 fd ff ff 	mov %r3,0xfffffd66
+ 150:	b7 04 00 00 ef be ad 7e 	mov %r4,0x7eadbeef
+ 158:	bf 65 00 00 00 00 00 00 	mov %r5,%r6
+ 160:	c7 02 00 00 9a 02 00 00 	arsh %r2,0x29a
+ 168:	c7 03 00 00 66 fd ff ff 	arsh %r3,0xfffffd66
+ 170:	c7 04 00 00 ef be ad 7e 	arsh %r4,0x7eadbeef
+ 178:	cf 65 00 00 00 00 00 00 	arsh %r5,%r6
+ 180:	8f 32 00 00 00 00 00 00 	neg %r2,%r3
+ 188:	d4 09 00 00 10 00 00 00 	endle %r9,16
+ 190:	d4 08 00 00 20 00 00 00 	endle %r8,32
+ 198:	d4 07 00 00 40 00 00 00 	endle %r7,64
+ 1a0:	dc 06 00 00 10 00 00 00 	endbe %r6,16
+ 1a8:	dc 05 00 00 20 00 00 00 	endbe %r5,32
+ 1b0:	dc 04 00 00 40 00 00 00 	endbe %r4,64
diff --git a/gas/testsuite/gas/bpf/alu.s b/gas/testsuite/gas/bpf/alu.s
index 18e60d5eaed..bb3f9265200 100644
--- a/gas/testsuite/gas/bpf/alu.s
+++ b/gas/testsuite/gas/bpf/alu.s
@@ -48,4 +48,10 @@
         arsh	%r3, -666
         arsh	%r4, 0x7eadbeef
         arsh	%r5, %r6
-        neg     %r2
+        neg     %r2, %r3
+	endle	%r9,16
+        endle	%r8,32
+        endle	%r7,64
+        endbe	%r6,16
+        endbe	%r5,32
+        endbe	%r4,64
diff --git a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
index 396d7d40603..6daad3b6926 100644
--- a/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu32-be-pseudoc.d
@@ -1,5 +1,59 @@
-#as: --EB
-#objdump: -dr
+#as: -EB -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
 #source: alu32-pseudoc.s
-#dump: alu32-be.dump
-#name: eBPF ALU instructions, big-endian, pseudo-c syntax
+#name: eBPF ALU32 instructions, big-endian, pseudo-c syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	04 20 00 00 00 00 02 9a 	w2\+=0x29a
+   8:	04 30 00 00 ff ff fd 66 	w3\+=0xfffffd66
+  10:	04 40 00 00 7e ad be ef 	w4\+=0x7eadbeef
+  18:	0c 56 00 00 00 00 00 00 	w5\+=w6
+  20:	14 20 00 00 00 00 02 9a 	w2-=0x29a
+  28:	14 30 00 00 ff ff fd 66 	w3-=0xfffffd66
+  30:	14 40 00 00 7e ad be ef 	w4-=0x7eadbeef
+  38:	1c 56 00 00 00 00 00 00 	w5-=w6
+  40:	24 20 00 00 00 00 02 9a 	w2\*=0x29a
+  48:	24 30 00 00 ff ff fd 66 	w3\*=0xfffffd66
+  50:	24 40 00 00 7e ad be ef 	w4\*=0x7eadbeef
+  58:	2c 56 00 00 00 00 00 00 	w5\*=w6
+  60:	34 20 00 00 00 00 02 9a 	w2/=0x29a
+  68:	34 30 00 00 ff ff fd 66 	w3/=0xfffffd66
+  70:	34 40 00 00 7e ad be ef 	w4/=0x7eadbeef
+  78:	3c 56 00 00 00 00 00 00 	w5/=w6
+  80:	44 20 00 00 00 00 02 9a 	w2|=0x29a
+  88:	44 30 00 00 ff ff fd 66 	w3|=0xfffffd66
+  90:	44 40 00 00 7e ad be ef 	w4|=0x7eadbeef
+  98:	4c 56 00 00 00 00 00 00 	w5|=w6
+  a0:	54 20 00 00 00 00 02 9a 	w2&=0x29a
+  a8:	54 30 00 00 ff ff fd 66 	w3&=0xfffffd66
+  b0:	54 40 00 00 7e ad be ef 	w4&=0x7eadbeef
+  b8:	5c 56 00 00 00 00 00 00 	w5&=w6
+  c0:	64 20 00 00 00 00 02 9a 	w2<<=0x29a
+  c8:	64 30 00 00 ff ff fd 66 	w3<<=0xfffffd66
+  d0:	64 40 00 00 7e ad be ef 	w4<<=0x7eadbeef
+  d8:	6c 56 00 00 00 00 00 00 	w5<<=w6
+  e0:	74 20 00 00 00 00 02 9a 	w2>>=0x29a
+  e8:	74 30 00 00 ff ff fd 66 	w3>>=0xfffffd66
+  f0:	74 40 00 00 7e ad be ef 	w4>>=0x7eadbeef
+  f8:	7c 56 00 00 00 00 00 00 	w5>>=w6
+ 100:	94 20 00 00 00 00 02 9a 	w2%=0x29a
+ 108:	94 30 00 00 ff ff fd 66 	w3%=0xfffffd66
+ 110:	94 40 00 00 7e ad be ef 	w4%=0x7eadbeef
+ 118:	9c 56 00 00 00 00 00 00 	w5%=w6
+ 120:	a4 20 00 00 00 00 02 9a 	w2\^=0x29a
+ 128:	a4 30 00 00 ff ff fd 66 	w3\^=0xfffffd66
+ 130:	a4 40 00 00 7e ad be ef 	w4\^=0x7eadbeef
+ 138:	ac 56 00 00 00 00 00 00 	w5\^=w6
+ 140:	b4 20 00 00 00 00 02 9a 	w2=0x29a
+ 148:	b4 30 00 00 ff ff fd 66 	w3=0xfffffd66
+ 150:	b4 40 00 00 7e ad be ef 	w4=0x7eadbeef
+ 158:	bc 56 00 00 00 00 00 00 	w5=w6
+ 160:	c4 20 00 00 00 00 02 9a 	w2 s>>=0x29a
+ 168:	c4 30 00 00 ff ff fd 66 	w3 s>>=0xfffffd66
+ 170:	c4 40 00 00 7e ad be ef 	w4 s>>=0x7eadbeef
+ 178:	cc 56 00 00 00 00 00 00 	w5 s>>=w6
+ 180:	8c 23 00 00 00 00 00 00 	w2=-w3
diff --git a/gas/testsuite/gas/bpf/alu32-be.d b/gas/testsuite/gas/bpf/alu32-be.d
index 6ed9e556bf4..6de8f0660d8 100644
--- a/gas/testsuite/gas/bpf/alu32-be.d
+++ b/gas/testsuite/gas/bpf/alu32-be.d
@@ -1,5 +1,59 @@
-#as: --EB
-#objdump: -dr
-#source: alu32-pseudoc.s
-#dump: alu32-be.dump
-#name: eBPF ALU instructions, big-endian, normal syntax
+#as: -EB -mdialect=normal
+#objdump: -dr -M hex
+#source: alu32.s
+#name: eBPF ALU32 instructions, big-endian, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	04 20 00 00 00 00 02 9a 	add32 %r2,0x29a
+   8:	04 30 00 00 ff ff fd 66 	add32 %r3,0xfffffd66
+  10:	04 40 00 00 7e ad be ef 	add32 %r4,0x7eadbeef
+  18:	0c 56 00 00 00 00 00 00 	add32 %r5,%r6
+  20:	14 20 00 00 00 00 02 9a 	sub32 %r2,0x29a
+  28:	14 30 00 00 ff ff fd 66 	sub32 %r3,0xfffffd66
+  30:	14 40 00 00 7e ad be ef 	sub32 %r4,0x7eadbeef
+  38:	1c 56 00 00 00 00 00 00 	sub32 %r5,%r6
+  40:	24 20 00 00 00 00 02 9a 	mul32 %r2,0x29a
+  48:	24 30 00 00 ff ff fd 66 	mul32 %r3,0xfffffd66
+  50:	24 40 00 00 7e ad be ef 	mul32 %r4,0x7eadbeef
+  58:	2c 56 00 00 00 00 00 00 	mul32 %r5,%r6
+  60:	34 20 00 00 00 00 02 9a 	div32 %r2,0x29a
+  68:	34 30 00 00 ff ff fd 66 	div32 %r3,0xfffffd66
+  70:	34 40 00 00 7e ad be ef 	div32 %r4,0x7eadbeef
+  78:	3c 56 00 00 00 00 00 00 	div32 %r5,%r6
+  80:	44 20 00 00 00 00 02 9a 	or32 %r2,0x29a
+  88:	44 30 00 00 ff ff fd 66 	or32 %r3,0xfffffd66
+  90:	44 40 00 00 7e ad be ef 	or32 %r4,0x7eadbeef
+  98:	4c 56 00 00 00 00 00 00 	or32 %r5,%r6
+  a0:	54 20 00 00 00 00 02 9a 	and32 %r2,0x29a
+  a8:	54 30 00 00 ff ff fd 66 	and32 %r3,0xfffffd66
+  b0:	54 40 00 00 7e ad be ef 	and32 %r4,0x7eadbeef
+  b8:	5c 56 00 00 00 00 00 00 	and32 %r5,%r6
+  c0:	64 20 00 00 00 00 02 9a 	lsh32 %r2,0x29a
+  c8:	64 30 00 00 ff ff fd 66 	lsh32 %r3,0xfffffd66
+  d0:	64 40 00 00 7e ad be ef 	lsh32 %r4,0x7eadbeef
+  d8:	6c 56 00 00 00 00 00 00 	lsh32 %r5,%r6
+  e0:	74 20 00 00 00 00 02 9a 	rsh32 %r2,0x29a
+  e8:	74 30 00 00 ff ff fd 66 	rsh32 %r3,0xfffffd66
+  f0:	74 40 00 00 7e ad be ef 	rsh32 %r4,0x7eadbeef
+  f8:	7c 56 00 00 00 00 00 00 	rsh32 %r5,%r6
+ 100:	94 20 00 00 00 00 02 9a 	mod32 %r2,0x29a
+ 108:	94 30 00 00 ff ff fd 66 	mod32 %r3,0xfffffd66
+ 110:	94 40 00 00 7e ad be ef 	mod32 %r4,0x7eadbeef
+ 118:	9c 56 00 00 00 00 00 00 	mod32 %r5,%r6
+ 120:	a4 20 00 00 00 00 02 9a 	xor32 %r2,0x29a
+ 128:	a4 30 00 00 ff ff fd 66 	xor32 %r3,0xfffffd66
+ 130:	a4 40 00 00 7e ad be ef 	xor32 %r4,0x7eadbeef
+ 138:	ac 56 00 00 00 00 00 00 	xor32 %r5,%r6
+ 140:	b4 20 00 00 00 00 02 9a 	mov32 %r2,0x29a
+ 148:	b4 30 00 00 ff ff fd 66 	mov32 %r3,0xfffffd66
+ 150:	b4 40 00 00 7e ad be ef 	mov32 %r4,0x7eadbeef
+ 158:	bc 56 00 00 00 00 00 00 	mov32 %r5,%r6
+ 160:	c4 20 00 00 00 00 02 9a 	arsh32 %r2,0x29a
+ 168:	c4 30 00 00 ff ff fd 66 	arsh32 %r3,0xfffffd66
+ 170:	c4 40 00 00 7e ad be ef 	arsh32 %r4,0x7eadbeef
+ 178:	cc 56 00 00 00 00 00 00 	arsh32 %r5,%r6
+ 180:	8c 23 00 00 00 00 00 00 	neg32 %r2,%r3
diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.d b/gas/testsuite/gas/bpf/alu32-pseudoc.d
index 98b99215b27..f339c808d26 100644
--- a/gas/testsuite/gas/bpf/alu32-pseudoc.d
+++ b/gas/testsuite/gas/bpf/alu32-pseudoc.d
@@ -1,5 +1,59 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
 #source: alu32-pseudoc.s
-#dump: alu32.dump
-#name: eBPF ALU instructions, pseudo-c syntax
+#name: eBPF ALU32 instructions, pseudo-c syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	04 02 00 00 9a 02 00 00 	w2\+=0x29a
+   8:	04 03 00 00 66 fd ff ff 	w3\+=0xfffffd66
+  10:	04 04 00 00 ef be ad 7e 	w4\+=0x7eadbeef
+  18:	0c 65 00 00 00 00 00 00 	w5\+=w6
+  20:	14 02 00 00 9a 02 00 00 	w2-=0x29a
+  28:	14 03 00 00 66 fd ff ff 	w3-=0xfffffd66
+  30:	14 04 00 00 ef be ad 7e 	w4-=0x7eadbeef
+  38:	1c 65 00 00 00 00 00 00 	w5-=w6
+  40:	24 02 00 00 9a 02 00 00 	w2\*=0x29a
+  48:	24 03 00 00 66 fd ff ff 	w3\*=0xfffffd66
+  50:	24 04 00 00 ef be ad 7e 	w4\*=0x7eadbeef
+  58:	2c 65 00 00 00 00 00 00 	w5\*=w6
+  60:	34 02 00 00 9a 02 00 00 	w2/=0x29a
+  68:	34 03 00 00 66 fd ff ff 	w3/=0xfffffd66
+  70:	34 04 00 00 ef be ad 7e 	w4/=0x7eadbeef
+  78:	3c 65 00 00 00 00 00 00 	w5/=w6
+  80:	44 02 00 00 9a 02 00 00 	w2|=0x29a
+  88:	44 03 00 00 66 fd ff ff 	w3|=0xfffffd66
+  90:	44 04 00 00 ef be ad 7e 	w4|=0x7eadbeef
+  98:	4c 65 00 00 00 00 00 00 	w5|=w6
+  a0:	54 02 00 00 9a 02 00 00 	w2&=0x29a
+  a8:	54 03 00 00 66 fd ff ff 	w3&=0xfffffd66
+  b0:	54 04 00 00 ef be ad 7e 	w4&=0x7eadbeef
+  b8:	5c 65 00 00 00 00 00 00 	w5&=w6
+  c0:	64 02 00 00 9a 02 00 00 	w2<<=0x29a
+  c8:	64 03 00 00 66 fd ff ff 	w3<<=0xfffffd66
+  d0:	64 04 00 00 ef be ad 7e 	w4<<=0x7eadbeef
+  d8:	6c 65 00 00 00 00 00 00 	w5<<=w6
+  e0:	74 02 00 00 9a 02 00 00 	w2>>=0x29a
+  e8:	74 03 00 00 66 fd ff ff 	w3>>=0xfffffd66
+  f0:	74 04 00 00 ef be ad 7e 	w4>>=0x7eadbeef
+  f8:	7c 65 00 00 00 00 00 00 	w5>>=w6
+ 100:	94 02 00 00 9a 02 00 00 	w2%=0x29a
+ 108:	94 03 00 00 66 fd ff ff 	w3%=0xfffffd66
+ 110:	94 04 00 00 ef be ad 7e 	w4%=0x7eadbeef
+ 118:	9c 65 00 00 00 00 00 00 	w5%=w6
+ 120:	a4 02 00 00 9a 02 00 00 	w2\^=0x29a
+ 128:	a4 03 00 00 66 fd ff ff 	w3\^=0xfffffd66
+ 130:	a4 04 00 00 ef be ad 7e 	w4\^=0x7eadbeef
+ 138:	ac 65 00 00 00 00 00 00 	w5\^=w6
+ 140:	b4 02 00 00 9a 02 00 00 	w2=0x29a
+ 148:	b4 03 00 00 66 fd ff ff 	w3=0xfffffd66
+ 150:	b4 04 00 00 ef be ad 7e 	w4=0x7eadbeef
+ 158:	bc 65 00 00 00 00 00 00 	w5=w6
+ 160:	c4 02 00 00 9a 02 00 00 	w2 s>>=0x29a
+ 168:	c4 03 00 00 66 fd ff ff 	w3 s>>=0xfffffd66
+ 170:	c4 04 00 00 ef be ad 7e 	w4 s>>=0x7eadbeef
+ 178:	cc 65 00 00 00 00 00 00 	w5 s>>=w6
+ 180:	8c 32 00 00 00 00 00 00 	w2=-w3
diff --git a/gas/testsuite/gas/bpf/alu32-pseudoc.s b/gas/testsuite/gas/bpf/alu32-pseudoc.s
index a29f6ea0336..0a0d41fdf46 100644
--- a/gas/testsuite/gas/bpf/alu32-pseudoc.s
+++ b/gas/testsuite/gas/bpf/alu32-pseudoc.s
@@ -1,16 +1,16 @@
 # Tests for the ALU eBPF pseudo-C instructions
         .text
-	W2 += 666
-	W3 += -666
-	W4 += 2125315823
-	W5 += w6
-	W2 -= 666
-	W3 -= -666
-	W4 -= 2125315823
-	W5 -= w6
-	W2 *= 666
-	W3 *= -666
-	W4 *= 2125315823
+	w2 += 666
+	w3 += -666
+	w4 += 2125315823
+	w5 += w6
+	w2 -= 666
+	w3 -= -666
+	w4 -= 2125315823
+	w5 -= w6
+	w2 *= 666
+	w3 *= -666
+	w4 *= 2125315823
 	w5 *= w6
 	w2 /= 666
 	w3 /= -666
@@ -48,10 +48,4 @@
 	w3 s>>= -666
 	w4 s>>= 2125315823
 	w5 s>>= w6
-	w2 = -w2
-	r9 = le16 r9
-	r8 = le32 r8
-	r7 = le64 r7
-	r6 = be16 r6
-	r5 = be32 r5
-	r4 = be64 r4
+	w2 = - w3
diff --git a/gas/testsuite/gas/bpf/alu32.d b/gas/testsuite/gas/bpf/alu32.d
index 87efc20ba30..712d1c7328e 100644
--- a/gas/testsuite/gas/bpf/alu32.d
+++ b/gas/testsuite/gas/bpf/alu32.d
@@ -1,5 +1,59 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
 #source: alu32.s
-#dump: alu32.dump
-#name: eBPF ALU instructions, normal syntax
+#name: eBPF ALU32 instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	04 02 00 00 9a 02 00 00 	add32 %r2,0x29a
+   8:	04 03 00 00 66 fd ff ff 	add32 %r3,0xfffffd66
+  10:	04 04 00 00 ef be ad 7e 	add32 %r4,0x7eadbeef
+  18:	0c 65 00 00 00 00 00 00 	add32 %r5,%r6
+  20:	14 02 00 00 9a 02 00 00 	sub32 %r2,0x29a
+  28:	14 03 00 00 66 fd ff ff 	sub32 %r3,0xfffffd66
+  30:	14 04 00 00 ef be ad 7e 	sub32 %r4,0x7eadbeef
+  38:	1c 65 00 00 00 00 00 00 	sub32 %r5,%r6
+  40:	24 02 00 00 9a 02 00 00 	mul32 %r2,0x29a
+  48:	24 03 00 00 66 fd ff ff 	mul32 %r3,0xfffffd66
+  50:	24 04 00 00 ef be ad 7e 	mul32 %r4,0x7eadbeef
+  58:	2c 65 00 00 00 00 00 00 	mul32 %r5,%r6
+  60:	34 02 00 00 9a 02 00 00 	div32 %r2,0x29a
+  68:	34 03 00 00 66 fd ff ff 	div32 %r3,0xfffffd66
+  70:	34 04 00 00 ef be ad 7e 	div32 %r4,0x7eadbeef
+  78:	3c 65 00 00 00 00 00 00 	div32 %r5,%r6
+  80:	44 02 00 00 9a 02 00 00 	or32 %r2,0x29a
+  88:	44 03 00 00 66 fd ff ff 	or32 %r3,0xfffffd66
+  90:	44 04 00 00 ef be ad 7e 	or32 %r4,0x7eadbeef
+  98:	4c 65 00 00 00 00 00 00 	or32 %r5,%r6
+  a0:	54 02 00 00 9a 02 00 00 	and32 %r2,0x29a
+  a8:	54 03 00 00 66 fd ff ff 	and32 %r3,0xfffffd66
+  b0:	54 04 00 00 ef be ad 7e 	and32 %r4,0x7eadbeef
+  b8:	5c 65 00 00 00 00 00 00 	and32 %r5,%r6
+  c0:	64 02 00 00 9a 02 00 00 	lsh32 %r2,0x29a
+  c8:	64 03 00 00 66 fd ff ff 	lsh32 %r3,0xfffffd66
+  d0:	64 04 00 00 ef be ad 7e 	lsh32 %r4,0x7eadbeef
+  d8:	6c 65 00 00 00 00 00 00 	lsh32 %r5,%r6
+  e0:	74 02 00 00 9a 02 00 00 	rsh32 %r2,0x29a
+  e8:	74 03 00 00 66 fd ff ff 	rsh32 %r3,0xfffffd66
+  f0:	74 04 00 00 ef be ad 7e 	rsh32 %r4,0x7eadbeef
+  f8:	7c 65 00 00 00 00 00 00 	rsh32 %r5,%r6
+ 100:	94 02 00 00 9a 02 00 00 	mod32 %r2,0x29a
+ 108:	94 03 00 00 66 fd ff ff 	mod32 %r3,0xfffffd66
+ 110:	94 04 00 00 ef be ad 7e 	mod32 %r4,0x7eadbeef
+ 118:	9c 65 00 00 00 00 00 00 	mod32 %r5,%r6
+ 120:	a4 02 00 00 9a 02 00 00 	xor32 %r2,0x29a
+ 128:	a4 03 00 00 66 fd ff ff 	xor32 %r3,0xfffffd66
+ 130:	a4 04 00 00 ef be ad 7e 	xor32 %r4,0x7eadbeef
+ 138:	ac 65 00 00 00 00 00 00 	xor32 %r5,%r6
+ 140:	b4 02 00 00 9a 02 00 00 	mov32 %r2,0x29a
+ 148:	b4 03 00 00 66 fd ff ff 	mov32 %r3,0xfffffd66
+ 150:	b4 04 00 00 ef be ad 7e 	mov32 %r4,0x7eadbeef
+ 158:	bc 65 00 00 00 00 00 00 	mov32 %r5,%r6
+ 160:	c4 02 00 00 9a 02 00 00 	arsh32 %r2,0x29a
+ 168:	c4 03 00 00 66 fd ff ff 	arsh32 %r3,0xfffffd66
+ 170:	c4 04 00 00 ef be ad 7e 	arsh32 %r4,0x7eadbeef
+ 178:	cc 65 00 00 00 00 00 00 	arsh32 %r5,%r6
+ 180:	8c 32 00 00 00 00 00 00 	neg32 %r2,%r3
diff --git a/gas/testsuite/gas/bpf/alu32.s b/gas/testsuite/gas/bpf/alu32.s
index 7b6f014e8be..f43ea4a4d23 100644
--- a/gas/testsuite/gas/bpf/alu32.s
+++ b/gas/testsuite/gas/bpf/alu32.s
@@ -48,10 +48,4 @@
         arsh32	%r3, -666
         arsh32	%r4, 0x7eadbeef
         arsh32	%r5, %r6
-        neg32	%r2
-	endle	%r9,16
-        endle	%r8,32
-        endle	%r7,64
-        endbe	%r6,16
-        endbe	%r5,32
-        endbe	%r4,64
+        neg32	%r2, %r3
diff --git a/gas/testsuite/gas/bpf/atomic-be-pseudoc.d b/gas/testsuite/gas/bpf/atomic-be-pseudoc.d
new file mode 100644
index 00000000000..a57322e49d9
--- /dev/null
+++ b/gas/testsuite/gas/bpf/atomic-be-pseudoc.d
@@ -0,0 +1,12 @@
+#as: -EB -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
+#source: atomic-pseudoc.s
+#name: eBPF atomic instructions, pseudoc syntax, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	db 12 1e ef 00 00 00 00 	\*\(u64\*\)\(r1\+0x1eef\)\+=r2
+   8:	c3 12 1e ef 00 00 00 00 	\*\(u32\*\)\(r1\+0x1eef\)\+=r2
diff --git a/gas/testsuite/gas/bpf/atomic-be.d b/gas/testsuite/gas/bpf/atomic-be.d
index b252571e5fd..fa81d8f6ffb 100644
--- a/gas/testsuite/gas/bpf/atomic-be.d
+++ b/gas/testsuite/gas/bpf/atomic-be.d
@@ -1,7 +1,6 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: atomic.s
-#source: atomic-pseudoc.s
-#objdump: -dr
+#objdump: -dr -M hex,v1
 #name: eBPF atomic instructions, big endian
 
 .*: +file format .*bpf.*
diff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.d b/gas/testsuite/gas/bpf/atomic-pseudoc.d
index 3b0e5c567be..3aafd47e0d8 100644
--- a/gas/testsuite/gas/bpf/atomic-pseudoc.d
+++ b/gas/testsuite/gas/bpf/atomic-pseudoc.d
@@ -1,5 +1,12 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
 #source: atomic-pseudoc.s
-#dump: atomic.dump
-#name: eBPF atomic instructions, normal syntax
+#name: eBPF atomic instructions, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	db 21 ef 1e 00 00 00 00 	\*\(u64\*\)\(r1\+0x1eef\)\+=r2
+   8:	c3 21 ef 1e 00 00 00 00 	\*\(u32\*\)\(r1\+0x1eef\)\+=r2
diff --git a/gas/testsuite/gas/bpf/atomic-pseudoc.s b/gas/testsuite/gas/bpf/atomic-pseudoc.s
index 1a4f218ccb7..ac73cadf999 100644
--- a/gas/testsuite/gas/bpf/atomic-pseudoc.s
+++ b/gas/testsuite/gas/bpf/atomic-pseudoc.s
@@ -1,4 +1,4 @@
         # Test for eBPF ADDW and ADDDW pseudo-C instructions
         .text
-	lock *(u64 *)(r1 + 7919) += r2
-	lock *(u32 *)(r1 + 7919) += r2
+	*(u64 *)(r1 + 7919) += r2
+	*(u32 *)(r1 + 7919) += r2
diff --git a/gas/testsuite/gas/bpf/atomic.d b/gas/testsuite/gas/bpf/atomic.d
index c48ba9aabda..0a27cae0019 100644
--- a/gas/testsuite/gas/bpf/atomic.d
+++ b/gas/testsuite/gas/bpf/atomic.d
@@ -1,5 +1,12 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
 #source: atomic.s
-#dump: atomic.dump
 #name: eBPF atomic instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	db 21 ef 1e 00 00 00 00 	aadd \[%r1\+0x1eef\],%r2
+   8:	c3 21 ef 1e 00 00 00 00 	aadd32 \[%r1\+0x1eef\],%r2
diff --git a/gas/testsuite/gas/bpf/atomic.s b/gas/testsuite/gas/bpf/atomic.s
index 0119b24c8bb..4669f4adf04 100644
--- a/gas/testsuite/gas/bpf/atomic.s
+++ b/gas/testsuite/gas/bpf/atomic.s
@@ -1,5 +1,5 @@
         # Test for eBPF ADDW and ADDDW instructions
         .text
-        xadddw	[%r1+0x1eef], %r2
-        xaddw	[%r1+0x1eef], %r2
+        aadd	[%r1+0x1eef], %r2
+        aadd32	[%r1+0x1eef], %r2
         
diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp
index 5d91805f478..adf413f834c 100644
--- a/gas/testsuite/gas/bpf/bpf.exp
+++ b/gas/testsuite/gas/bpf/bpf.exp
@@ -18,6 +18,10 @@
 # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  
 
 if {[istarget bpf*-*-*]} {
+    # Little-endian BPF tests
+    run_dump_test call
+    run_dump_test exit
+    run_dump_test data
     run_dump_test lddw
     run_dump_test lddw-pseudoc
     run_dump_test alu
@@ -30,13 +34,15 @@ if {[istarget bpf*-*-*]} {
     run_dump_test jump-pseudoc
     run_dump_test jump32
     run_dump_test jump32-pseudoc
-    run_dump_test call
-    run_dump_test exit
     run_dump_test atomic
     run_dump_test atomic-pseudoc
-    run_dump_test data
-    run_dump_test pseudoc-normal
+    run_dump_test indcall-1
+    run_dump_test indcall-1-pseudoc
 
+    # Big-endian BPF tests
+    run_dump_test call-be
+    run_dump_test exit-be
+    run_dump_test data-be
     run_dump_test lddw-be
     run_dump_test lddw-be-pseudoc
     run_dump_test alu-be
@@ -44,17 +50,11 @@ if {[istarget bpf*-*-*]} {
     run_dump_test alu32-be
     run_dump_test alu32-be-pseudoc
     run_dump_test mem-be
+    run_dump_test mem-be-pseudoc
     run_dump_test jump-be
-    run_dump_test call-be
-    run_dump_test exit-be
+    run_dump_test jump-be-pseudoc
+    run_dump_test jump32-be
+    run_dump_test jump32-be-pseudoc
     run_dump_test atomic-be
-    run_dump_test data-be
-    run_dump_test pseudoc-normal-be
-
-    run_dump_test indcall-1
-    run_dump_test indcall-1-pseudoc
-    run_list_test indcall-bad-1
-
-    run_dump_test alu-xbpf
-    run_dump_test alu32-xbpf
+    run_dump_test atomic-be-pseudoc
 }
diff --git a/gas/testsuite/gas/bpf/call-be.d b/gas/testsuite/gas/bpf/call-be.d
index bd3b50f36b2..55e4e700ab4 100644
--- a/gas/testsuite/gas/bpf/call-be.d
+++ b/gas/testsuite/gas/bpf/call-be.d
@@ -1,6 +1,6 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: call.s
-#objdump: -dr
+#objdump: -dr -M dec
 #name: eBPF CALL instruction, big endian
 
 .*: +file format .*bpf.*
diff --git a/gas/testsuite/gas/bpf/call.d b/gas/testsuite/gas/bpf/call.d
index daefbd08022..a85cb7f58ab 100644
--- a/gas/testsuite/gas/bpf/call.d
+++ b/gas/testsuite/gas/bpf/call.d
@@ -1,5 +1,5 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M dec
 #name: eBPF CALL instruction
 
 .*: +file format .*bpf.*
diff --git a/gas/testsuite/gas/bpf/data-be.d b/gas/testsuite/gas/bpf/data-be.d
index 010f08f2508..3a8b68bd1d2 100644
--- a/gas/testsuite/gas/bpf/data-be.d
+++ b/gas/testsuite/gas/bpf/data-be.d
@@ -1,4 +1,4 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: data.s
 #objdump: -s -j .data
 #name: eBPF data directives, big endian
diff --git a/gas/testsuite/gas/bpf/data.d b/gas/testsuite/gas/bpf/data.d
index 6824e8b8b5a..9fa108b6542 100644
--- a/gas/testsuite/gas/bpf/data.d
+++ b/gas/testsuite/gas/bpf/data.d
@@ -1,4 +1,4 @@
-#as: --EL
+#as: -EL -mdialect=normal
 #objdump: -s -j .data
 #name: eBPF data directives
 
diff --git a/gas/testsuite/gas/bpf/exit-be.d b/gas/testsuite/gas/bpf/exit-be.d
index d3b88c7373a..b83af3eacab 100644
--- a/gas/testsuite/gas/bpf/exit-be.d
+++ b/gas/testsuite/gas/bpf/exit-be.d
@@ -1,6 +1,6 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: exit.s
-#objdump: -dr
+#objdump: -dr -M hex
 #name: eBPF EXIT instruction, big endian
 
 .*: +file format .*bpf.*
diff --git a/gas/testsuite/gas/bpf/exit.d b/gas/testsuite/gas/bpf/exit.d
index 87bc91b2d2e..68ef9020185 100644
--- a/gas/testsuite/gas/bpf/exit.d
+++ b/gas/testsuite/gas/bpf/exit.d
@@ -1,5 +1,5 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
 #name: eBPF EXIT instruction
 
 .*: +file format .*bpf.*
diff --git a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d
index b04e656bd82..7a95bad8e65 100644
--- a/gas/testsuite/gas/bpf/indcall-1-pseudoc.d
+++ b/gas/testsuite/gas/bpf/indcall-1-pseudoc.d
@@ -1,5 +1,23 @@
-#as: -mxbpf --EL
-#objdump: -mxbpf -dr
+#as: -EL -mdialect=pseudoc -misa-spec=xbpf
+#objdump: -M xbpf,pseudoc,dec -dr
 #source: indcall-1-pseudoc.s
-#dump: indcall-1.dump
 #name: BPF indirect call 1, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section \.text:
+
+0000000000000000 <main>:
+   0:	b7 00 00 00 01 00 00 00 	r0=1
+   8:	b7 01 00 00 01 00 00 00 	r1=1
+  10:	b7 02 00 00 02 00 00 00 	r2=2
+  18:	18 06 00 00 38 00 00 00 	r6=56 ll
+  20:	00 00 00 00 00 00 00 00[    ]*
+			18: R_BPF_64_64	.text
+  28:	8d 06 00 00 00 00 00 00 	callx r6
+  30:	95 00 00 00 00 00 00 00 	exit
+
+0000000000000038 <bar>:
+  38:	b7 00 00 00 00 00 00 00 	r0=0
+  40:	95 00 00 00 00 00 00 00 	exit
+#pass
diff --git a/gas/testsuite/gas/bpf/indcall-1.d b/gas/testsuite/gas/bpf/indcall-1.d
index e04b98b175b..51103bba2a1 100644
--- a/gas/testsuite/gas/bpf/indcall-1.d
+++ b/gas/testsuite/gas/bpf/indcall-1.d
@@ -1,5 +1,23 @@
-#as: -mxbpf --EL
-#objdump: -mxbpf -dr
+#as: -EL -misa-spec=xbpf
+#objdump: -dr -M xbpf,dec
 #source: indcall-1.s
-#dump: indcall-1.dump
 #name: BPF indirect call 1, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section \.text:
+
+0000000000000000 <main>:
+   0:	b7 00 00 00 01 00 00 00 	mov %r0,1
+   8:	b7 01 00 00 01 00 00 00 	mov %r1,1
+  10:	b7 02 00 00 02 00 00 00 	mov %r2,2
+  18:	18 06 00 00 38 00 00 00 	lddw %r6,56
+  20:	00 00 00 00 00 00 00 00[    ]*
+			18: R_BPF_64_64	.text
+  28:	8d 06 00 00 00 00 00 00 	call %r6
+  30:	95 00 00 00 00 00 00 00 	exit
+
+0000000000000038 <bar>:
+  38:	b7 00 00 00 00 00 00 00 	mov %r0,0
+  40:	95 00 00 00 00 00 00 00 	exit
+#pass
diff --git a/gas/testsuite/gas/bpf/jump-be-pseudoc.d b/gas/testsuite/gas/bpf/jump-be-pseudoc.d
new file mode 100644
index 00000000000..3874d58f73a
--- /dev/null
+++ b/gas/testsuite/gas/bpf/jump-be-pseudoc.d
@@ -0,0 +1,32 @@
+#as: -EB -mdialect=pseudoc
+#source: jump-pseudoc.s
+#objdump: -dr -M dec,pseudoc
+#name: eBPF JUMP instructions, big endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	05 00 00 03 00 00 00 00 	goto 3
+   8:	0f 11 00 00 00 00 00 00 	r1\+=r1
+  10:	15 30 00 01 00 00 00 03 	if r3==3 goto 1
+  18:	1d 34 00 00 00 00 00 00 	if r3==r4 goto 0
+  20:	35 30 ff fd 00 00 00 03 	if r3>=3 goto -3
+  28:	3d 34 ff fc 00 00 00 00 	if r3>=r4 goto -4
+  30:	a5 30 00 01 00 00 00 03 	if r3<3 goto 1
+  38:	ad 34 00 00 00 00 00 00 	if r3<r4 goto 0
+  40:	b5 30 00 01 00 00 00 03 	if r3<=3 goto 1
+  48:	bd 34 00 00 00 00 00 00 	if r3<=r4 goto 0
+  50:	45 30 00 01 00 00 00 03 	if r3&3 goto 1
+  58:	4d 34 00 00 00 00 00 00 	if r3&r4 goto 0
+  60:	55 30 00 01 00 00 00 03 	if r3!=3 goto 1
+  68:	5d 34 00 00 00 00 00 00 	if r3!=r4 goto 0
+  70:	65 30 00 01 00 00 00 03 	if r3s>3 goto 1
+  78:	6d 34 00 00 00 00 00 00 	if r3s>r4 goto 0
+  80:	75 30 00 01 00 00 00 03 	if r3s>=3 goto 1
+  88:	7d 34 00 00 00 00 00 00 	if r3s>=r4 goto 0
+  90:	c5 30 00 01 00 00 00 03 	if r3s<3 goto 1
+  98:	cd 34 00 00 00 00 00 00 	if r3s<r4 goto 0
+  a0:	d5 30 00 01 00 00 00 03 	if r3s<=3 goto 1
+  a8:	dd 34 00 00 00 00 00 00 	if r3s<=r4 goto 0
diff --git a/gas/testsuite/gas/bpf/jump-be.d b/gas/testsuite/gas/bpf/jump-be.d
index 7e235e69551..7c8a765ddcf 100644
--- a/gas/testsuite/gas/bpf/jump-be.d
+++ b/gas/testsuite/gas/bpf/jump-be.d
@@ -1,7 +1,6 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: jump.s
-#source: jump-pseudoc.s
-#objdump: -dr
+#objdump: -dr -M dec
 #name: eBPF JUMP instructions, big endian
 
 .*: +file format .*bpf.*
diff --git a/gas/testsuite/gas/bpf/jump-pseudoc.d b/gas/testsuite/gas/bpf/jump-pseudoc.d
index bc172665af8..644d2be30b7 100644
--- a/gas/testsuite/gas/bpf/jump-pseudoc.d
+++ b/gas/testsuite/gas/bpf/jump-pseudoc.d
@@ -1,5 +1,32 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M dec,pseudoc
 #source: jump-pseudoc.s
-#dump: jump.dump
 #name: eBPF JUMP instructions, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	05 00 03 00 00 00 00 00 	goto 3
+   8:	0f 11 00 00 00 00 00 00 	r1\+=r1
+  10:	15 03 01 00 03 00 00 00 	if r3==3 goto 1
+  18:	1d 43 00 00 00 00 00 00 	if r3==r4 goto 0
+  20:	35 03 fd ff 03 00 00 00 	if r3>=3 goto -3
+  28:	3d 43 fc ff 00 00 00 00 	if r3>=r4 goto -4
+  30:	a5 03 01 00 03 00 00 00 	if r3<3 goto 1
+  38:	ad 43 00 00 00 00 00 00 	if r3<r4 goto 0
+  40:	b5 03 01 00 03 00 00 00 	if r3<=3 goto 1
+  48:	bd 43 00 00 00 00 00 00 	if r3<=r4 goto 0
+  50:	45 03 01 00 03 00 00 00 	if r3&3 goto 1
+  58:	4d 43 00 00 00 00 00 00 	if r3&r4 goto 0
+  60:	55 03 01 00 03 00 00 00 	if r3!=3 goto 1
+  68:	5d 43 00 00 00 00 00 00 	if r3!=r4 goto 0
+  70:	65 03 01 00 03 00 00 00 	if r3s>3 goto 1
+  78:	6d 43 00 00 00 00 00 00 	if r3s>r4 goto 0
+  80:	75 03 01 00 03 00 00 00 	if r3s>=3 goto 1
+  88:	7d 43 00 00 00 00 00 00 	if r3s>=r4 goto 0
+  90:	c5 03 01 00 03 00 00 00 	if r3s<3 goto 1
+  98:	cd 43 00 00 00 00 00 00 	if r3s<r4 goto 0
+  a0:	d5 03 01 00 03 00 00 00 	if r3s<=3 goto 1
+  a8:	dd 43 00 00 00 00 00 00 	if r3s<=r4 goto 0
diff --git a/gas/testsuite/gas/bpf/jump.d b/gas/testsuite/gas/bpf/jump.d
index 082b3c3018e..742610a8ab2 100644
--- a/gas/testsuite/gas/bpf/jump.d
+++ b/gas/testsuite/gas/bpf/jump.d
@@ -1,5 +1,32 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M dec
 #source: jump.s
-#dump: jump.dump
 #name: eBPF JUMP instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	05 00 03 00 00 00 00 00 	ja 3
+   8:	0f 11 00 00 00 00 00 00 	add %r1,%r1
+  10:	15 03 01 00 03 00 00 00 	jeq %r3,3,1
+  18:	1d 43 00 00 00 00 00 00 	jeq %r3,%r4,0
+  20:	35 03 fd ff 03 00 00 00 	jge %r3,3,-3
+  28:	3d 43 fc ff 00 00 00 00 	jge %r3,%r4,-4
+  30:	a5 03 01 00 03 00 00 00 	jlt %r3,3,1
+  38:	ad 43 00 00 00 00 00 00 	jlt %r3,%r4,0
+  40:	b5 03 01 00 03 00 00 00 	jle %r3,3,1
+  48:	bd 43 00 00 00 00 00 00 	jle %r3,%r4,0
+  50:	45 03 01 00 03 00 00 00 	jset %r3,3,1
+  58:	4d 43 00 00 00 00 00 00 	jset %r3,%r4,0
+  60:	55 03 01 00 03 00 00 00 	jne %r3,3,1
+  68:	5d 43 00 00 00 00 00 00 	jne %r3,%r4,0
+  70:	65 03 01 00 03 00 00 00 	jsgt %r3,3,1
+  78:	6d 43 00 00 00 00 00 00 	jsgt %r3,%r4,0
+  80:	75 03 01 00 03 00 00 00 	jsge %r3,3,1
+  88:	7d 43 00 00 00 00 00 00 	jsge %r3,%r4,0
+  90:	c5 03 01 00 03 00 00 00 	jslt %r3,3,1
+  98:	cd 43 00 00 00 00 00 00 	jslt %r3,%r4,0
+  a0:	d5 03 01 00 03 00 00 00 	jsle %r3,3,1
+  a8:	dd 43 00 00 00 00 00 00 	jsle %r3,%r4,0
diff --git a/gas/testsuite/gas/bpf/jump32-be-pseudoc.d b/gas/testsuite/gas/bpf/jump32-be-pseudoc.d
new file mode 100644
index 00000000000..ca20186e59b
--- /dev/null
+++ b/gas/testsuite/gas/bpf/jump32-be-pseudoc.d
@@ -0,0 +1,32 @@
+#as: -EB -mdialect=pseudoc
+#objdump: -dr -M dec,pseudoc
+#source: jump32-pseudoc.s
+#name: eBPF JUMP32 instructions, pseudoc syntax, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	05 00 00 03 00 00 00 00 	goto 3
+   8:	0f 11 00 00 00 00 00 00 	r1\+=r1
+  10:	16 30 00 01 00 00 00 03 	if w3==3 goto 1
+  18:	1e 34 00 00 00 00 00 00 	if w3==w4 goto 0
+  20:	36 30 ff fd 00 00 00 03 	if w3>=3 goto -3
+  28:	3e 34 ff fc 00 00 00 00 	if w3>=w4 goto -4
+  30:	a6 30 00 01 00 00 00 03 	if w3<3 goto 1
+  38:	ae 34 00 00 00 00 00 00 	if w3<w4 goto 0
+  40:	b6 30 00 01 00 00 00 03 	if w3<=3 goto 1
+  48:	be 34 00 00 00 00 00 00 	if w3<=w4 goto 0
+  50:	46 30 00 01 00 00 00 03 	if w3&3 goto 1
+  58:	4e 34 00 00 00 00 00 00 	if w3&w4 goto 0
+  60:	56 30 00 01 00 00 00 03 	if w3!=3 goto 1
+  68:	5e 34 00 00 00 00 00 00 	if w3!=w4 goto 0
+  70:	66 30 00 01 00 00 00 03 	if w3s>3 goto 1
+  78:	6e 34 00 00 00 00 00 00 	if w3s>w4 goto 0
+  80:	76 30 00 01 00 00 00 03 	if w3s>=3 goto 1
+  88:	7e 34 00 00 00 00 00 00 	if w3s>=w4 goto 0
+  90:	c6 30 00 01 00 00 00 03 	if w3s<3 goto 1
+  98:	ce 34 00 00 00 00 00 00 	if w3s<w4 goto 0
+  a0:	d6 30 00 01 00 00 00 03 	if w3s<=3 goto 1
+  a8:	de 34 00 00 00 00 00 00 	if w3s<=w4 goto 0
diff --git a/gas/testsuite/gas/bpf/jump32-be.d b/gas/testsuite/gas/bpf/jump32-be.d
new file mode 100644
index 00000000000..446d33889d8
--- /dev/null
+++ b/gas/testsuite/gas/bpf/jump32-be.d
@@ -0,0 +1,32 @@
+#as: -EB -mdialect=normal
+#objdump: -dr -M dec
+#source: jump32.s
+#name: eBPF JUMP32 instructions, normal syntax, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	05 00 00 03 00 00 00 00 	ja 3
+   8:	0f 11 00 00 00 00 00 00 	add %r1,%r1
+  10:	16 30 00 01 00 00 00 03 	jeq32 %r3,3,1
+  18:	1e 34 00 00 00 00 00 00 	jeq32 %r3,%r4,0
+  20:	36 30 ff fd 00 00 00 03 	jge32 %r3,3,-3
+  28:	3e 34 ff fc 00 00 00 00 	jge32 %r3,%r4,-4
+  30:	a6 30 00 01 00 00 00 03 	jlt32 %r3,3,1
+  38:	ae 34 00 00 00 00 00 00 	jlt32 %r3,%r4,0
+  40:	b6 30 00 01 00 00 00 03 	jle32 %r3,3,1
+  48:	be 34 00 00 00 00 00 00 	jle32 %r3,%r4,0
+  50:	46 30 00 01 00 00 00 03 	jset32 %r3,3,1
+  58:	4e 34 00 00 00 00 00 00 	jset32 %r3,%r4,0
+  60:	56 30 00 01 00 00 00 03 	jne32 %r3,3,1
+  68:	5e 34 00 00 00 00 00 00 	jne32 %r3,%r4,0
+  70:	66 30 00 01 00 00 00 03 	jsgt32 %r3,3,1
+  78:	6e 34 00 00 00 00 00 00 	jsgt32 %r3,%r4,0
+  80:	76 30 00 01 00 00 00 03 	jsge32 %r3,3,1
+  88:	7e 34 00 00 00 00 00 00 	jsge32 %r3,%r4,0
+  90:	c6 30 00 01 00 00 00 03 	jslt32 %r3,3,1
+  98:	ce 34 00 00 00 00 00 00 	jslt32 %r3,%r4,0
+  a0:	d6 30 00 01 00 00 00 03 	jsle32 %r3,3,1
+  a8:	de 34 00 00 00 00 00 00 	jsle32 %r3,%r4,0
diff --git a/gas/testsuite/gas/bpf/jump32-pseudoc.d b/gas/testsuite/gas/bpf/jump32-pseudoc.d
index 55fb97b82db..27367d36594 100644
--- a/gas/testsuite/gas/bpf/jump32-pseudoc.d
+++ b/gas/testsuite/gas/bpf/jump32-pseudoc.d
@@ -1,5 +1,32 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M dec,pseudoc
 #source: jump32-pseudoc.s
-#dump: jump32.dump
 #name: eBPF JUMP32 instructions, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	05 00 03 00 00 00 00 00 	goto 3
+   8:	0f 11 00 00 00 00 00 00 	r1\+=r1
+  10:	16 03 01 00 03 00 00 00 	if w3==3 goto 1
+  18:	1e 43 00 00 00 00 00 00 	if w3==w4 goto 0
+  20:	36 03 fd ff 03 00 00 00 	if w3>=3 goto -3
+  28:	3e 43 fc ff 00 00 00 00 	if w3>=w4 goto -4
+  30:	a6 03 01 00 03 00 00 00 	if w3<3 goto 1
+  38:	ae 43 00 00 00 00 00 00 	if w3<w4 goto 0
+  40:	b6 03 01 00 03 00 00 00 	if w3<=3 goto 1
+  48:	be 43 00 00 00 00 00 00 	if w3<=w4 goto 0
+  50:	46 03 01 00 03 00 00 00 	if w3&3 goto 1
+  58:	4e 43 00 00 00 00 00 00 	if w3&w4 goto 0
+  60:	56 03 01 00 03 00 00 00 	if w3!=3 goto 1
+  68:	5e 43 00 00 00 00 00 00 	if w3!=w4 goto 0
+  70:	66 03 01 00 03 00 00 00 	if w3s>3 goto 1
+  78:	6e 43 00 00 00 00 00 00 	if w3s>w4 goto 0
+  80:	76 03 01 00 03 00 00 00 	if w3s>=3 goto 1
+  88:	7e 43 00 00 00 00 00 00 	if w3s>=w4 goto 0
+  90:	c6 03 01 00 03 00 00 00 	if w3s<3 goto 1
+  98:	ce 43 00 00 00 00 00 00 	if w3s<w4 goto 0
+  a0:	d6 03 01 00 03 00 00 00 	if w3s<=3 goto 1
+  a8:	de 43 00 00 00 00 00 00 	if w3s<=w4 goto 0
diff --git a/gas/testsuite/gas/bpf/jump32.d b/gas/testsuite/gas/bpf/jump32.d
index c5efb41cc08..e39dc381384 100644
--- a/gas/testsuite/gas/bpf/jump32.d
+++ b/gas/testsuite/gas/bpf/jump32.d
@@ -1,5 +1,32 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M dec
 #source: jump32.s
-#dump: jump32.dump
 #name: eBPF JUMP32 instructions, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	05 00 03 00 00 00 00 00 	ja 3
+   8:	0f 11 00 00 00 00 00 00 	add %r1,%r1
+  10:	16 03 01 00 03 00 00 00 	jeq32 %r3,3,1
+  18:	1e 43 00 00 00 00 00 00 	jeq32 %r3,%r4,0
+  20:	36 03 fd ff 03 00 00 00 	jge32 %r3,3,-3
+  28:	3e 43 fc ff 00 00 00 00 	jge32 %r3,%r4,-4
+  30:	a6 03 01 00 03 00 00 00 	jlt32 %r3,3,1
+  38:	ae 43 00 00 00 00 00 00 	jlt32 %r3,%r4,0
+  40:	b6 03 01 00 03 00 00 00 	jle32 %r3,3,1
+  48:	be 43 00 00 00 00 00 00 	jle32 %r3,%r4,0
+  50:	46 03 01 00 03 00 00 00 	jset32 %r3,3,1
+  58:	4e 43 00 00 00 00 00 00 	jset32 %r3,%r4,0
+  60:	56 03 01 00 03 00 00 00 	jne32 %r3,3,1
+  68:	5e 43 00 00 00 00 00 00 	jne32 %r3,%r4,0
+  70:	66 03 01 00 03 00 00 00 	jsgt32 %r3,3,1
+  78:	6e 43 00 00 00 00 00 00 	jsgt32 %r3,%r4,0
+  80:	76 03 01 00 03 00 00 00 	jsge32 %r3,3,1
+  88:	7e 43 00 00 00 00 00 00 	jsge32 %r3,%r4,0
+  90:	c6 03 01 00 03 00 00 00 	jslt32 %r3,3,1
+  98:	ce 43 00 00 00 00 00 00 	jslt32 %r3,%r4,0
+  a0:	d6 03 01 00 03 00 00 00 	jsle32 %r3,3,1
+  a8:	de 43 00 00 00 00 00 00 	jsle32 %r3,%r4,0
diff --git a/gas/testsuite/gas/bpf/lddw-be-pseudoc.d b/gas/testsuite/gas/bpf/lddw-be-pseudoc.d
index e7b477ac4ca..940780b81a2 100644
--- a/gas/testsuite/gas/bpf/lddw-be-pseudoc.d
+++ b/gas/testsuite/gas/bpf/lddw-be-pseudoc.d
@@ -1,5 +1,18 @@
-#as: --EB
+#as: -EB -mdialect=pseudoc
 #source: lddw-pseudoc.s
-#objdump: -dr
-#dump: lddw-be.dump
+#objdump: -dr -M hex,pseudoc
 #name: eBPF LDDW, big-endian, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	18 30 00 00 00 00 00 01 	r3=0x1 ll
+   8:	00 00 00 00 00 00 00 00 
+  10:	18 40 00 00 de ad be ef 	r4=0xdeadbeef ll
+  18:	00 00 00 00 00 00 00 00 
+  20:	18 50 00 00 55 66 77 88 	r5=0x1122334455667788 ll
+  28:	00 00 00 00 11 22 33 44 
+  30:	18 60 00 00 ff ff ff fe 	r6=0xfffffffffffffffe ll
+  38:	00 00 00 00 ff ff ff ff 
diff --git a/gas/testsuite/gas/bpf/lddw-be.d b/gas/testsuite/gas/bpf/lddw-be.d
index cf1bfba9b3d..c1043787dcd 100644
--- a/gas/testsuite/gas/bpf/lddw-be.d
+++ b/gas/testsuite/gas/bpf/lddw-be.d
@@ -1,5 +1,18 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: lddw.s
-#objdump: -dr
-#dump: lddw-be.dump
+#objdump: -dr -M hex
 #name: eBPF LDDW, big-endian, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	18 30 00 00 00 00 00 01 	lddw %r3,0x1
+   8:	00 00 00 00 00 00 00 00 
+  10:	18 40 00 00 de ad be ef 	lddw %r4,0xdeadbeef
+  18:	00 00 00 00 00 00 00 00 
+  20:	18 50 00 00 55 66 77 88 	lddw %r5,0x1122334455667788
+  28:	00 00 00 00 11 22 33 44 
+  30:	18 60 00 00 ff ff ff fe 	lddw %r6,0xfffffffffffffffe
+  38:	00 00 00 00 ff ff ff ff 
diff --git a/gas/testsuite/gas/bpf/lddw-pseudoc.d b/gas/testsuite/gas/bpf/lddw-pseudoc.d
index 838e012be0b..3a5ce86ff95 100644
--- a/gas/testsuite/gas/bpf/lddw-pseudoc.d
+++ b/gas/testsuite/gas/bpf/lddw-pseudoc.d
@@ -1,5 +1,18 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
 #source: lddw-pseudoc.s
-#dump: lddw.dump
 #name: eBPF LDDW, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	18 03 00 00 01 00 00 00 	r3=0x1 ll
+   8:	00 00 00 00 00 00 00 00 
+  10:	18 04 00 00 ef be ad de 	r4=0xdeadbeef ll
+  18:	00 00 00 00 00 00 00 00 
+  20:	18 05 00 00 88 77 66 55 	r5=0x1122334455667788 ll
+  28:	00 00 00 00 44 33 22 11 
+  30:	18 06 00 00 fe ff ff ff 	r6=0xfffffffffffffffe ll
+  38:	00 00 00 00 ff ff ff ff 
diff --git a/gas/testsuite/gas/bpf/lddw.d b/gas/testsuite/gas/bpf/lddw.d
index 82ff1b47bc4..c7a08098fb8 100644
--- a/gas/testsuite/gas/bpf/lddw.d
+++ b/gas/testsuite/gas/bpf/lddw.d
@@ -1,5 +1,18 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
 #source: lddw.s
-#dump: lddw.dump
 #name: eBPF LDDW, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	18 03 00 00 01 00 00 00 	lddw %r3,0x1
+   8:	00 00 00 00 00 00 00 00 
+  10:	18 04 00 00 ef be ad de 	lddw %r4,0xdeadbeef
+  18:	00 00 00 00 00 00 00 00 
+  20:	18 05 00 00 88 77 66 55 	lddw %r5,0x1122334455667788
+  28:	00 00 00 00 44 33 22 11 
+  30:	18 06 00 00 fe ff ff ff 	lddw %r6,0xfffffffffffffffe
+  38:	00 00 00 00 ff ff ff ff 
diff --git a/gas/testsuite/gas/bpf/mem-be-pseudoc.d b/gas/testsuite/gas/bpf/mem-be-pseudoc.d
new file mode 100644
index 00000000000..ef13fe1f8a4
--- /dev/null
+++ b/gas/testsuite/gas/bpf/mem-be-pseudoc.d
@@ -0,0 +1,30 @@
+#as: -EB -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
+#source: mem-pseudoc.s
+#name: eBPF MEM instructions, modulus lddw, pseudo-c syntax, big-endian
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	20 00 00 00 00 00 be ef 	r0=\*\(u32\*\)skb\[0xbeef\]
+   8:	28 00 00 00 00 00 be ef 	r0=\*\(u16\*\)skb\[0xbeef\]
+  10:	30 00 00 00 00 00 be ef 	r0=\*\(u8\*\)skb\[0xbeef\]
+  18:	38 00 00 00 00 00 be ef 	r0=\*\(u64\*\)skb\[0xbeef\]
+  20:	40 03 00 00 00 00 be ef 	r0=\*\(u32\*\)skb\[r3\+0xbeef\]
+  28:	48 05 00 00 00 00 be ef 	r0=\*\(u16\*\)skb\[r5\+0xbeef\]
+  30:	50 07 00 00 00 00 be ef 	r0=\*\(u8\*\)skb\[r7\+0xbeef\]
+  38:	58 09 00 00 00 00 be ef 	r0=\*\(u64\*\)skb\[r9\+0xbeef\]
+  40:	61 21 7e ef 00 00 00 00 	r2=\*\(u32\*\)\(r1\+0x7eef\)
+  48:	69 21 7e ef 00 00 00 00 	r2=\*\(u16\*\)\(r1\+0x7eef\)
+  50:	71 21 7e ef 00 00 00 00 	r2=\*\(u8\*\)\(r1\+0x7eef\)
+  58:	79 21 ff fe 00 00 00 00 	r2=\*\(u64\*\)\(r1\+0xfffe\)
+  60:	63 12 7e ef 00 00 00 00 	\*\(u32\*\)\(r1\+0x7eef\)=r2
+  68:	6b 12 7e ef 00 00 00 00 	\*\(u16\*\)\(r1\+0x7eef\)=r2
+  70:	73 12 7e ef 00 00 00 00 	\*\(u8\*\)\(r1\+0x7eef\)=r2
+  78:	7b 12 ff fe 00 00 00 00 	\*\(u64\*\)\(r1\+0xfffe\)=r2
+  80:	72 10 7e ef 11 22 33 44 	\*\(u8\*\)\(r1\+0x7eef\)=0x11223344
+  88:	6a 10 7e ef 11 22 33 44 	\*\(u16\*\)\(r1\+0x7eef\)=0x11223344
+  90:	62 10 7e ef 11 22 33 44 	\*\(u32\*\)\(r1\+0x7eef\)=0x11223344
+  98:	7a 10 ff fe 11 22 33 44 	\*\(u64\*\)\(r1\+0xfffe\)=0x11223344
diff --git a/gas/testsuite/gas/bpf/mem-be.d b/gas/testsuite/gas/bpf/mem-be.d
index 148c55a3491..f24efaa4c7b 100644
--- a/gas/testsuite/gas/bpf/mem-be.d
+++ b/gas/testsuite/gas/bpf/mem-be.d
@@ -1,7 +1,6 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: mem.s
-#source: mem-pseudoc.s
-#objdump: -dr
+#objdump: -dr -M hex
 #name: eBPF MEM instructions, modulus lddw, big endian
 
 .*: +file format .*bpf.*
@@ -20,12 +19,12 @@ Disassembly of section .text:
   40:	61 21 7e ef 00 00 00 00 	ldxw %r2,\[%r1\+0x7eef\]
   48:	69 21 7e ef 00 00 00 00 	ldxh %r2,\[%r1\+0x7eef\]
   50:	71 21 7e ef 00 00 00 00 	ldxb %r2,\[%r1\+0x7eef\]
-  58:	79 21 ff fe 00 00 00 00 	ldxdw %r2,\[%r1\+-2\]
+  58:	79 21 ff fe 00 00 00 00 	ldxdw %r2,\[%r1\+0xfffe\]
   60:	63 12 7e ef 00 00 00 00 	stxw \[%r1\+0x7eef\],%r2
   68:	6b 12 7e ef 00 00 00 00 	stxh \[%r1\+0x7eef\],%r2
   70:	73 12 7e ef 00 00 00 00 	stxb \[%r1\+0x7eef\],%r2
-  78:	7b 12 ff fe 00 00 00 00 	stxdw \[%r1\+-2\],%r2
+  78:	7b 12 ff fe 00 00 00 00 	stxdw \[%r1\+0xfffe\],%r2
   80:	72 10 7e ef 11 22 33 44 	stb \[%r1\+0x7eef\],0x11223344
   88:	6a 10 7e ef 11 22 33 44 	sth \[%r1\+0x7eef\],0x11223344
   90:	62 10 7e ef 11 22 33 44 	stw \[%r1\+0x7eef\],0x11223344
-  98:	7a 10 ff fe 11 22 33 44 	stdw \[%r1\+-2\],0x11223344
+  98:	7a 10 ff fe 11 22 33 44 	stdw \[%r1\+0xfffe\],0x11223344
diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.d b/gas/testsuite/gas/bpf/mem-pseudoc.d
index ef5b8957d64..4e8b7d012e3 100644
--- a/gas/testsuite/gas/bpf/mem-pseudoc.d
+++ b/gas/testsuite/gas/bpf/mem-pseudoc.d
@@ -1,5 +1,30 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=pseudoc
+#objdump: -dr -M hex,pseudoc
 #source: mem-pseudoc.s
-#dump: mem.dump
 #name: eBPF MEM instructions, modulus lddw, pseudo-c syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	20 00 00 00 ef be 00 00 	r0=\*\(u32\*\)skb\[0xbeef\]
+   8:	28 00 00 00 ef be 00 00 	r0=\*\(u16\*\)skb\[0xbeef\]
+  10:	30 00 00 00 ef be 00 00 	r0=\*\(u8\*\)skb\[0xbeef\]
+  18:	38 00 00 00 ef be 00 00 	r0=\*\(u64\*\)skb\[0xbeef\]
+  20:	40 30 00 00 ef be 00 00 	r0=\*\(u32\*\)skb\[r3\+0xbeef\]
+  28:	48 50 00 00 ef be 00 00 	r0=\*\(u16\*\)skb\[r5\+0xbeef\]
+  30:	50 70 00 00 ef be 00 00 	r0=\*\(u8\*\)skb\[r7\+0xbeef\]
+  38:	58 90 00 00 ef be 00 00 	r0=\*\(u64\*\)skb\[r9\+0xbeef\]
+  40:	61 12 ef 7e 00 00 00 00 	r2=\*\(u32\*\)\(r1\+0x7eef\)
+  48:	69 12 ef 7e 00 00 00 00 	r2=\*\(u16\*\)\(r1\+0x7eef\)
+  50:	71 12 ef 7e 00 00 00 00 	r2=\*\(u8\*\)\(r1\+0x7eef\)
+  58:	79 12 fe ff 00 00 00 00 	r2=\*\(u64\*\)\(r1\+0xfffe\)
+  60:	63 21 ef 7e 00 00 00 00 	\*\(u32\*\)\(r1\+0x7eef\)=r2
+  68:	6b 21 ef 7e 00 00 00 00 	\*\(u16\*\)\(r1\+0x7eef\)=r2
+  70:	73 21 ef 7e 00 00 00 00 	\*\(u8\*\)\(r1\+0x7eef\)=r2
+  78:	7b 21 fe ff 00 00 00 00 	\*\(u64\*\)\(r1\+0xfffe\)=r2
+  80:	72 01 ef 7e 44 33 22 11 	\*\(u8\*\)\(r1\+0x7eef\)=0x11223344
+  88:	6a 01 ef 7e 44 33 22 11 	\*\(u16\*\)\(r1\+0x7eef\)=0x11223344
+  90:	62 01 ef 7e 44 33 22 11 	\*\(u32\*\)\(r1\+0x7eef\)=0x11223344
+  98:	7a 01 fe ff 44 33 22 11 	\*\(u64\*\)\(r1\+0xfffe\)=0x11223344
diff --git a/gas/testsuite/gas/bpf/mem-pseudoc.s b/gas/testsuite/gas/bpf/mem-pseudoc.s
index 06c2cfcdde9..7b8c832eb40 100644
--- a/gas/testsuite/gas/bpf/mem-pseudoc.s
+++ b/gas/testsuite/gas/bpf/mem-pseudoc.s
@@ -17,7 +17,7 @@
 	*(u16 *)(r1 + 32495) = r2
 	*(u8 *)(r1 + 32495) = r2
 	*(u64 *)(r1 - 2) = r2
-	stb [%r1+0x7eef], 0x11223344
-	sth [%r1+0x7eef], 0x11223344
-	stw [%r1+0x7eef], 0x11223344
-	stdw [%r1+-2], 0x11223344
+        *(u8 *)(r1 + 0x7eef) = 0x11223344
+	*(u16 *)(r1 + 0x7eef) = 0x11223344
+	*(u32 *)(r1 + 0x7eef) = 0x11223344
+	*(u64 *)(r1 + -2) = 0x11223344
diff --git a/gas/testsuite/gas/bpf/mem.d b/gas/testsuite/gas/bpf/mem.d
index b01bdaaf241..669aae36ce7 100644
--- a/gas/testsuite/gas/bpf/mem.d
+++ b/gas/testsuite/gas/bpf/mem.d
@@ -1,5 +1,30 @@
-#as: --EL
-#objdump: -dr
+#as: -EL -mdialect=normal
+#objdump: -dr -M hex
 #source: mem.s
-#dump: mem.dump
 #name: eBPF MEM instructions, modulus lddw, normal syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	20 00 00 00 ef be 00 00 	ldabsw 0xbeef
+   8:	28 00 00 00 ef be 00 00 	ldabsh 0xbeef
+  10:	30 00 00 00 ef be 00 00 	ldabsb 0xbeef
+  18:	38 00 00 00 ef be 00 00 	ldabsdw 0xbeef
+  20:	40 30 00 00 ef be 00 00 	ldindw %r3,0xbeef
+  28:	48 50 00 00 ef be 00 00 	ldindh %r5,0xbeef
+  30:	50 70 00 00 ef be 00 00 	ldindb %r7,0xbeef
+  38:	58 90 00 00 ef be 00 00 	ldinddw %r9,0xbeef
+  40:	61 12 ef 7e 00 00 00 00 	ldxw %r2,\[%r1\+0x7eef\]
+  48:	69 12 ef 7e 00 00 00 00 	ldxh %r2,\[%r1\+0x7eef\]
+  50:	71 12 ef 7e 00 00 00 00 	ldxb %r2,\[%r1\+0x7eef\]
+  58:	79 12 fe ff 00 00 00 00 	ldxdw %r2,\[%r1\+0xfffe\]
+  60:	63 21 ef 7e 00 00 00 00 	stxw \[%r1\+0x7eef\],%r2
+  68:	6b 21 ef 7e 00 00 00 00 	stxh \[%r1\+0x7eef\],%r2
+  70:	73 21 ef 7e 00 00 00 00 	stxb \[%r1\+0x7eef\],%r2
+  78:	7b 21 fe ff 00 00 00 00 	stxdw \[%r1\+0xfffe\],%r2
+  80:	72 01 ef 7e 44 33 22 11 	stb \[%r1\+0x7eef\],0x11223344
+  88:	6a 01 ef 7e 44 33 22 11 	sth \[%r1\+0x7eef\],0x11223344
+  90:	62 01 ef 7e 44 33 22 11 	stw \[%r1\+0x7eef\],0x11223344
+  98:	7a 01 fe ff 44 33 22 11 	stdw \[%r1\+0xfffe\],0x11223344
diff --git a/gas/testsuite/gas/bpf/mem.s b/gas/testsuite/gas/bpf/mem.s
index af6f41b0db0..798a18e2436 100644
--- a/gas/testsuite/gas/bpf/mem.s
+++ b/gas/testsuite/gas/bpf/mem.s
@@ -21,4 +21,4 @@
  	stb [%r1+0x7eef], 0x11223344
  	sth [%r1+0x7eef], 0x11223344
  	stw [%r1+0x7eef], 0x11223344
- 	stdw [%r1+-2], 0x11223344
+ 	stdw [%r1-2], 0x11223344
diff --git a/gas/testsuite/gas/bpf/spacing-pseudoc.d b/gas/testsuite/gas/bpf/spacing-pseudoc.d
new file mode 100644
index 00000000000..16f5763aeb0
--- /dev/null
+++ b/gas/testsuite/gas/bpf/spacing-pseudoc.d
@@ -0,0 +1,18 @@
+#as: -EB -mdialect=pseudoc
+#source: spacing-pseudoc.s
+#objdump: -dr -M hex,pseudoc
+#name: spacing, pseudoc syntax
+
+.*: +file format .*bpf.*
+
+Disassembly of section .text:
+
+0+ <.text>:
+   0:	b7 04 00 00 ef be ad de 	r4=0xdeadbeef
+   8:	18 04 00 00 ef be ad de 	r4=0xdeadbeef ll
+  10:	00 00 00 00 00 00 00 00 
+  18:	05 00 01 00 00 00 00 00 	goto 0x1
+  20:	05 00 01 00 00 00 00 00 	goto 0x1
+  28:	05 00 01 00 00 00 00 00 	goto 0x1
+  30:	16 03 01 00 03 00 00 00 	if w3==0x3 goto 0x1
+  38:	16 03 01 00 03 00 00 00 	if w3==0x3 goto 0x1
diff --git a/gas/testsuite/gas/bpf/spacing-pseudoc.s b/gas/testsuite/gas/bpf/spacing-pseudoc.s
new file mode 100644
index 00000000000..3c19d9a5073
--- /dev/null
+++ b/gas/testsuite/gas/bpf/spacing-pseudoc.s
@@ -0,0 +1,9 @@
+        ;; This test checks that flexible spacing is supported in the
+        ;; pseudoc syntax.
+        r4 = 0xdeadbeefll
+        r4 = 0xdeadbeef ll
+        goto +1
+        goto+1
+        goto1
+        if w3==3 goto+1
+        if w3==3 goto1
diff --git a/include/dis-asm.h b/include/dis-asm.h
index d356429f3c5..c76185f5b3c 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -388,6 +388,7 @@ extern void print_arc_disassembler_options (FILE *);
 extern void print_s390_disassembler_options (FILE *);
 extern void print_wasm32_disassembler_options (FILE *);
 extern void print_loongarch_disassembler_options (FILE *);
+extern void print_bpf_disassembler_options (FILE *);
 extern bool aarch64_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *);
 extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *);
diff --git a/include/elf/bpf.h b/include/elf/bpf.h
index fb1936010bf..d0fad08c24a 100644
--- a/include/elf/bpf.h
+++ b/include/elf/bpf.h
@@ -34,6 +34,7 @@ START_RELOC_NUMBERS (elf_bpf_reloc_type)
  * It is kept in this file to remind that the value is already taken. */
   RELOC_NUMBER (R_BPF_64_NODYLD32, 		4)
   RELOC_NUMBER (R_BPF_64_32,      		10)
+  RELOC_NUMBER (R_BPF_GNU_64_16,                256)
 END_RELOC_NUMBERS (R_BPF_max)
 
 #endif /* _ELF_BPF_H  */
diff --git a/include/opcode/bpf.h b/include/opcode/bpf.h
new file mode 100644
index 00000000000..f928979f86f
--- /dev/null
+++ b/include/opcode/bpf.h
@@ -0,0 +1,306 @@
+/* bpf.h - BPF opcode list for binutils.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   Contributed by Oracle Inc.
+
+   This file is part of the GNU binutils.
+
+   This is free software; you can redistribute them and/or modify them
+   under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+#ifndef _BPF_H_
+#define _BPF_H_
+
+#include <stdint.h>
+
+/* The BPF ISA has little-endian and big-endian variants.  */
+
+enum bpf_endian
+{
+  BPF_ENDIAN_LITTLE,
+  BPF_ENDIAN_BIG
+};
+
+/* Most BPF instructions are conformed by a single 64-bit instruction
+   word.  The lddw instruction is conformed by two consecutive 64-bit
+   instruction words.  */
+
+typedef uint64_t bpf_insn_word;
+
+/* There are several versions of the BPF ISA.  */
+
+#define BPF_V1 0x1
+#define BPF_V2 0x2
+#define BPF_V3 0x3
+#define BPF_V4 0x4
+#define BPF_XBPF 0xff
+
+/* Masks for the several instruction fields in a BPF instruction.
+   These assume big-endian BPF instructions.  */
+
+#define BPF_CODE     0xff00000000000000UL
+#define BPF_REGS     0x00ff000000000000UL
+#define BPF_DST      0x00f0000000000000UL
+#define BPF_SRC      0x000f000000000000UL
+#define BPF_OFFSET16 0x0000ffff00000000UL
+#define BPF_IMM32    0x00000000ffffffffUL
+
+/* The BPF opcode instruction field is eight bits long and its
+   interpretation depends on the instruction class.
+
+   For arithmetic and jump instructions the 8-bit opcode field is
+   subdivided in:
+
+     op-code:4 op-src:1 op-class:3
+
+   For load/store instructions, the 8-bit opcode field is subdivided
+   in:
+
+     op-mode:3 op-size:2 op-class:3
+
+   All the constants defined below are to be applied on the first
+   64-bit word of a BPF instruction.  Please define them assuming
+   big-endian instructions; the matching and writing routines using
+   the instruction table know how to handle the endianness groups.  */
+
+#define BPF_SRC_X ((uint64_t)0x08 << 56)
+#define BPF_SRC_K ((uint64_t)0x00 << 56)
+
+#define BPF_CODE_ADD ((uint64_t)0x00 << 56)
+#define BPF_CODE_SUB ((uint64_t)0x10 << 56)
+#define BPF_CODE_MUL ((uint64_t)0x20 << 56)
+#define BPF_CODE_DIV ((uint64_t)0x30 << 56)
+#define BPF_CODE_OR  ((uint64_t)0x40 << 56)
+#define BPF_CODE_AND ((uint64_t)0x50 << 56)
+#define BPF_CODE_LSH ((uint64_t)0x60 << 56)
+#define BPF_CODE_RSH ((uint64_t)0x70 << 56)
+#define BPF_CODE_NEG ((uint64_t)0x80 << 56)
+#define BPF_CODE_MOD ((uint64_t)0x90 << 56)
+#define BPF_CODE_XOR ((uint64_t)0xa0 << 56)
+#define BPF_CODE_MOV ((uint64_t)0xb0 << 56)
+#define BPF_CODE_ARSH ((uint64_t)0xc0 << 56)
+#define BPF_CODE_END ((uint64_t)0xd0 << 56)
+
+#define BPF_CODE_JA   ((uint64_t)0x00 << 56)
+#define BPF_CODE_JEQ  ((uint64_t)0x10 << 56)
+#define BPF_CODE_JGT  ((uint64_t)0x20 << 56)
+#define BPF_CODE_JGE  ((uint64_t)0x30 << 56)
+#define BPF_CODE_JSET ((uint64_t)0x40 << 56)
+#define BPF_CODE_JNE  ((uint64_t)0x50 << 56)
+#define BPF_CODE_JSGT ((uint64_t)0x60 << 56)
+#define BPF_CODE_JSGE ((uint64_t)0x70 << 56)
+#define BPF_CODE_CALL ((uint64_t)0x80 << 56)
+#define BPF_CODE_EXIT ((uint64_t)0x90 << 56)
+#define BPF_CODE_JLT  ((uint64_t)0xa0 << 56)
+#define BPF_CODE_JLE  ((uint64_t)0xb0 << 56)
+#define BPF_CODE_JSLT ((uint64_t)0xc0 << 56)
+#define BPF_CODE_JSLE ((uint64_t)0xd0 << 56)
+
+#define BPF_MODE_IMM  ((uint64_t)0x00 << 56)
+#define BPF_MODE_ABS  ((uint64_t)0x20 << 56)
+#define BPF_MODE_IND  ((uint64_t)0x40 << 56)
+#define BPF_MODE_MEM  ((uint64_t)0x60 << 56)
+#define BPF_MODE_ATOMIC ((uint64_t)0xc0 << 56)
+
+#define BPF_SIZE_W  ((uint64_t)0x00 << 56)
+#define BPF_SIZE_H  ((uint64_t)0x08 << 56)
+#define BPF_SIZE_B  ((uint64_t)0x10 << 56)
+#define BPF_SIZE_DW ((uint64_t)0x18 << 56)
+
+#define BPF_CLASS_LD    ((uint64_t)0x00 << 56)
+#define BPF_CLASS_LDX   ((uint64_t)0x01 << 56)
+#define BPF_CLASS_ST    ((uint64_t)0x02 << 56)
+#define BPF_CLASS_STX   ((uint64_t)0x03 << 56)
+#define BPF_CLASS_ALU   ((uint64_t)0x04 << 56)
+#define BPF_CLASS_JMP   ((uint64_t)0x05 << 56)
+#define BPF_CLASS_JMP32 ((uint64_t)0x06 << 56)
+#define BPF_CLASS_ALU64 ((uint64_t)0x07 << 56)
+
+/* Certain instructions (ab)use other instruction fields as opcodes,
+   even if these are multi-byte or infra-byte.  Bleh.  */
+
+#define BPF_OFFSET16_SDIVMOD ((uint64_t)0x1 << 32)
+
+#define BPF_IMM32_END16 ((uint64_t)0x00000010)
+#define BPF_IMM32_END32 ((uint64_t)0x00000020)
+#define BPF_IMM32_END64 ((uint64_t)0x00000040)
+
+#define BPF_IMM32_AADD ((uint64_t)0x00000000)
+#define BPF_IMM32_AOR  ((uint64_t)0x00000040)
+#define BPF_IMM32_AAND ((uint64_t)0x00000050)
+#define BPF_IMM32_AXOR ((uint64_t)0x000000a0)
+#define BPF_IMM32_AFADD ((uint64_t)0x00000001)
+#define BPF_IMM32_AFOR  ((uint64_t)0x00000041)
+#define BPF_IMM32_AFAND ((uint64_t)0x00000051)
+#define BPF_IMM32_AFXOR ((uint64_t)0x000000a1)
+#define BPF_IMM32_AXCHG ((uint64_t)0x000000e1)
+#define BPF_IMM32_ACMP  ((uint64_t)b0x000000f1)
+
+/* Unique identifiers for BPF instructions.  */
+
+enum bpf_insn_id
+{
+  BPF_NOINSN = 0,
+  /* 64-bit load instruction.  */
+  BPF_INSN_LDDW,
+  /* ALU instructions.  */
+  BPF_INSN_ADDR, BPF_INSN_ADDI, BPF_INSN_SUBR, BPF_INSN_SUBI,
+  BPF_INSN_MULR, BPF_INSN_MULI, BPF_INSN_SDIVR, BPF_INSN_SDIVI,
+  BPF_INSN_SMODR, BPF_INSN_SMODI, BPF_INSN_DIVR, BPF_INSN_DIVI,
+  BPF_INSN_MODR, BPF_INSN_MODI, BPF_INSN_ORR, BPF_INSN_ORI,
+  BPF_INSN_ANDR, BPF_INSN_ANDI, BPF_INSN_XORR, BPF_INSN_XORI,
+  BPF_INSN_NEGR, BPF_INSN_NEGI, BPF_INSN_LSHR, BPF_INSN_LSHI,
+  BPF_INSN_RSHR, BPF_INSN_RSHI, BPF_INSN_ARSHR, BPF_INSN_ARSHI,
+  BPF_INSN_MOVR, BPF_INSN_MOVI,
+  /* ALU32 instructions.  */
+  BPF_INSN_ADD32R, BPF_INSN_ADD32I, BPF_INSN_SUB32R, BPF_INSN_SUB32I,
+  BPF_INSN_MUL32R, BPF_INSN_MUL32I, BPF_INSN_SDIV32R, BPF_INSN_SDIV32I,
+  BPF_INSN_SMOD32R, BPF_INSN_SMOD32I, BPF_INSN_DIV32R, BPF_INSN_DIV32I,
+  BPF_INSN_MOD32R, BPF_INSN_MOD32I, BPF_INSN_OR32R, BPF_INSN_OR32I,
+  BPF_INSN_AND32R, BPF_INSN_AND32I, BPF_INSN_XOR32R, BPF_INSN_XOR32I,
+  BPF_INSN_NEG32R, BPF_INSN_NEG32I, BPF_INSN_LSH32R, BPF_INSN_LSH32I,
+  BPF_INSN_RSH32R, BPF_INSN_RSH32I, BPF_INSN_ARSH32R, BPF_INSN_ARSH32I,
+  BPF_INSN_MOV32R, BPF_INSN_MOV32I,
+  /* Endianness conversion instructions.  */
+  BPF_INSN_ENDLE16, BPF_INSN_ENDLE32, BPF_INSN_ENDLE64,
+  BPF_INSN_ENDBE16, BPF_INSN_ENDBE32, BPF_INSN_ENDBE64,
+  /* Absolute load instructions.  */
+  BPF_INSN_LDABSB, BPF_INSN_LDABSH, BPF_INSN_LDABSW, BPF_INSN_LDABSDW,
+  /* Indirect load instructions.  */
+  BPF_INSN_LDINDB, BPF_INSN_LDINDH, BPF_INSN_LDINDW, BPF_INSN_LDINDDW,
+  /* Generic load instructions (to register.)  */
+  BPF_INSN_LDXB, BPF_INSN_LDXH, BPF_INSN_LDXW, BPF_INSN_LDXDW,
+  /* Generic store instructions (from register.)  */
+  BPF_INSN_STXBR, BPF_INSN_STXHR, BPF_INSN_STXWR, BPF_INSN_STXDWR,
+  BPF_INSN_STXBI, BPF_INSN_STXHI, BPF_INSN_STXWI, BPF_INSN_STXDWI,
+  /* Compare-and-jump instructions (reg OP reg.)  */
+  BPF_INSN_JAR, BPF_INSN_JEQR, BPF_INSN_JGTR, BPF_INSN_JSGTR,
+  BPF_INSN_JGER, BPF_INSN_JSGER, BPF_INSN_JLTR, BPF_INSN_JSLTR,
+  BPF_INSN_JSLER, BPF_INSN_JLER, BPF_INSN_JSETR, BPF_INSN_JNER,
+  BPF_INSN_CALLR, BPF_INSN_CALL, BPF_INSN_EXIT,
+  /* Compare-and-jump instructions (reg OP imm.)  */
+  BPF_INSN_JEQI, BPF_INSN_JGTI, BPF_INSN_JSGTI,
+  BPF_INSN_JGEI, BPF_INSN_JSGEI, BPF_INSN_JLTI, BPF_INSN_JSLTI,
+  BPF_INSN_JSLEI, BPF_INSN_JLEI, BPF_INSN_JSETI, BPF_INSN_JNEI,
+  BPF_INSN_CALLI,
+  /* 32-bit compare-and-jump instructions (reg OP reg.)  */
+  BPF_INSN_JEQ32R, BPF_INSN_JGT32R, BPF_INSN_JSGT32R,
+  BPF_INSN_JGE32R, BPF_INSN_JSGE32R, BPF_INSN_JLT32R, BPF_INSN_JSLT32R,
+  BPF_INSN_JSLE32R, BPF_INSN_JLE32R, BPF_INSN_JSET32R, BPF_INSN_JNE32R,
+  /* 32-bit compare-and-jump instructions (reg OP imm.)  */
+  BPF_INSN_JEQ32I, BPF_INSN_JGT32I, BPF_INSN_JSGT32I,
+  BPF_INSN_JGE32I, BPF_INSN_JSGE32I, BPF_INSN_JLT32I, BPF_INSN_JSLT32I,
+  BPF_INSN_JSLE32I, BPF_INSN_JLE32I, BPF_INSN_JSET32I, BPF_INSN_JNE32I,
+  /* Atomic instructions.  */
+  BPF_INSN_AADD, BPF_INSN_AOR, BPF_INSN_AAND, BPF_INSN_AXOR,
+  /* Atomic instructions with fetching.  */
+  BPF_INSN_AFADD, BPF_INSN_AFOR, BPF_INSN_AFAND, BPF_INSN_AFXOR,
+  /* Atomic instructions (32-bit.)  */
+  BPF_INSN_AADD32, BPF_INSN_AOR32, BPF_INSN_AAND32, BPF_INSN_AXOR32,
+  /* Atomic instructions with fetching (32-bit.)  */
+  BPF_INSN_AFADD32, BPF_INSN_AFOR32, BPF_INSN_AFAND32, BPF_INSN_AFXOR32,
+  /* GNU simulator specific instruction.  */
+  BPF_INSN_BRKPT,
+};
+
+/* Entry for a BPF instruction in the opcodes table.  */
+
+struct bpf_opcode
+{
+  /* Unique numerical code for the instruction.  */
+  enum bpf_insn_id id;
+
+  /* The instruction template defines both the syntax of the
+     instruction and the set of the different operands that appear in
+     the instruction.
+
+     Tags:
+     %% - literal %.
+     %dr - destination 64-bit register.
+     %dw - destination 32-bit register.
+     %sr - source 64-bit register.
+     %sw - source 32-bit register.
+     %d32 - 32-bit signed displacement (in 64-bit words minus one.)
+     %d16 - 16-bit signed displacement (in 64-bit words minus one.)
+     %o16 - 16-bit signed offset (in bytes.)
+     %i32 - 32-bit signed immediate.
+     %I32 - Like %i32.
+     %i64 - 64-bit signed immediate.
+     %w - expect zero or more white spaces and print a single space.
+     %W - expect one or more white spaces and print a single space.
+
+     When parsing and printing %o16 and %I32 (but not %i32) an
+     explicit sign is always expected and included.  Therefore, to
+     denote something like `[%r3 + 10]', please use a template like `[
+     %sr %o16]' instead of `[ %sr + %o16 ]'.
+     
+     If %dr, %dw, %sr or %sw are found multiple times in a template,
+     they refer to the same register, i.e. `%rd = le64 %rd' denotes
+     `r2 = le64 r2', but not `r2 = le64 r1'.
+
+     If %i64 appears in a template then the instruction is 128-bits
+     long and composed by two consecutive 64-bit instruction words.
+
+     A white space character means to expect zero or more white
+     spaces, and to print no space.
+
+     There are two templates defined per instruction, corresponding to
+     two used different dialects: a "normal" assembly-like syntax and
+     a "pseudo-c" syntax.  Some toolchains support just one of these
+     dialects.  The GNU Toolchain supports both.  */
+  const char *normal;
+  const char *pseudoc;
+
+  /* The version that introduced this instruction.  Instructions are
+     generally not removed once they get introduced.  */
+  uint8_t version;
+
+  /* Maks marking the opcode fields in the instruction, and the
+     opcodes characterizing it.
+
+     In multi-word instructions these apply to the first word in the
+     instruction.  Note that these values assumes big-endian
+     instructions; code using these field must be aware of the
+     endianness groups to which BPF instructions must conform to and
+     DTRT.  */
+  bpf_insn_word mask;
+  bpf_insn_word opcode;
+};
+
+/* Try to match a BPF instruction given its first instruction word.
+   If no matching instruction is found, return NULL.  */
+
+const struct bpf_opcode *bpf_match_insn (bpf_insn_word word,
+                                         enum bpf_endian endian,
+                                         int version);
+
+/* Operand extractors.
+
+   These all get big-endian instruction words.  Note how the extractor
+   for 64-bit signed immediates requires two instruction words.  */
+
+uint8_t bpf_extract_src (bpf_insn_word word, enum bpf_endian endian);
+uint8_t bpf_extract_dst (bpf_insn_word word, enum bpf_endian endian);
+int16_t bpf_extract_offset16 (bpf_insn_word word, enum bpf_endian endian);
+int32_t bpf_extract_imm32 (bpf_insn_word word, enum bpf_endian endian);
+int64_t bpf_extract_imm64 (bpf_insn_word word1, bpf_insn_word word2,
+                           enum bpf_endian endian);
+
+/* Get the opcode occupying the INDEX position in the opcodes table.
+   The INDEX is zero based.  If the provided index overflows the
+   opcodes table then NULL is returned.  */
+
+const struct bpf_opcode *bpf_get_opcode (unsigned int index);
+
+#endif /* !_BPF_H_ */
diff --git a/ld/testsuite/ld-bpf/call-1.d b/ld/testsuite/ld-bpf/call-1.d
index aad51d5cedc..ae455882e0f 100644
--- a/ld/testsuite/ld-bpf/call-1.d
+++ b/ld/testsuite/ld-bpf/call-1.d
@@ -1,7 +1,7 @@
-#as: --EL
+#as: --EL -mdialect=normal
 #source: foo.s
 #source: bar.s
-#objdump: -dr
+#objdump: -dr -M dec
 #ld: -EL
 #name: CALL with 64_32 reloc
 
diff --git a/ld/testsuite/ld-bpf/call-2.d b/ld/testsuite/ld-bpf/call-2.d
index 3d09095f6be..d00fabaa9b1 100644
--- a/ld/testsuite/ld-bpf/call-2.d
+++ b/ld/testsuite/ld-bpf/call-2.d
@@ -1,7 +1,7 @@
 #as: --EL
 #source: call-2.s
 #source: bar.s
-#objdump: -dr
+#objdump: -dr -M dec
 #ld: -EL
 #name: CALL with disp32 reloc and addend
 
diff --git a/ld/testsuite/ld-bpf/reloc-insn-external-be.d b/ld/testsuite/ld-bpf/reloc-insn-external-be.d
index 455daa701f7..b22ebbd99a2 100644
--- a/ld/testsuite/ld-bpf/reloc-insn-external-be.d
+++ b/ld/testsuite/ld-bpf/reloc-insn-external-be.d
@@ -1,7 +1,7 @@
-#as: --EB
+#as: -EB -mdialect=normal
 #source: reloc-data.s
 #source: reloc-insn-external.s
-#objdump: -dr
+#objdump: -dr -M hex
 #ld: -Tdata=0x20 -EB
 #name: reloc insn external BE
 
diff --git a/ld/testsuite/ld-bpf/reloc-insn-external-le.d b/ld/testsuite/ld-bpf/reloc-insn-external-le.d
index 51066388e84..ba9c305851d 100644
--- a/ld/testsuite/ld-bpf/reloc-insn-external-le.d
+++ b/ld/testsuite/ld-bpf/reloc-insn-external-le.d
@@ -1,7 +1,7 @@
-#as: --EL
+#as: -EL -mdialect=normal
 #source: reloc-data.s
 #source: reloc-insn-external.s
-#objdump: -dr
+#objdump: -dr -M hex
 #ld: -Tdata=0x20 -EL
 #name: reloc insn external LE
 
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 578fdc056c5..7cc16d58cbc 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -59,7 +59,6 @@ BUILD_LIB_DEPS = @BUILD_LIB_DEPS@
 # Header files.
 HFILES = \
 	aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
-	bpf-desc.h bpf-opc.h \
 	cris-desc.h cris-opc.h \
 	epiphany-desc.h epiphany-opc.h \
 	fr30-desc.h fr30-opc.h \
@@ -94,10 +93,6 @@ TARGET64_LIBOPCODES_CFILES = \
 	aarch64-opc-2.c \
 	alpha-dis.c \
 	alpha-opc.c \
-	bpf-asm.c \
-	bpf-desc.c \
-	bpf-dis.c \
-	bpf-ibld.c \
 	bpf-opc.c \
 	ia64-dis.c \
 	ia64-opc.c \
@@ -352,7 +347,6 @@ CGENDEPS = \
 CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
 
 if CGEN_MAINT
-BPF_DEPS = stamp-bpf
 CRIS_DEPS = stamp-cris
 EPIPHANY_DEPS = stamp-epiphany
 FR30_DEPS = stamp-fr30
@@ -367,7 +361,6 @@ MT_DEPS = stamp-mt
 OR1K_DEPS = stamp-or1k
 XSTORMY16_DEPS = stamp-xstormy16
 else
-BPF_DEPS =
 CRIS_DEPS =
 EPIPHANY_DEPS =
 FR30_DEPS =
@@ -400,15 +393,6 @@ run-cgen-all:
 
 # For now, require developers to configure with --enable-cgen-maint.
 
-$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
-		$(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
-		$(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
-	@true
-
-stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
-	$(MAKE) run-cgen arch=bpf prefix=bpf \
-		archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
-
 $(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS)
 	@true
 
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 2db307e8d7c..dcd0e9f2dce 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -450,7 +450,6 @@ BFD_H = ../bfd/bfd.h
 # Header files.
 HFILES = \
 	aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
-	bpf-desc.h bpf-opc.h \
 	cris-desc.h cris-opc.h \
 	epiphany-desc.h epiphany-opc.h \
 	fr30-desc.h fr30-opc.h \
@@ -486,10 +485,6 @@ TARGET64_LIBOPCODES_CFILES = \
 	aarch64-opc-2.c \
 	alpha-dis.c \
 	alpha-opc.c \
-	bpf-asm.c \
-	bpf-desc.c \
-	bpf-dis.c \
-	bpf-ibld.c \
 	bpf-opc.c \
 	ia64-dis.c \
 	ia64-opc.c \
@@ -708,8 +703,6 @@ CGENDEPS = \
 	cgen-asm.in cgen-dis.in cgen-ibld.in
 
 CGEN_CPUS = cris epiphany fr30 frv ip2k iq2000 lm32 m32c m32r mep mt or1k xstormy16
-@CGEN_MAINT_FALSE@BPF_DEPS = 
-@CGEN_MAINT_TRUE@BPF_DEPS = stamp-bpf
 @CGEN_MAINT_FALSE@CRIS_DEPS = 
 @CGEN_MAINT_TRUE@CRIS_DEPS = stamp-cris
 @CGEN_MAINT_FALSE@EPIPHANY_DEPS = 
@@ -883,10 +876,6 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/arm-dis.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/avr-dis.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bfin-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-asm.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-desc.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-dis.Plo@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-ibld.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bpf-opc.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-asm.Plo@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cgen-bitset.Plo@am__quote@
@@ -1385,15 +1374,6 @@ run-cgen-all:
 
 # For now, require developers to configure with --enable-cgen-maint.
 
-$(srcdir)/bpf-desc.h $(srcdir)/bpf-desc.c $(srcdir)/bpf-opc.h \
-		$(srcdir)/bpf-opc.c $(srcdir)/bpf-ibld.c \
-		$(srcdir)/bpf-asm.c $(srcdir)/bpf-dis.c: $(BPF_DEPS)
-	@true
-
-stamp-bpf: $(CGENDEPS) $(CPUDIR)/bpf.cpu $(CPUDIR)/bpf.opc
-	$(MAKE) run-cgen arch=bpf prefix=bpf \
-		archfile=$(CPUDIR)/bpf.cpu opcfile=$(CPUDIR)/bpf.opc
-
 $(srcdir)/cris-desc.h $(srcdir)/cris-desc.c $(srcdir)/cris-opc.h: $(CRIS_DEPS)
 	@true
 
diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c
index 0a345179569..a4dc3dc2523 100644
--- a/opcodes/bpf-dis.c
+++ b/opcodes/bpf-dis.c
@@ -1,631 +1,284 @@
-/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
-/* Disassembler interface for targets using CGEN. -*- C -*-
-   CGEN: Cpu tools GENerator
+/* bpf-dis.c - BPF disassembler.
+   Copyright (C) 2023 Free Software Foundation, Inc.
 
-   THIS FILE IS MACHINE GENERATED WITH CGEN.
-   - the resultant file is machine generated, cgen-dis.in isn't
+   Contributed by Oracle Inc.
 
-   Copyright (C) 1996-2023 Free Software Foundation, Inc.
+   This file is part of the GNU binutils.
 
-   This file is part of libopcodes.
-
-   This library is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
+   This is free software; you can redistribute them and/or modify them
+   under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3, or (at your option)
    any later version.
 
-   It is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
 
    You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation, Inc.,
-   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-/* ??? Eventually more and more of this stuff can go to cpu-independent files.
-   Keep that in mind.  */
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
 
 #include "sysdep.h"
-#include <stdio.h>
-#include "ansidecl.h"
 #include "disassemble.h"
-#include "bfd.h"
-#include "symcat.h"
 #include "libiberty.h"
-#include "bpf-desc.h"
-#include "bpf-opc.h"
 #include "opintl.h"
+#include "opcode/bpf.h"
 
-/* Default text to print if an instruction isn't recognized.  */
-#define UNKNOWN_INSN_MSG _("*unknown*")
-
-static void print_normal
-  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
-static void print_address
-  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
-static void print_keyword
-  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
-static void print_insn_normal
-  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
-static int print_insn
-  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
-static int default_print_insn
-  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
-static int read_insn
-  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
-   unsigned long *);
-
-/* -- disassembler routines inserted here.  */
-
-/* -- dis.c */
-
-/* We need to customize the disassembler a bit:
-   - Use 8 bytes per line by default.
-*/
-
-#define CGEN_PRINT_INSN bpf_print_insn
-
-static int
-bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
-{
-  bfd_byte buf[CGEN_MAX_INSN_SIZE];
-  int buflen;
-  int status;
-
-  info->bytes_per_chunk = 1;
-  info->bytes_per_line = 8;
-
-  /* Attempt to read the base part of the insn.  */
-  buflen = cd->base_insn_bitsize / 8;
-  status = (*info->read_memory_func) (pc, buf, buflen, info);
-
-  /* Try again with the minimum part, if min < base.  */
-  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
-    {
-      buflen = cd->min_insn_bitsize / 8;
-      status = (*info->read_memory_func) (pc, buf, buflen, info);
-    }
-
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, pc, info);
-      return -1;
-    }
-
-  return print_insn (cd, pc, info, buf, buflen);
-}
+#include <string.h>
+#include <inttypes.h>
 
-/* Signed immediates should be printed in hexadecimal.  */
+/* This disassembler supports two different syntaxes for BPF assembly.
+   One is called "normal" and has the typical form for assembly
+   languages, with mnemonics and the like.  The othe is called
+   "pseudoc" and looks like C.  */
 
-static void
-print_immediate (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
-                 void *dis_info,
-                 int64_t value,
-                 unsigned int attrs ATTRIBUTE_UNUSED,
-                 bfd_vma pc ATTRIBUTE_UNUSED,
-                 int length ATTRIBUTE_UNUSED)
+enum bpf_dialect
 {
-  disassemble_info *info = (disassemble_info *) dis_info;
-
-  if (value <= 9)
-    (*info->fprintf_func) (info->stream, "%" PRId64, value);
-  else
-    (*info->fprintf_func) (info->stream, "%#" PRIx64, value);
-
-  /* This is to avoid -Wunused-function for print_normal.  */
-  if (0)
-    print_normal (cd, dis_info, value, attrs, pc, length);
-}
-
-/* Endianness bit sizes should be printed in decimal.  */
-
-static void
-print_endsize (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
-               void *dis_info,
-               unsigned long value,
-               unsigned int attrs ATTRIBUTE_UNUSED,
-               bfd_vma pc ATTRIBUTE_UNUSED,
-               int length ATTRIBUTE_UNUSED)
-{
-  disassemble_info *info = (disassemble_info *) dis_info;
-  (*info->fprintf_func) (info->stream, "%lu", value);
-}
-
-
-/* -- */
-
-void bpf_cgen_print_operand
-  (CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int);
+  BPF_DIALECT_NORMAL,
+  BPF_DIALECT_PSEUDOC
+};
 
-/* Main entry point for printing operands.
-   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
-   of dis-asm.h on cgen.h.
+/* Global configuration for the disassembler.  */
 
-   This function is basically just a big switch statement.  Earlier versions
-   used tables to look up the function to use, but
-   - if the table contains both assembler and disassembler functions then
-     the disassembler contains much of the assembler and vice-versa,
-   - there's a lot of inlining possibilities as things grow,
-   - using a switch statement avoids the function call overhead.
+static enum bpf_dialect asm_dialect = BPF_DIALECT_NORMAL;
+static int asm_bpf_version = BPF_V4;
+static int asm_obase = 10;
 
-   This function could be moved into `print_insn_normal', but keeping it
-   separate makes clear the interface between `print_insn_normal' and each of
-   the handlers.  */
+/* Print BPF specific command-line options.  */
 
 void
-bpf_cgen_print_operand (CGEN_CPU_DESC cd,
-			   int opindex,
-			   void * xinfo,
-			   CGEN_FIELDS *fields,
-			   void const *attrs ATTRIBUTE_UNUSED,
-			   bfd_vma pc,
-			   int length)
+print_bpf_disassembler_options (FILE *stream)
 {
-  disassemble_info *info = (disassemble_info *) xinfo;
-
-  switch (opindex)
-    {
-    case BPF_OPERAND_DISP16 :
-      print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
-      break;
-    case BPF_OPERAND_DISP32 :
-      print_normal (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
-      break;
-    case BPF_OPERAND_DSTBE :
-      print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstbe, 0);
-      break;
-    case BPF_OPERAND_DSTLE :
-      print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_dstle, 0);
-      break;
-    case BPF_OPERAND_ENDSIZE :
-      print_endsize (cd, info, fields->f_imm32, 0, pc, length);
-      break;
-    case BPF_OPERAND_IMM32 :
-      print_immediate (cd, info, fields->f_imm32, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
-      break;
-    case BPF_OPERAND_IMM64 :
-      print_immediate (cd, info, fields->f_imm64, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length);
-      break;
-    case BPF_OPERAND_OFFSET16 :
-      print_immediate (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
-      break;
-    case BPF_OPERAND_SRCBE :
-      print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcbe, 0);
-      break;
-    case BPF_OPERAND_SRCLE :
-      print_keyword (cd, info, & bpf_cgen_opval_h_gpr, fields->f_srcle, 0);
-      break;
-
-    default :
-      /* xgettext:c-format */
-      opcodes_error_handler
-	(_("internal error: unrecognized field %d while printing insn"),
-	 opindex);
-      abort ();
-  }
+  fprintf (stream, _("\n\
+The following BPF specific disassembler options are supported for use\n\
+with the -M switch (multiple options should be separated by commas):\n"));
+  fprintf (stream, "\n");
+  fprintf (stream, _("\
+      pseudoc                  Use pseudo-c syntax.\n\
+      v1,v2,v3,v4,xbpf         Version of the BPF ISA to use.\n\
+      hex,oct,dec              Output numerical base for immediates.\n"));
 }
 
-cgen_print_fn * const bpf_cgen_print_handlers[] =
-{
-  print_insn_normal,
-};
-
-
-void
-bpf_cgen_init_dis (CGEN_CPU_DESC cd)
-{
-  bpf_cgen_init_opcode_table (cd);
-  bpf_cgen_init_ibld_table (cd);
-  cd->print_handlers = & bpf_cgen_print_handlers[0];
-  cd->print_operand = bpf_cgen_print_operand;
-}
-
-
-/* Default print handler.  */
+/* Parse BPF specific command-line options.  */
 
 static void
-print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
-	      void *dis_info,
-	      long value,
-	      unsigned int attrs,
-	      bfd_vma pc ATTRIBUTE_UNUSED,
-	      int length ATTRIBUTE_UNUSED)
+parse_bpf_dis_option (const char *option)
 {
-  disassemble_info *info = (disassemble_info *) dis_info;
-
-  /* Print the operand as directed by the attributes.  */
-  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* nothing to do */
-  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
-    (*info->fprintf_func) (info->stream, "%ld", value);
+  if (strcmp (option, "pseudoc") == 0)
+    asm_dialect = BPF_DIALECT_PSEUDOC;
+  else if (strcmp (option, "v1") == 0)
+    asm_bpf_version = BPF_V1;
+  else if (strcmp (option, "v2") == 0)
+    asm_bpf_version = BPF_V2;
+  else if (strcmp (option, "v3") == 0)
+    asm_bpf_version = BPF_V3;
+  else if (strcmp (option, "v4") == 0)
+    asm_bpf_version = BPF_V4;
+  else if (strcmp (option, "xbpf") == 0)
+    asm_bpf_version = BPF_XBPF;
+  else if (strcmp (option, "hex") == 0)
+    asm_obase = 16;
+  else if (strcmp (option, "oct") == 0)
+    asm_obase = 8;
+  else if (strcmp (option, "dec") == 0)
+    asm_obase = 10;
   else
-    (*info->fprintf_func) (info->stream, "0x%lx", value);
+    /* xgettext:c-format */
+    opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
 }
 
-/* Default address handler.  */
-
 static void
-print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
-	       void *dis_info,
-	       bfd_vma value,
-	       unsigned int attrs,
-	       bfd_vma pc ATTRIBUTE_UNUSED,
-	       int length ATTRIBUTE_UNUSED)
+parse_bpf_dis_options (const char *opts_in)
 {
-  disassemble_info *info = (disassemble_info *) dis_info;
-
-  /* Print the operand as directed by the attributes.  */
-  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
-    ; /* Nothing to do.  */
-  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
-    (*info->print_address_func) (value, info);
-  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
-    (*info->print_address_func) (value, info);
-  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
-    (*info->fprintf_func) (info->stream, "%ld", (long) value);
-  else
-    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
-}
+  char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts;
 
-/* Keyword print handler.  */
-
-static void
-print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
-	       void *dis_info,
-	       CGEN_KEYWORD *keyword_table,
-	       long value,
-	       unsigned int attrs ATTRIBUTE_UNUSED)
-{
-  disassemble_info *info = (disassemble_info *) dis_info;
-  const CGEN_KEYWORD_ENTRY *ke;
+  for ( ; opt_end != NULL; opt = opt_end + 1)
+    {
+      if ((opt_end = strchr (opt, ',')) != NULL)
+	*opt_end = 0;
+      parse_bpf_dis_option (opt);
+    }
 
-  ke = cgen_keyword_lookup_value (keyword_table, value);
-  if (ke != NULL)
-    (*info->fprintf_func) (info->stream, "%s", ke->name);
-  else
-    (*info->fprintf_func) (info->stream, "???");
+  free (opts);
 }
-
-/* Default insn printer.
 
-   DIS_INFO is defined as `void *' so the disassembler needn't know anything
-   about disassemble_info.  */
+/* Auxiliary function used in print_insn_bpf below.  */
 
 static void
-print_insn_normal (CGEN_CPU_DESC cd,
-		   void *dis_info,
-		   const CGEN_INSN *insn,
-		   CGEN_FIELDS *fields,
-		   bfd_vma pc,
-		   int length)
+print_register (disassemble_info *info,
+                const char *tag, uint8_t regno)
 {
-  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
-  disassemble_info *info = (disassemble_info *) dis_info;
-  const CGEN_SYNTAX_CHAR_TYPE *syn;
-
-  CGEN_INIT_PRINT (cd);
-
-  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
-    {
-      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
-	{
-	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
-	  continue;
-	}
-      if (CGEN_SYNTAX_CHAR_P (*syn))
-	{
-	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
-	  continue;
-	}
-
-      /* We have an operand.  */
-      bpf_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
-				 fields, CGEN_INSN_ATTRS (insn), pc, length);
-    }
+  const char *fmt
+    = (asm_dialect == BPF_DIALECT_NORMAL
+       ? "%%r%d"
+       : ((*(tag + 2) == 'w')
+          ? "w%d"
+          : "r%d"));
+
+  (*info->fprintf_styled_func) (info->stream, dis_style_register, fmt, regno);
 }
-
-/* Subroutine of print_insn. Reads an insn into the given buffers and updates
-   the extract info.
-   Returns 0 if all is well, non-zero otherwise.  */
-
-static int
-read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
-	   bfd_vma pc,
-	   disassemble_info *info,
-	   bfd_byte *buf,
-	   int buflen,
-	   CGEN_EXTRACT_INFO *ex_info,
-	   unsigned long *insn_value)
-{
-  int status = (*info->read_memory_func) (pc, buf, buflen, info);
 
-  if (status != 0)
-    {
-      (*info->memory_error_func) (status, pc, info);
-      return -1;
-    }
-
-  ex_info->dis_info = info;
-  ex_info->valid = (1 << buflen) - 1;
-  ex_info->insn_bytes = buf;
-
-  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
-  return 0;
-}
+/* Main entry point.
+   Print one instruction from PC on INFO->STREAM.
+   Return the size of the instruction (in bytes).  */
 
-/* Utility to print an insn.
-   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
-   The result is the size of the insn in bytes or zero for an unknown insn
-   or -1 if an error occurs fetching data (memory_error_func will have
-   been called).  */
-
-static int
-print_insn (CGEN_CPU_DESC cd,
-	    bfd_vma pc,
-	    disassemble_info *info,
-	    bfd_byte *buf,
-	    unsigned int buflen)
+int
+print_insn_bpf (bfd_vma pc, disassemble_info *info)
 {
-  CGEN_INSN_INT insn_value;
-  const CGEN_INSN_LIST *insn_list;
-  CGEN_EXTRACT_INFO ex_info;
-  int basesize;
-
-  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
-  basesize = cd->base_insn_bitsize < buflen * 8 ?
-                                     cd->base_insn_bitsize : buflen * 8;
-  insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian);
-
-
-  /* Fill in ex_info fields like read_insn would.  Don't actually call
-     read_insn, since the incoming buffer is already read (and possibly
-     modified a la m32r).  */
-  ex_info.valid = (1 << buflen) - 1;
-  ex_info.dis_info = info;
-  ex_info.insn_bytes = buf;
-
-  /* The instructions are stored in hash lists.
-     Pick the first one and keep trying until we find the right one.  */
-
-  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
-  while (insn_list != NULL)
+  int insn_size = 8, status;
+  bfd_byte insn_bytes[16];
+  bpf_insn_word word = 0;
+  const struct bpf_opcode *insn = NULL;
+  enum bpf_endian endian = (info->endian == BFD_ENDIAN_LITTLE
+                            ? BPF_ENDIAN_LITTLE : BPF_ENDIAN_BIG);
+
+  /* Handle bpf-specific command-line options.  */
+  if (info->disassembler_options != NULL)
     {
-      const CGEN_INSN *insn = insn_list->insn;
-      CGEN_FIELDS fields;
-      int length;
-      unsigned long insn_value_cropped;
-
-#ifdef CGEN_VALIDATE_INSN_SUPPORTED
-      /* Not needed as insn shouldn't be in hash lists if not supported.  */
-      /* Supported by this cpu?  */
-      if (! bpf_cgen_insn_supported (cd, insn))
-        {
-          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
-	  continue;
-        }
-#endif
-
-      /* Basic bit mask must be correct.  */
-      /* ??? May wish to allow target to defer this check until the extract
-	 handler.  */
-
-      /* Base size may exceed this instruction's size.  Extract the
-         relevant part from the buffer. */
-      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
-	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
-	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
-					   info->endian == BFD_ENDIAN_BIG);
-      else
-	insn_value_cropped = insn_value;
-
-      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
-	  == CGEN_INSN_BASE_VALUE (insn))
-	{
-	  /* Printing is handled in two passes.  The first pass parses the
-	     machine insn and extracts the fields.  The second pass prints
-	     them.  */
-
-	  /* Make sure the entire insn is loaded into insn_value, if it
-	     can fit.  */
-	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
-	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
-	    {
-	      unsigned long full_insn_value;
-	      int rc = read_insn (cd, pc, info, buf,
-				  CGEN_INSN_BITSIZE (insn) / 8,
-				  & ex_info, & full_insn_value);
-	      if (rc != 0)
-		return rc;
-	      length = CGEN_EXTRACT_FN (cd, insn)
-		(cd, insn, &ex_info, full_insn_value, &fields, pc);
-	    }
-	  else
-	    length = CGEN_EXTRACT_FN (cd, insn)
-	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
-
-	  /* Length < 0 -> error.  */
-	  if (length < 0)
-	    return length;
-	  if (length > 0)
-	    {
-	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
-	      /* Length is in bits, result is in bytes.  */
-	      return length / 8;
-	    }
-	}
-
-      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+      parse_bpf_dis_options (info->disassembler_options);
+      /* Avoid repeteadly parsing the options.  */
+      info->disassembler_options = NULL;
     }
 
-  return 0;
-}
-
-/* Default value for CGEN_PRINT_INSN.
-   The result is the size of the insn in bytes or zero for an unknown insn
-   or -1 if an error occured fetching bytes.  */
-
-#ifndef CGEN_PRINT_INSN
-#define CGEN_PRINT_INSN default_print_insn
-#endif
-
-static int
-default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
-{
-  bfd_byte buf[CGEN_MAX_INSN_SIZE];
-  int buflen;
-  int status;
-
-  /* Attempt to read the base part of the insn.  */
-  buflen = cd->base_insn_bitsize / 8;
-  status = (*info->read_memory_func) (pc, buf, buflen, info);
-
-  /* Try again with the minimum part, if min < base.  */
-  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
-    {
-      buflen = cd->min_insn_bitsize / 8;
-      status = (*info->read_memory_func) (pc, buf, buflen, info);
-    }
+  /* Print eight bytes per line.  */
+  info->bytes_per_chunk = 1;
+  info->bytes_per_line = 8;
 
+  /* Read an instruction word.  */
+  status = (*info->read_memory_func) (pc, insn_bytes, 8, info);
   if (status != 0)
     {
       (*info->memory_error_func) (status, pc, info);
       return -1;
     }
+  word = (bpf_insn_word) bfd_getb64 (insn_bytes);
 
-  return print_insn (cd, pc, info, buf, buflen);
-}
+  /* Try to match an instruction with it.  */
+  insn = bpf_match_insn (word, endian, asm_bpf_version);
 
-/* Main entry point.
-   Print one instruction from PC on INFO->STREAM.
-   Return the size of the instruction (in bytes).  */
-
-typedef struct cpu_desc_list
-{
-  struct cpu_desc_list *next;
-  CGEN_BITSET *isa;
-  int mach;
-  int endian;
-  int insn_endian;
-  CGEN_CPU_DESC cd;
-} cpu_desc_list;
-
-int
-print_insn_bpf (bfd_vma pc, disassemble_info *info)
-{
-  static cpu_desc_list *cd_list = 0;
-  cpu_desc_list *cl = 0;
-  static CGEN_CPU_DESC cd = 0;
-  static CGEN_BITSET *prev_isa;
-  static int prev_mach;
-  static int prev_endian;
-  static int prev_insn_endian;
-  int length;
-  CGEN_BITSET *isa;
-  int mach;
-  int endian = (info->endian == BFD_ENDIAN_BIG
-		? CGEN_ENDIAN_BIG
-		: CGEN_ENDIAN_LITTLE);
-  int insn_endian = (info->endian_code == BFD_ENDIAN_BIG
-                     ? CGEN_ENDIAN_BIG
-                     : CGEN_ENDIAN_LITTLE);
-  enum bfd_architecture arch;
-
-  /* ??? gdb will set mach but leave the architecture as "unknown" */
-#ifndef CGEN_BFD_ARCH
-#define CGEN_BFD_ARCH bfd_arch_bpf
-#endif
-  arch = info->arch;
-  if (arch == bfd_arch_unknown)
-    arch = CGEN_BFD_ARCH;
-
-  /* There's no standard way to compute the machine or isa number
-     so we leave it to the target.  */
-#ifdef CGEN_COMPUTE_MACH
-  mach = CGEN_COMPUTE_MACH (info);
-#else
-  mach = info->mach;
-#endif
-
-#ifdef CGEN_COMPUTE_ISA
-  {
-    static CGEN_BITSET *permanent_isa;
-
-    if (!permanent_isa)
-      permanent_isa = cgen_bitset_create (MAX_ISAS);
-    isa = permanent_isa;
-    cgen_bitset_clear (isa);
-    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
-  }
-#else
-  isa = info->private_data;
-#endif
-
-  /* If we've switched cpu's, try to find a handle we've used before */
-  if (cd
-      && (cgen_bitset_compare (isa, prev_isa) != 0
-	  || mach != prev_mach
-	  || endian != prev_endian))
+  /* Print it out.  */
+  if (insn)
     {
-      cd = 0;
-      for (cl = cd_list; cl; cl = cl->next)
-	{
-	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
-	      cl->mach == mach &&
-	      cl->endian == endian)
-	    {
-	      cd = cl->cd;
- 	      prev_isa = cd->isas;
-	      break;
-	    }
-	}
-    }
+      const char *insn_tmpl
+        = asm_dialect == BPF_DIALECT_NORMAL ? insn->normal : insn->pseudoc;
+      const char *p = insn_tmpl;
 
-  /* If we haven't initialized yet, initialize the opcode table.  */
-  if (! cd)
-    {
-      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
-      const char *mach_name;
-
-      if (!arch_type)
-	abort ();
-      mach_name = arch_type->printable_name;
-
-      prev_isa = cgen_bitset_copy (isa);
-      prev_mach = mach;
-      prev_endian = endian;
-      prev_insn_endian = insn_endian;
-      cd = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
-				 CGEN_CPU_OPEN_BFDMACH, mach_name,
-				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
-                                 CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian,
-				 CGEN_CPU_OPEN_END);
-      if (!cd)
-	abort ();
-
-      /* Save this away for future reference.  */
-      cl = xmalloc (sizeof (struct cpu_desc_list));
-      cl->cd = cd;
-      cl->isa = prev_isa;
-      cl->mach = mach;
-      cl->endian = endian;
-      cl->next = cd_list;
-      cd_list = cl;
-
-      bpf_cgen_init_dis (cd);
+      /* Print the template contents completed with the instruction
+         operands.  */
+      for (p = insn_tmpl; *p != '\0';)
+        {
+          switch (*p)
+            {
+            case ' ':
+              /* Single space prints to nothing.  */
+              p += 1;
+              break;
+            case '%':
+              if (*(p + 1) == '%')
+                {
+                  (*info->fprintf_styled_func) (info->stream, dis_style_text, "%%");
+                  p += 2;
+                }
+              else if (*(p + 1) == 'w' || *(p + 1) == 'W')
+                {
+                  /* %W prints to a single space.  */
+                  (*info->fprintf_styled_func) (info->stream, dis_style_text, " ");
+                  p += 2;
+                }
+              else if (strncmp (p, "%dr", 3) == 0)
+                {
+                  print_register (info, p, bpf_extract_dst (word, endian));
+                  p += 3;
+                }
+              else if (strncmp (p, "%sr", 3) == 0)
+                {
+                  print_register (info, p, bpf_extract_src (word, endian));
+                  p += 3;
+                }
+              else if (strncmp (p, "%dw", 3) == 0)
+                {
+                  print_register (info, p, bpf_extract_dst (word, endian));
+                  p += 3;
+                }
+              else if (strncmp (p, "%sw", 3) == 0)
+                {
+                  print_register (info, p, bpf_extract_src (word, endian));
+                  p += 3;
+                }
+              else if (strncmp (p, "%i32", 4) == 0
+                       || strncmp (p, "%d32", 4) == 0
+                       || strncmp (p, "%I32", 4) == 0)
+                {
+                  int32_t imm32 = bpf_extract_imm32 (word, endian);
+
+                  if (p[1] == 'I')
+                    (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+                                                  "%s",
+                                                  asm_obase != 10 || imm32 > 0 ? "+" : "");
+                  (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+                                                asm_obase == 10 ? "%" PRIi32
+                                                : asm_obase == 8 ? "%" PRIo32
+                                                : "0x%" PRIx32,
+                                                imm32);
+                  p += 4;
+                }
+              else if (strncmp (p, "%o16", 4) == 0
+                       || strncmp (p, "%d16", 4) == 0)
+                {
+                  int16_t offset16 = bpf_extract_offset16 (word, endian);
+
+                  if (p[1] == 'o')
+                    (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+                                                  "%s",
+                                                  asm_obase != 10 || offset16 > 0 ? "+" : "");
+                  if (asm_obase == 16 || asm_obase == 8)
+                    (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+                                                  asm_obase == 8 ? "0%" PRIo16 : "0x%" PRIx16,
+                                                  (uint16_t) offset16);
+                  else
+                    (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+                                                  "%" PRIi16, offset16);
+                  p += 4;
+                }
+              else if (strncmp (p, "%i64", 4) == 0)
+                {
+                  bpf_insn_word word2 = 0;
+
+                  status = (*info->read_memory_func) (pc + 8, insn_bytes + 8,
+                                                          8, info);
+                  if (status != 0)
+                    {
+                      (*info->memory_error_func) (status, pc + 8, info);
+                      return -1;
+                    }
+                  word2 = (bpf_insn_word) bfd_getb64 (insn_bytes + 8);
+
+                  (*info->fprintf_styled_func) (info->stream, dis_style_immediate,
+                                                asm_obase == 10 ? "%" PRIi64
+                                                : asm_obase == 8 ? "0%" PRIo64
+                                                : "0x%" PRIx64,
+                                                bpf_extract_imm64 (word, word2, endian));
+                  insn_size = 16;
+                  p += 4;
+                }
+              else
+                {
+                  /* xgettext:c-format */
+                  opcodes_error_handler (_("# internal error, unknown tag in opcode template (%s)"),
+                                         insn_tmpl);
+                  return -1;
+                }
+              break;
+            default:
+              /* Any other character is printed literally.  */
+              (*info->fprintf_styled_func) (info->stream, dis_style_text, "%c", *p);
+              p += 1;
+            }
+        }
     }
+  else
+    (*info->fprintf_styled_func) (info->stream, dis_style_text, "<unknown>");
 
-  /* We try to have as much common code as possible.
-     But at this point some targets need to take over.  */
-  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
-     but if not possible try to move this hook elsewhere rather than
-     have two hooks.  */
-  length = CGEN_PRINT_INSN (cd, pc, info);
-  if (length > 0)
-    return length;
-  if (length < 0)
-    return -1;
-
-  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
-  return cd->default_insn_bitsize / 8;
+  return insn_size;
 }
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index 1cc06f7cbf6..f89d93a5c78 100644
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -1,1863 +1,484 @@
-/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
-/* Instruction opcode table for bpf.
+/* bpf-opc.c - BPF opcodes.
+   Copyright (C) 2023 Free Software Foundation, Inc.
 
-THIS FILE IS MACHINE GENERATED WITH CGEN.
+   Contributed by Oracle Inc.
 
-Copyright (C) 1996-2023 Free Software Foundation, Inc.
+   This file is part of the GNU binutils.
 
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
-   This file is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
+   This is free software; you can redistribute them and/or modify them
+   under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3, or (at your option)
    any later version.
 
-   It is distributed in the hope that it will be useful, but WITHOUT
-   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-   License for more details.
-
-   You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#include "sysdep.h"
-#include "ansidecl.h"
-#include "bfd.h"
-#include "symcat.h"
-#include "bpf-desc.h"
-#include "bpf-opc.h"
-#include "libiberty.h"
-
-/* -- opc.c */
-
-/* -- asm.c */
-/* The hash functions are recorded here to help keep assembler code out of
-   the disassembler and vice versa.  */
-
-static int asm_hash_insn_p        (const CGEN_INSN *);
-static unsigned int asm_hash_insn (const char *);
-static int dis_hash_insn_p        (const CGEN_INSN *);
-static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
-
-/* Instruction formats.  */
-
-#define F(f) & bpf_cgen_ifld_table[BPF_##f]
-static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
-  0, 0, 0x0, { { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addile ATTRIBUTE_UNUSED = {
-  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrle ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_negle ATTRIBUTE_UNUSED = {
-  64, 64, 0xfffffffffffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addibe ATTRIBUTE_UNUSED = {
-  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_addrbe ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffffffff00ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_negbe ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffffffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_endlele ATTRIBUTE_UNUSED = {
-  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_endlebe ATTRIBUTE_UNUSED = {
-  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_lddwle ATTRIBUTE_UNUSED = {
-  64, 128, 0xfffff0ff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_lddwbe ATTRIBUTE_UNUSED = {
-  64, 128, 0xffff0fff, { { F (F_IMM64) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldabsw ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldindwle ATTRIBUTE_UNUSED = {
-  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldindwbe ATTRIBUTE_UNUSED = {
-  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldxwle ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_ldxwbe ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_stble ATTRIBUTE_UNUSED = {
-  64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_DSTLE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_stbbe ATTRIBUTE_UNUSED = {
-  64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_MODE) }, { F (F_OP_SIZE) }, { F (F_SRCBE) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jeqile ATTRIBUTE_UNUSED = {
-  64, 64, 0xf0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jeqrle ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jeqibe ATTRIBUTE_UNUSED = {
-  64, 64, 0xfff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffff000000ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = {
-  64, 64, 0xffff0fff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_SRCLE) }, { F (F_OP_CODE) }, { F (F_DSTLE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
-
-static const CGEN_IFMT ifmt_callbe ATTRIBUTE_UNUSED = {
-  64, 64, 0xfffff0ff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
 
-static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffff0000ffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
 
-static const CGEN_IFMT ifmt_exit ATTRIBUTE_UNUSED = {
-  64, 64, 0xffffffffffffffff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
-};
+#include "config.h"
+#include <stdlib.h>
+#include "opcode/bpf.h"
 
-#undef F
+/* Note that the entries in the opcodes table below are accessed
+   sequentially when matching instructions per opcode, and also when
+   parsing.  Please take care to keep the entries sorted
+   accordingly!  */
 
-#define A(a) (1 << CGEN_INSN_##a)
-#define OPERAND(op) BPF_OPERAND_##op
-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-
-/* The instruction table.  */
-
-static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
+const struct bpf_opcode bpf_opcodes[] =
 {
-  /* Special null first entry.
-     A `num' value of zero is thus invalid.
-     Also, the special `invalid' insn resides here.  */
-  { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
-/* add $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x7 }
-  },
-/* add $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xf }
-  },
-/* add32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x4 }
-  },
-/* add32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xc }
-  },
-/* sub $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x17 }
-  },
-/* sub $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x1f }
-  },
-/* sub32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x14 }
-  },
-/* sub32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x1c }
-  },
-/* mul $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x27 }
-  },
-/* mul $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x2f }
-  },
-/* mul32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x24 }
-  },
-/* mul32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x2c }
-  },
-/* div $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x37 }
-  },
-/* div $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x3f }
-  },
-/* div32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x34 }
-  },
-/* div32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x3c }
-  },
-/* or $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x47 }
-  },
-/* or $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x4f }
-  },
-/* or32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x44 }
-  },
-/* or32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x4c }
-  },
-/* and $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x57 }
-  },
-/* and $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x5f }
-  },
-/* and32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x54 }
-  },
-/* and32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x5c }
-  },
-/* lsh $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x67 }
-  },
-/* lsh $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x6f }
-  },
-/* lsh32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x64 }
-  },
-/* lsh32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x6c }
-  },
-/* rsh $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x77 }
-  },
-/* rsh $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x7f }
-  },
-/* rsh32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x74 }
-  },
-/* rsh32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x7c }
-  },
-/* mod $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x97 }
-  },
-/* mod $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x9f }
-  },
-/* mod32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0x94 }
-  },
-/* mod32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0x9c }
-  },
-/* xor $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xa7 }
-  },
-/* xor $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xaf }
-  },
-/* xor32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xa4 }
-  },
-/* xor32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xac }
-  },
-/* arsh $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xc7 }
-  },
-/* arsh $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xcf }
-  },
-/* arsh32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xc4 }
-  },
-/* arsh32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xcc }
-  },
-/* sdiv $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xe7 }
-  },
-/* sdiv $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xef }
-  },
-/* sdiv32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xe4 }
-  },
-/* sdiv32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xec }
-  },
-/* smod $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xf7 }
-  },
-/* smod $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xff }
-  },
-/* smod32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xf4 }
-  },
-/* smod32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xfc }
-  },
-/* neg $dstle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), 0 } },
-    & ifmt_negle, { 0x87 }
-  },
-/* neg32 $dstle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), 0 } },
-    & ifmt_negle, { 0x84 }
-  },
-/* mov $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xb7 }
-  },
-/* mov $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xbf }
-  },
-/* mov32 $dstle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
-    & ifmt_addile, { 0xb4 }
-  },
-/* mov32 $dstle,$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
-    & ifmt_addrle, { 0xbc }
-  },
-/* add $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x7 }
-  },
-/* add $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xf }
-  },
-/* add32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x4 }
-  },
-/* add32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xc }
-  },
-/* sub $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x17 }
-  },
-/* sub $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x1f }
-  },
-/* sub32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x14 }
-  },
-/* sub32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x1c }
-  },
-/* mul $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x27 }
-  },
-/* mul $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x2f }
-  },
-/* mul32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x24 }
-  },
-/* mul32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x2c }
-  },
-/* div $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x37 }
-  },
-/* div $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x3f }
-  },
-/* div32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x34 }
-  },
-/* div32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x3c }
-  },
-/* or $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x47 }
-  },
-/* or $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x4f }
-  },
-/* or32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x44 }
-  },
-/* or32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x4c }
-  },
-/* and $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x57 }
-  },
-/* and $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x5f }
-  },
-/* and32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x54 }
-  },
-/* and32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x5c }
-  },
-/* lsh $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x67 }
-  },
-/* lsh $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x6f }
-  },
-/* lsh32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x64 }
-  },
-/* lsh32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x6c }
-  },
-/* rsh $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x77 }
-  },
-/* rsh $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x7f }
-  },
-/* rsh32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x74 }
-  },
-/* rsh32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x7c }
-  },
-/* mod $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x97 }
-  },
-/* mod $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x9f }
-  },
-/* mod32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0x94 }
-  },
-/* mod32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0x9c }
-  },
-/* xor $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xa7 }
-  },
-/* xor $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xaf }
-  },
-/* xor32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xa4 }
-  },
-/* xor32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xac }
-  },
-/* arsh $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xc7 }
-  },
-/* arsh $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xcf }
-  },
-/* arsh32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xc4 }
-  },
-/* arsh32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xcc }
-  },
-/* sdiv $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xe7 }
-  },
-/* sdiv $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xef }
-  },
-/* sdiv32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xe4 }
-  },
-/* sdiv32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xec }
-  },
-/* smod $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xf7 }
-  },
-/* smod $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xff }
-  },
-/* smod32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xf4 }
-  },
-/* smod32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xfc }
-  },
-/* neg $dstbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), 0 } },
-    & ifmt_negbe, { 0x87 }
-  },
-/* neg32 $dstbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), 0 } },
-    & ifmt_negbe, { 0x84 }
-  },
-/* mov $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xb7 }
-  },
-/* mov $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xbf }
-  },
-/* mov32 $dstbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
-    & ifmt_addibe, { 0xb4 }
-  },
-/* mov32 $dstbe,$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
-    & ifmt_addrbe, { 0xbc }
-  },
-/* endle $dstle,$endsize */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (ENDSIZE), 0 } },
-    & ifmt_endlele, { 0xd4 }
-  },
-/* endbe $dstle,$endsize */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (ENDSIZE), 0 } },
-    & ifmt_endlele, { 0xdc }
-  },
-/* endle $dstbe,$endsize */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (ENDSIZE), 0 } },
-    & ifmt_endlebe, { 0xd4 }
-  },
-/* endbe $dstbe,$endsize */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (ENDSIZE), 0 } },
-    & ifmt_endlebe, { 0xdc }
-  },
-/* lddw $dstle,$imm64 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM64), 0 } },
-    & ifmt_lddwle, { 0x18 }
-  },
-/* lddw $dstbe,$imm64 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM64), 0 } },
-    & ifmt_lddwbe, { 0x18 }
-  },
-/* ldabsw $imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (IMM32), 0 } },
-    & ifmt_ldabsw, { 0x20 }
-  },
-/* ldabsh $imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (IMM32), 0 } },
-    & ifmt_ldabsw, { 0x28 }
-  },
-/* ldabsb $imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (IMM32), 0 } },
-    & ifmt_ldabsw, { 0x30 }
-  },
-/* ldabsdw $imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (IMM32), 0 } },
-    & ifmt_ldabsw, { 0x38 }
-  },
-/* ldindw $srcle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldindwle, { 0x40 }
-  },
-/* ldindh $srcle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldindwle, { 0x48 }
-  },
-/* ldindb $srcle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldindwle, { 0x50 }
-  },
-/* ldinddw $srcle,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCLE), ',', OP (IMM32), 0 } },
-    & ifmt_ldindwle, { 0x58 }
-  },
-/* ldindw $srcbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldindwbe, { 0x40 }
-  },
-/* ldindh $srcbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldindwbe, { 0x48 }
-  },
-/* ldindb $srcbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldindwbe, { 0x50 }
-  },
-/* ldinddw $srcbe,$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (SRCBE), ',', OP (IMM32), 0 } },
-    & ifmt_ldindwbe, { 0x58 }
-  },
-/* ldxw $dstle,[$srcle+$offset16] */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
-    & ifmt_ldxwle, { 0x61 }
-  },
-/* ldxh $dstle,[$srcle+$offset16] */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
-    & ifmt_ldxwle, { 0x69 }
-  },
-/* ldxb $dstle,[$srcle+$offset16] */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
-    & ifmt_ldxwle, { 0x71 }
-  },
-/* ldxdw $dstle,[$srcle+$offset16] */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', '[', OP (SRCLE), '+', OP (OFFSET16), ']', 0 } },
-    & ifmt_ldxwle, { 0x79 }
-  },
-/* stxw [$dstle+$offset16],$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
-    & ifmt_ldxwle, { 0x63 }
-  },
-/* stxh [$dstle+$offset16],$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
-    & ifmt_ldxwle, { 0x6b }
-  },
-/* stxb [$dstle+$offset16],$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
-    & ifmt_ldxwle, { 0x73 }
-  },
-/* stxdw [$dstle+$offset16],$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
-    & ifmt_ldxwle, { 0x7b }
-  },
-/* ldxw $dstbe,[$srcbe+$offset16] */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
-    & ifmt_ldxwbe, { 0x61 }
-  },
-/* ldxh $dstbe,[$srcbe+$offset16] */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
-    & ifmt_ldxwbe, { 0x69 }
-  },
-/* ldxb $dstbe,[$srcbe+$offset16] */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
-    & ifmt_ldxwbe, { 0x71 }
-  },
-/* ldxdw $dstbe,[$srcbe+$offset16] */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', '[', OP (SRCBE), '+', OP (OFFSET16), ']', 0 } },
-    & ifmt_ldxwbe, { 0x79 }
-  },
-/* stxw [$dstbe+$offset16],$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
-    & ifmt_ldxwbe, { 0x63 }
-  },
-/* stxh [$dstbe+$offset16],$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
-    & ifmt_ldxwbe, { 0x6b }
-  },
-/* stxb [$dstbe+$offset16],$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
-    & ifmt_ldxwbe, { 0x73 }
-  },
-/* stxdw [$dstbe+$offset16],$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
-    & ifmt_ldxwbe, { 0x7b }
-  },
-/* stb [$dstle+$offset16],$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
-    & ifmt_stble, { 0x72 }
-  },
-/* sth [$dstle+$offset16],$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
-    & ifmt_stble, { 0x6a }
-  },
-/* stw [$dstle+$offset16],$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
-    & ifmt_stble, { 0x62 }
-  },
-/* stdw [$dstle+$offset16],$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
-    & ifmt_stble, { 0x7a }
-  },
-/* stb [$dstbe+$offset16],$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
-    & ifmt_stbbe, { 0x72 }
-  },
-/* sth [$dstbe+$offset16],$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
-    & ifmt_stbbe, { 0x6a }
-  },
-/* stw [$dstbe+$offset16],$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
-    & ifmt_stbbe, { 0x62 }
-  },
-/* stdw [$dstbe+$offset16],$imm32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (IMM32), 0 } },
-    & ifmt_stbbe, { 0x7a }
-  },
-/* jeq $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x15 }
-  },
-/* jeq $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x1d }
-  },
-/* jeq32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x16 }
-  },
-/* jeq32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x1e }
-  },
-/* jgt $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x25 }
-  },
-/* jgt $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x2d }
-  },
-/* jgt32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x26 }
-  },
-/* jgt32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x2e }
-  },
-/* jge $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x35 }
-  },
-/* jge $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x3d }
-  },
-/* jge32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x36 }
-  },
-/* jge32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x3e }
-  },
-/* jlt $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0xa5 }
-  },
-/* jlt $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0xad }
-  },
-/* jlt32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0xa6 }
-  },
-/* jlt32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0xae }
-  },
-/* jle $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0xb5 }
-  },
-/* jle $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0xbd }
-  },
-/* jle32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0xb6 }
-  },
-/* jle32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0xbe }
-  },
-/* jset $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x45 }
-  },
-/* jset $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x4d }
-  },
-/* jset32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x46 }
-  },
-/* jset32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x4e }
-  },
-/* jne $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x55 }
-  },
-/* jne $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x5d }
-  },
-/* jne32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x56 }
-  },
-/* jne32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x5e }
-  },
-/* jsgt $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x65 }
-  },
-/* jsgt $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x6d }
-  },
-/* jsgt32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x66 }
-  },
-/* jsgt32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x6e }
-  },
-/* jsge $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x75 }
-  },
-/* jsge $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x7d }
-  },
-/* jsge32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0x76 }
-  },
-/* jsge32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0x7e }
-  },
-/* jslt $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0xc5 }
-  },
-/* jslt $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0xcd }
-  },
-/* jslt32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0xc6 }
-  },
-/* jslt32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0xce }
-  },
-/* jsle $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0xd5 }
-  },
-/* jsle $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0xdd }
-  },
-/* jsle32 $dstle,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqile, { 0xd6 }
-  },
-/* jsle32 $dstle,$srcle,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrle, { 0xde }
-  },
-/* jeq $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x15 }
-  },
-/* jeq $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x1d }
-  },
-/* jeq32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x16 }
-  },
-/* jeq32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x1e }
-  },
-/* jgt $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x25 }
-  },
-/* jgt $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x2d }
-  },
-/* jgt32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x26 }
-  },
-/* jgt32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x2e }
-  },
-/* jge $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x35 }
-  },
-/* jge $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x3d }
-  },
-/* jge32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x36 }
-  },
-/* jge32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x3e }
-  },
-/* jlt $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0xa5 }
-  },
-/* jlt $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0xad }
-  },
-/* jlt32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0xa6 }
-  },
-/* jlt32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0xae }
-  },
-/* jle $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0xb5 }
-  },
-/* jle $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0xbd }
-  },
-/* jle32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0xb6 }
-  },
-/* jle32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0xbe }
-  },
-/* jset $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x45 }
-  },
-/* jset $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x4d }
-  },
-/* jset32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x46 }
-  },
-/* jset32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x4e }
-  },
-/* jne $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x55 }
-  },
-/* jne $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x5d }
-  },
-/* jne32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x56 }
-  },
-/* jne32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x5e }
-  },
-/* jsgt $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x65 }
-  },
-/* jsgt $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x6d }
-  },
-/* jsgt32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x66 }
-  },
-/* jsgt32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x6e }
-  },
-/* jsge $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x75 }
-  },
-/* jsge $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x7d }
-  },
-/* jsge32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0x76 }
-  },
-/* jsge32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0x7e }
-  },
-/* jslt $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0xc5 }
-  },
-/* jslt $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0xcd }
-  },
-/* jslt32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0xc6 }
-  },
-/* jslt32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0xce }
-  },
-/* jsle $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0xd5 }
-  },
-/* jsle $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0xdd }
-  },
-/* jsle32 $dstbe,$imm32,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), ',', OP (DISP16), 0 } },
-    & ifmt_jeqibe, { 0xd6 }
-  },
-/* jsle32 $dstbe,$srcbe,$disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
-    & ifmt_jeqrbe, { 0xde }
-  },
-/* call $disp32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DISP32), 0 } },
-    & ifmt_callle, { 0x85 }
-  },
-/* call $disp32 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DISP32), 0 } },
-    & ifmt_callbe, { 0x85 }
-  },
-/* call $dstle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTLE), 0 } },
-    & ifmt_negle, { 0x8d }
-  },
-/* call $dstbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DSTBE), 0 } },
-    & ifmt_negbe, { 0x8d }
-  },
-/* ja $disp16 */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', OP (DISP16), 0 } },
-    & ifmt_ja, { 0x5 }
-  },
-/* exit */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, 0 } },
-    & ifmt_exit, { 0x95 }
-  },
-/* xadddw [$dstle+$offset16],$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
-    & ifmt_ldxwle, { 0xdb }
-  },
-/* xaddw [$dstle+$offset16],$srcle */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTLE), '+', OP (OFFSET16), ']', ',', OP (SRCLE), 0 } },
-    & ifmt_ldxwle, { 0xc3 }
-  },
-/* xadddw [$dstbe+$offset16],$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
-    & ifmt_ldxwbe, { 0xdb }
-  },
-/* xaddw [$dstbe+$offset16],$srcbe */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
-    & ifmt_ldxwbe, { 0xc3 }
-  },
-/* brkpt */
-  {
-    { 0, 0, 0, 0 },
-    { { MNEM, 0 } },
-    & ifmt_exit, { 0x8c }
-  },
+  /* id, normal, pseudoc, version, mask, opcodes */
+
+  /* ALU instructions.  */
+  {BPF_INSN_ADDR, "add%W%dr , %sr", "%dr += %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ADD|BPF_SRC_X},
+  {BPF_INSN_ADDI, "add%W%dr , %i32", "%dr += %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ADD|BPF_SRC_K},
+  {BPF_INSN_SUBR, "sub%W%dr , %sr", "%dr -= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_SUB|BPF_SRC_X},
+  {BPF_INSN_SUBI, "sub%W%dr , %i32", "%dr -= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_SUB|BPF_SRC_K},
+  {BPF_INSN_MULR, "mul%W%dr , %sr", "%dr *= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MUL|BPF_SRC_X},
+  {BPF_INSN_MULI, "mul%W%dr , %i32", "%dr *= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MUL|BPF_SRC_K},
+  {BPF_INSN_SDIVR, "sdiv%W%dr, %sr", "%dr s/= %sr",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
+  {BPF_INSN_SDIVI, "sdiv%W%dr , %i32","%dr s/= %i32",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
+  {BPF_INSN_SMODR, "smod%W%dr , %sr", "%dr s%%= %sr",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
+  {BPF_INSN_SMODI, "smod%W%dr , %i32", "%dr s%%= %i32",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
+  {BPF_INSN_DIVR, "div%W%dr , %sr", "%dr /= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_X},
+  {BPF_INSN_DIVI, "div%W%dr , %i32", "%dr /= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_DIV|BPF_SRC_K},
+  {BPF_INSN_MODR, "mod%W%dr , %sr", "%dr %%= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_X},
+  {BPF_INSN_MODI, "mod%W%dr , %i32", "%dr %%= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOD|BPF_SRC_K},
+  {BPF_INSN_ORR, "or%W%dr , %sr", "%dr |= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_OR|BPF_SRC_X},
+  {BPF_INSN_ORI, "or%W%dr , %i32", "%dr |= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_OR|BPF_SRC_K},
+  {BPF_INSN_ANDR, "and%W%dr , %sr", "%dr &= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_AND|BPF_SRC_X},
+  {BPF_INSN_ANDI, "and%W%dr , %i32", "%dr &= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_AND|BPF_SRC_K},
+  {BPF_INSN_XORR, "xor%W%dr , %sr", "%dr ^= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_X},
+  {BPF_INSN_XORI, "xor%W%dr , %i32", "%dr ^= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_XOR|BPF_SRC_K},
+  {BPF_INSN_NEGR, "neg%W%dr, %sr", "%dr = - %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_X},
+  {BPF_INSN_NEGI, "neg%W%dr , %i32", "%dr = -%W%i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_NEG|BPF_SRC_K},
+  {BPF_INSN_LSHR, "lsh%W%dr , %sr", "%dr <<= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_X},
+  {BPF_INSN_LSHI, "lsh%W%dr , %i32", "%dr <<= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_LSH|BPF_SRC_K},
+  {BPF_INSN_RSHR, "rsh%W%dr , %sr", "%dr >>= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_RSH|BPF_SRC_X},
+  {BPF_INSN_RSHI, "rsh%W%dr , %i32", "%dr >>= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_RSH|BPF_SRC_K},
+  {BPF_INSN_ARSHR, "arsh%W%dr , %sr", "%dr%ws>>= %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_X},
+  {BPF_INSN_ARSHI, "arsh%W%dr , %i32", "%dr%ws>>= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_ARSH|BPF_SRC_K},
+  {BPF_INSN_MOVR, "mov%W%dr , %sr", "%dr = %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_X},
+  {BPF_INSN_MOVI, "mov%W%dr , %i32", "%dr = %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU64|BPF_CODE_MOV|BPF_SRC_K},
+
+  /* ALU32 instructions.  */
+  {BPF_INSN_ADD32R, "add32%W%dr , %sr", "%dw += %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ADD|BPF_SRC_X},
+  {BPF_INSN_ADD32I, "add32%W%dr , %i32", "%dw += %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ADD|BPF_SRC_K},
+  {BPF_INSN_SUB32R, "sub32%W%dr , %sr", "%dw -= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_SUB|BPF_SRC_X},
+  {BPF_INSN_SUB32I, "sub32%W%dr , %i32", "%dw -= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_SUB|BPF_SRC_K},
+  {BPF_INSN_MUL32R, "mul32%W%dr , %sr", "%dw *= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MUL|BPF_SRC_X},
+  {BPF_INSN_MUL32I, "mul32%W%dr , %i32", "%dw *= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MUL|BPF_SRC_K},
+  {BPF_INSN_SDIV32R, "sdiv32%W%dr , %sr", "%dw s/= %sw",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
+  {BPF_INSN_SDIV32I, "sdiv32%W%dr , %i32", "%dw s/= %i32",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
+  {BPF_INSN_SMOD32R, "smod32%W%dr , %sr", "%dw s%%= %sw",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_X|BPF_OFFSET16_SDIVMOD},
+  {BPF_INSN_SMOD32I, "smod32%W%dr , %i32", "%dw s%%= %i32",
+   BPF_V4, BPF_CODE|BPF_OFFSET16, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_K|BPF_OFFSET16_SDIVMOD},
+  {BPF_INSN_DIV32R, "div32%W%dr , %sr", "%dw /= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_X},
+  {BPF_INSN_DIV32I, "div32%W%dr , %i32", "%dw /= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_DIV|BPF_SRC_K},
+  {BPF_INSN_MOD32R, "mod32%W%dr , %sr", "%dw %%= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_X},
+  {BPF_INSN_MOD32I, "mod32%W%dr , %i32", "%dw %%= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOD|BPF_SRC_K},
+  {BPF_INSN_OR32R, "or32%W%dr , %sr",  "%dw |= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_OR|BPF_SRC_X},
+  {BPF_INSN_OR32I, "or32%W%dr , %i32", "%dw |= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_OR|BPF_SRC_K},
+  {BPF_INSN_AND32R, "and32%W%dr , %sr", "%dw &= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_AND|BPF_SRC_X},
+  {BPF_INSN_AND32I, "and32%W%dr , %i32", "%dw &= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_AND|BPF_SRC_K},
+  {BPF_INSN_XOR32R, "xor32%W%dr , %sr", "%dw ^= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_X},
+  {BPF_INSN_XOR32I, "xor32%W%dr , %i32", "%dw ^= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_XOR|BPF_SRC_K},
+  {BPF_INSN_NEG32R, "neg32%W%dr , %sr", "%dw = - %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_X},
+  {BPF_INSN_NEG32I, "neg32%W%dr , %i32", "%dw = -%W%i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_NEG|BPF_SRC_K},
+  {BPF_INSN_LSH32R, "lsh32%W%dr , %sr", "%dw <<= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_X},
+  {BPF_INSN_LSH32I, "lsh32%W%dr , %i32", "%dw <<= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_LSH|BPF_SRC_K},
+  {BPF_INSN_RSH32R, "rsh32%W%dr , %sr", "%dw >>= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_RSH|BPF_SRC_X},
+  {BPF_INSN_RSH32I, "rsh32%W%dr , %i32", "%dw >>= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_RSH|BPF_SRC_K},
+  {BPF_INSN_ARSH32R, "arsh32%W%dr , %sr", "%dw%ws>>= %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_X},
+  {BPF_INSN_ARSH32I, "arsh32%W%dr , %i32", "%dw%Ws>>= %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_ARSH|BPF_SRC_K},
+  {BPF_INSN_MOV32R, "mov32%W%dr , %sr", "%dw = %sw",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_X},
+  {BPF_INSN_MOV32I, "mov32%W%dr , %i32", "%dw = %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ALU|BPF_CODE_MOV|BPF_SRC_K},
+
+  /* Endianness conversion instructions.  */
+  {BPF_INSN_ENDLE16, "endle%W%dr , 16", "%dr = le16%w%dr",
+   BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END16},
+  {BPF_INSN_ENDLE32, "endle%W%dr , 32", "%dr = le32%w%dr",
+   BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END32},
+  {BPF_INSN_ENDLE64, "endle%W%dr , 64", "%dr = le64%w%dr",
+   BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_K|BPF_IMM32_END64},
+  {BPF_INSN_ENDBE16, "endbe%W%dr , 16", "%dr = be16%w%dr",
+   BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END16},
+  {BPF_INSN_ENDBE32, "endbe%W%dr , 32", "%dr = be32%w%dr",
+   BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END32},
+  {BPF_INSN_ENDBE64, "endbe%W%dr , 64", "%dr = be64%w%dr",
+   BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_ALU|BPF_CODE_END|BPF_SRC_X|BPF_IMM32_END64},
+
+  /* 64-bit load instruction.  */
+  {BPF_INSN_LDDW, "lddw%W%dr , %i64", "%dr = %i64%wll",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IMM},
+
+  /* Indirect load instructions, designed to be used in socket
+     filters.  */
+  {BPF_INSN_LDINDB, "ldindb%W%sr , %i32", "r0 = * ( u8 * ) skb [ %sr %I32 ]",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_B|BPF_MODE_IND},
+  {BPF_INSN_LDINDH, "ldindh%W%sr , %i32", "r0 = * ( u16 * ) skb [ %sr %I32 ]",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_H|BPF_MODE_IND},
+  {BPF_INSN_LDINDW, "ldindw%W%sr , %i32", "r0 = * ( u32 * ) skb [ %sr %I32 ]",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_IND},
+  {BPF_INSN_LDINDDW, "ldinddw%W%sr , %i32", "r0 = * ( u64 * ) skb [ %sr %I32 ]",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_IND},
+
+  /* Absolute load instructions, designed to be used in socket filters.  */
+  {BPF_INSN_LDABSB, "ldabsb%W%i32", "r0 = * ( u8 * ) skb [ %i32 ]",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_B|BPF_MODE_ABS},
+  {BPF_INSN_LDABSH, "ldabsh%W%i32", "r0 = * ( u16 * ) skb [ %i32 ]",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_H|BPF_MODE_ABS},
+  {BPF_INSN_LDABSW, "ldabsw%W%i32", "r0 = * ( u32 * ) skb [ %i32 ]",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_W|BPF_MODE_ABS},
+  {BPF_INSN_LDABSDW, "ldabsdw%W%i32", "r0 = * ( u64 * ) skb [ %i32 ]",
+   BPF_V1, BPF_CODE, BPF_CLASS_LD|BPF_SIZE_DW|BPF_MODE_ABS},
+
+  /* Generic load instructions (to register.)  */
+  {BPF_INSN_LDXB, "ldxb%W%dr , [ %sr %o16 ]", "%dr = * ( u8 * ) ( %sr %o16 )",
+   BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_B|BPF_MODE_MEM},
+  {BPF_INSN_LDXH, "ldxh%W%dr , [ %sr %o16 ]", "%dr = * ( u16 * ) ( %sr %o16 )",
+   BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_H|BPF_MODE_MEM},
+  {BPF_INSN_LDXW, "ldxw%W%dr , [ %sr %o16 ]", "%dr = * ( u32 * ) ( %sr %o16 )",
+   BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_W|BPF_MODE_MEM},
+  {BPF_INSN_LDXDW, "ldxdw%W%dr , [ %sr %o16 ]","%dr = * ( u64 * ) ( %sr %o16 )",
+   BPF_V1, BPF_CODE, BPF_CLASS_LDX|BPF_SIZE_DW|BPF_MODE_MEM},
+
+  /* Generic store instructions (from register.)  */
+  {BPF_INSN_STXBR, "stxb%W[ %dr %o16 ] , %sr", "* ( u8 * ) ( %dr %o16 ) = %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_B|BPF_MODE_MEM},
+  {BPF_INSN_STXHR, "stxh%W[ %dr %o16 ] , %sr", "* ( u16 * ) ( %dr %o16 ) = %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_H|BPF_MODE_MEM},
+  {BPF_INSN_STXWR, "stxw%W[ %dr %o16 ], %sr", "* ( u32 * ) ( %dr %o16 ) = %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_MEM},
+  {BPF_INSN_STXDWR, "stxdw%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) = %sr",
+   BPF_V1, BPF_CODE, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_MEM},
+
+  /* Generic store instructions (from 32-bit immediate.)  */
+  {BPF_INSN_STXBI, "stb%W[ %dr %o16 ] , %i32", "* ( u8 * ) ( %dr %o16 ) = %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_B|BPF_MODE_MEM},
+  {BPF_INSN_STXHI, "sth%W[ %dr %o16 ] , %i32", "* ( u16 * ) ( %dr %o16 ) = %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_H|BPF_MODE_MEM},
+  {BPF_INSN_STXWI, "stw%W[ %dr %o16 ] , %i32", "* ( u32 * ) ( %dr %o16 ) = %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_W|BPF_MODE_MEM},
+  {BPF_INSN_STXDWI, "stdw%W[ %dr %o16 ] , %i32", "* ( u64 * ) ( %dr %o16 ) = %i32",
+   BPF_V1, BPF_CODE, BPF_CLASS_ST|BPF_SIZE_DW|BPF_MODE_MEM},
+
+  /* Compare-and-jump instructions (reg OP reg).  */
+  {BPF_INSN_JAR, "ja%W%d16", "goto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JA|BPF_SRC_K},
+  {BPF_INSN_JEQR, "jeq%W%dr , %sr , %d16", "if%w%dr == %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JEQ|BPF_SRC_X},
+  {BPF_INSN_JGTR, "jgt%W%dr , %sr , %d16", "if%w%dr > %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGT|BPF_SRC_X},
+  {BPF_INSN_JSGTR, "jsgt%W%dr, %sr , %d16", "if%w%dr s> %sr%wgoto%w%d16",
+      BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGT|BPF_SRC_X},
+  {BPF_INSN_JGER, "jge%W%dr , %sr , %d16", "if%w%dr >= %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGE|BPF_SRC_X},
+  {BPF_INSN_JSGER, "jsge%W%dr , %sr , %d16", "if%w%dr s>= %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGE|BPF_SRC_X},
+  {BPF_INSN_JLTR, "jlt%W%dr , %sr , %d16", "if%w%dr < %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLT|BPF_SRC_X},
+  {BPF_INSN_JSLTR, "jslt%W%dr , %sr , %d16", "if%w%dr s< %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLT|BPF_SRC_X},
+  {BPF_INSN_JLER, "jle%W%dr , %sr , %d16", "if%w%dr <= %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLE|BPF_SRC_X},
+  {BPF_INSN_JSLER, "jsle%W%dr , %sr , %d16", "if%w%dr s<= %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLE|BPF_SRC_X},
+  {BPF_INSN_JSETR, "jset%W%dr , %sr , %d16", "if%w%dr & %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_X},
+  {BPF_INSN_JNER, "jne%W%dr , %sr , %d16", "if%w%dr != %sr%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_X},
+  {BPF_INSN_CALLR, "call%W%dr", "callx%w%dr",
+   BPF_XBPF, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_X},
+  {BPF_INSN_CALL, "call%W%d32", "call%w%d32",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_CALL|BPF_SRC_K},
+  {BPF_INSN_EXIT, "exit", "exit",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_EXIT|BPF_SRC_K},
+
+  /* Compare-and-jump instructions (reg OP imm).  */
+  {BPF_INSN_JEQI, "jeq%W%dr , %i32 , %d16", "if%w%dr == %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JEQ|BPF_SRC_K},
+  {BPF_INSN_JGTI, "jgt%W%dr , %i32 , %d16", "if%w%dr > %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGT|BPF_SRC_K},
+  {BPF_INSN_JSGTI, "jsgt%W%dr, %i32 , %d16", "if%w%dr s> %i32%wgoto%w%d16",
+      BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGT|BPF_SRC_K},
+  {BPF_INSN_JGEI, "jge%W%dr , %i32 , %d16", "if%w%dr >= %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JGE|BPF_SRC_K},
+  {BPF_INSN_JSGEI, "jsge%W%dr , %i32 , %d16", "if%w%dr s>= %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSGE|BPF_SRC_K},
+  {BPF_INSN_JLTI, "jlt%W%dr , %i32 , %d16", "if%w%dr < %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLT|BPF_SRC_K},
+  {BPF_INSN_JSLTI, "jslt%W%dr , %i32, %d16", "if%w%dr s< %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLT|BPF_SRC_K},
+  {BPF_INSN_JLEI, "jle%W%dr , %i32 , %d16", "if%w%dr <= %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JLE|BPF_SRC_K},
+  {BPF_INSN_JSLEI, "jsle%W%dr , %i32 , %d16", "if%w%dr s<= %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSLE|BPF_SRC_K},
+  {BPF_INSN_JSETI, "jset%W%dr , %i32 , %d16", "if%w%dr & %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JSET|BPF_SRC_K},
+  {BPF_INSN_JNEI, "jne%W%dr , %i32 , %d16", "if%w%dr != %i32%wgoto%w%d16",
+   BPF_V1, BPF_CODE, BPF_CLASS_JMP|BPF_CODE_JNE|BPF_SRC_K},
+
+  /* 32-bit compare-and-jump instructions (reg OP reg).  */
+  {BPF_INSN_JEQ32R, "jeq32%W%dr , %sr , %d16", "if%w%dw == %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JEQ|BPF_SRC_X},
+  {BPF_INSN_JGT32R, "jgt32%W%dr , %sr , %d16", "if%w%dw > %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGT|BPF_SRC_X},
+  {BPF_INSN_JSGT32R, "jsgt32%W%dr, %sr , %d16", "if%w%dw s> %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGT|BPF_SRC_X},
+  {BPF_INSN_JGE32R, "jge32%W%dr , %sr , %d16", "if%w%dw >= %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGE|BPF_SRC_X},
+  {BPF_INSN_JSGE32R, "jsge32%W%dr , %sr , %d16", "if%w%dw s>= %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGE|BPF_SRC_X},
+  {BPF_INSN_JLT32R, "jlt32%W%dr , %sr , %d16", "if%w%dw < %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLT|BPF_SRC_X},
+  {BPF_INSN_JSLT32R, "jslt32%W%dr , %sr , %d16", "if%w%dw s< %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLT|BPF_SRC_X},
+  {BPF_INSN_JLE32R, "jle32%W%dr , %sr , %d16", "if%w%dw <= %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLE|BPF_SRC_X},
+  {BPF_INSN_JSLE32R, "jsle32%W%dr , %sr , %d16", "if%w%dw s<= %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLE|BPF_SRC_X},
+  {BPF_INSN_JSET32R, "jset32%W%dr , %sr , %d16", "if%w%dw & %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSET|BPF_SRC_X},
+  {BPF_INSN_JNE32R, "jne32%W%dr , %sr , %d16", "if%w%dw != %sw%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_X},
+
+  /* 32-bit compare-and-jump instructions (reg OP imm).  */
+  {BPF_INSN_JEQ32I, "jeq32%W%dr , %i32 , %d16", "if%w%dw == %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JEQ|BPF_SRC_K},
+  {BPF_INSN_JGT32I, "jgt32%W%dr , %i32 , %d16", "if%w%dw > %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGT|BPF_SRC_K},
+  {BPF_INSN_JSGT32I, "jsgt32%W%dr, %i32 , %d16", "if%w%dw s> %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGT|BPF_SRC_K},
+  {BPF_INSN_JGE32I, "jge32%W%dr , %i32 , %d16", "if%w%dw >= %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JGE|BPF_SRC_K},
+  {BPF_INSN_JSGE32I, "jsge32%W%dr , %i32 , %d16", "if%w%dw s>= %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSGE|BPF_SRC_K},
+  {BPF_INSN_JLT32I, "jlt32%W%dr , %i32 , %d16", "if%w%dw < %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLT|BPF_SRC_K},
+  {BPF_INSN_JSLT32I, "jslt32%W%dr , %i32, %d16", "if%w%dw s< %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLT|BPF_SRC_K},
+  {BPF_INSN_JLE32I, "jle32%W%dr , %i32 , %d16", "if%w%dw <= %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JLE|BPF_SRC_K},
+  {BPF_INSN_JSLE32I, "jsle32%W%dr , %i32 , %d16", "if%w%dw s<= %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSLE|BPF_SRC_K},
+  {BPF_INSN_JSET32I, "jset32%W%dr , %i32 , %d16", "if%w%dw & %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JSET|BPF_SRC_K},
+  {BPF_INSN_JNE32I, "jne32%W%dr , %i32 , %d16", "if%w%dw != %i32%wgoto%w%d16",
+   BPF_V3, BPF_CODE, BPF_CLASS_JMP32|BPF_CODE_JNE|BPF_SRC_K},
+
+  /* Atomic instructions.  */
+  {BPF_INSN_AADD, "aadd%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) += %sr",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
+  {BPF_INSN_AOR, "aor%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) |= %sr",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
+  {BPF_INSN_AAND, "aand%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) &= %sr",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
+  {BPF_INSN_AXOR, "axor%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) ^= %sr",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
+
+  /* Atomic instructions with fetching.  */
+  {BPF_INSN_AFADD, "afadd%W[ %dr %o16 ] , %sr", "???",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},
+  {BPF_INSN_AFOR, "afor%W[ %dr %o16 ] , %sr", "???",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},
+  {BPF_INSN_AFAND, "afand%W[ %dr %o16 ] , %sr", "???",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},
+  {BPF_INSN_AFXOR, "afxor%W[ %dr %o16 ] , %sr", "???",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
+
+  /* Atomic instructions (32-bit.) */
+  {BPF_INSN_AADD32, "aadd32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) += %sr",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
+  {BPF_INSN_AOR32, "aor32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) |= %sr",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AOR},
+  {BPF_INSN_AAND32, "aand32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) &= %sr",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AAND},
+  {BPF_INSN_AXOR32, "axor32%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) ^= %sr",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AXOR},
+
+  /* Atomic instructions with fetching (32-bit.) */
+  {BPF_INSN_AFADD32, "afadd32 %W[ %dr %o16 ] , %sr", "???",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFADD},
+  {BPF_INSN_AFOR32, "afor32%W[ %dr %o16 ] , %sr", "???",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFOR},
+  {BPF_INSN_AFAND32, "afand32%W[ %dr %o16 ] , %sr", "???",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFAND},
+  {BPF_INSN_AFXOR32, "afxor32%W[ %dr %o16 ] , %sr", "???",
+   BPF_V3, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AFXOR},
+
+  /* Old versions of aadd and aadd32.  */
+  {BPF_INSN_AADD, "xadddw%W[ %dr %o16 ] , %sr", "* ( u64 * ) ( %dr %o16 ) += %sr",
+   BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_DW|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
+  {BPF_INSN_AADD32, "xaddw%W[ %dr %o16 ] , %sr", "* ( u32 * ) ( %dr %o16 ) += %sr",
+   BPF_V1, BPF_CODE|BPF_IMM32, BPF_CLASS_STX|BPF_SIZE_W|BPF_MODE_ATOMIC|BPF_IMM32_AADD},
+
+  /* the brkpt instruction is used by the BPF simulator and it doesn't
+     really belong to the BPF instruction set.  */
+  {BPF_INSN_BRKPT, "brkpt", "brkpt",
+   BPF_XBPF, BPF_CODE, BPF_CLASS_ALU|BPF_SRC_X|BPF_CODE_NEG},
+
+  /* Sentinel.  */
+  {BPF_NOINSN, NULL, NULL, 0, 0UL, 0UL},
 };
 
-#undef A
-#undef OPERAND
-#undef MNEM
-#undef OP
-
-/* Formats for ALIAS macro-insns.  */
-
-#define F(f) & bpf_cgen_ifld_table[BPF_##f]
-#undef F
-
-/* Each non-simple macro entry points to an array of expansion possibilities.  */
-
-#define A(a) (1 << CGEN_INSN_##a)
-#define OPERAND(op) BPF_OPERAND_##op
-#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-
-/* The macro instruction table.  */
-
-static const CGEN_IBASE bpf_cgen_macro_insn_table[] =
+static bpf_insn_word
+bpf_handle_endianness (bpf_insn_word word, enum bpf_endian endian)
 {
-};
+  if (endian == BPF_ENDIAN_LITTLE)
+    {
+      /* Endianness groups: 8 | 4 | 4 | 16 | 32  */
+
+      bpf_insn_word code = (word >> 56) & 0xff;
+      bpf_insn_word dst = (word >> 48) & 0xf;
+      bpf_insn_word src = (word >> 52) & 0xf;
+      bpf_insn_word offset16 = (word >> 32) & 0xffff;
+      bpf_insn_word imm32 = word & 0xffffffff;
+
+      return ((code << 56)
+              | dst << 52
+              | src << 48
+              | (offset16 & 0xff) << 40
+              | ((offset16 >> 8) & 0xff) << 32
+              | (imm32 & 0xff) << 24
+              | ((imm32 >> 8) & 0xff) << 16
+              | ((imm32 >> 16) & 0xff) << 8
+              | ((imm32 >> 24) & 0xff));
+    }
 
-/* The macro instruction opcode table.  */
+  return word;
+}
 
-static const CGEN_OPCODE bpf_cgen_macro_insn_opcode_table[] =
+const struct bpf_opcode *
+bpf_match_insn (bpf_insn_word word,
+                enum bpf_endian endian,
+                int version)
 {
-};
-
-#undef A
-#undef OPERAND
-#undef MNEM
-#undef OP
+  unsigned int i = 0;
 
-#ifndef CGEN_ASM_HASH_P
-#define CGEN_ASM_HASH_P(insn) 1
-#endif
-
-#ifndef CGEN_DIS_HASH_P
-#define CGEN_DIS_HASH_P(insn) 1
-#endif
+  while (bpf_opcodes[i].normal != NULL)
+    {
+      bpf_insn_word cword
+        = bpf_handle_endianness (word, endian);
+
+      /* Attempt match using mask and opcodes.  */
+      if (bpf_opcodes[i].version <= version
+          && (cword & bpf_opcodes[i].mask) == bpf_opcodes[i].opcode)
+        return &bpf_opcodes[i];
+      i++;
+    }
 
-/* Return non-zero if INSN is to be added to the hash table.
-   Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
+  /* No maching instruction found.  */
+  return NULL;
+}
 
-static int
-asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED)
+uint8_t
+bpf_extract_src (bpf_insn_word word, enum bpf_endian endian)
 {
-  return CGEN_ASM_HASH_P (insn);
+  word = bpf_handle_endianness (word, endian);
+  return (uint8_t) ((word >> 48) & 0xf);
 }
 
-static int
-dis_hash_insn_p (const CGEN_INSN *insn)
+uint8_t
+bpf_extract_dst (bpf_insn_word word, enum bpf_endian endian)
 {
-  /* If building the hash table and the NO-DIS attribute is present,
-     ignore.  */
-  if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
-    return 0;
-  return CGEN_DIS_HASH_P (insn);
+  word = bpf_handle_endianness (word, endian);
+  return (uint8_t) ((word >> 52) & 0xf);
 }
 
-#ifndef CGEN_ASM_HASH
-#define CGEN_ASM_HASH_SIZE 127
-#ifdef CGEN_MNEMONIC_OPERANDS
-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
-#else
-#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
-#endif
-#endif
-
-/* It doesn't make much sense to provide a default here,
-   but while this is under development we do.
-   BUFFER is a pointer to the bytes of the insn, target order.
-   VALUE is the first base_insn_bitsize bits as an int in host order.  */
-
-#ifndef CGEN_DIS_HASH
-#define CGEN_DIS_HASH_SIZE 256
-#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
-#endif
-
-/* The result is the hash value of the insn.
-   Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
-
-static unsigned int
-asm_hash_insn (const char *mnem)
+int16_t
+bpf_extract_offset16 (bpf_insn_word word, enum bpf_endian endian)
 {
-  return CGEN_ASM_HASH (mnem);
+  word = bpf_handle_endianness (word, endian);
+  return (int16_t) ((word >> 32) & 0xffff);
 }
 
-/* BUF is a pointer to the bytes of the insn, target order.
-   VALUE is the first base_insn_bitsize bits as an int in host order.  */
-
-static unsigned int
-dis_hash_insn (const char *buf ATTRIBUTE_UNUSED,
-		     CGEN_INSN_INT value ATTRIBUTE_UNUSED)
+int32_t
+bpf_extract_imm32 (bpf_insn_word word, enum bpf_endian endian)
 {
-  return CGEN_DIS_HASH (buf, value);
+  word = bpf_handle_endianness (word, endian);
+  return (int32_t) (word & 0xffffffff);
 }
 
-/* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
-
-static void
-set_fields_bitsize (CGEN_FIELDS *fields, int size)
+int64_t
+bpf_extract_imm64 (bpf_insn_word word1, bpf_insn_word word2,
+                   enum bpf_endian endian)
 {
-  CGEN_FIELDS_BITSIZE (fields) = size;
+  word1 = bpf_handle_endianness (word1, endian);
+  word2 = bpf_handle_endianness (word2, endian);
+  return (int64_t) (((word2 & 0xffffffff) << 32) | (word1 & 0xffffffff));
 }
 
-/* Function to call before using the operand instance table.
-   This plugs the opcode entries and macro instructions into the cpu table.  */
-
-void
-bpf_cgen_init_opcode_table (CGEN_CPU_DESC cd)
+const struct bpf_opcode *
+bpf_get_opcode (unsigned int index)
 {
-  int i;
-  int num_macros = (sizeof (bpf_cgen_macro_insn_table) /
-		    sizeof (bpf_cgen_macro_insn_table[0]));
-  const CGEN_IBASE *ib = & bpf_cgen_macro_insn_table[0];
-  const CGEN_OPCODE *oc = & bpf_cgen_macro_insn_opcode_table[0];
-  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
-
-  /* This test has been added to avoid a warning generated
-     if memset is called with a third argument of value zero.  */
-  if (num_macros >= 1)
-    memset (insns, 0, num_macros * sizeof (CGEN_INSN));
-  for (i = 0; i < num_macros; ++i)
-    {
-      insns[i].base = &ib[i];
-      insns[i].opcode = &oc[i];
-      bpf_cgen_build_insn_regex (& insns[i]);
-    }
-  cd->macro_insn_table.init_entries = insns;
-  cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
-  cd->macro_insn_table.num_init_entries = num_macros;
-
-  oc = & bpf_cgen_insn_opcode_table[0];
-  insns = (CGEN_INSN *) cd->insn_table.init_entries;
-  for (i = 0; i < MAX_INSNS; ++i)
-    {
-      insns[i].opcode = &oc[i];
-      bpf_cgen_build_insn_regex (& insns[i]);
-    }
-
-  cd->sizeof_fields = sizeof (CGEN_FIELDS);
-  cd->set_fields_bitsize = set_fields_bitsize;
-
-  cd->asm_hash_p = asm_hash_insn_p;
-  cd->asm_hash = asm_hash_insn;
-  cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+  unsigned int i = 0;
 
-  cd->dis_hash_p = dis_hash_insn_p;
-  cd->dis_hash = dis_hash_insn;
-  cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+  while (bpf_opcodes[i].normal != NULL && i < index)
+    ++i;
+  return (bpf_opcodes[i].normal == NULL
+          ? NULL
+          : &bpf_opcodes[i]);
 }
diff --git a/opcodes/configure b/opcodes/configure
index 84f8c2057fd..a9648baccb9 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12597,7 +12597,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_xtensa_arch)	ta="$ta xtensa-dis.lo" ;;
 	bfd_z80_arch)		ta="$ta z80-dis.lo" ;;
 	bfd_z8k_arch)		ta="$ta z8k-dis.lo" ;;
-	bfd_bpf_arch)		ta="$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo" using_cgen=yes ;;
+	bfd_bpf_arch)		ta="$ta bpf-dis.lo bpf-opc.lo" ;;
 	bfd_loongarch_arch)	ta="$ta loongarch-dis.lo loongarch-opc.lo loongarch-coder.lo" ;;
 
 	"")			;;
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index 1beb72e87e0..7f508089c6f 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -345,7 +345,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_xtensa_arch)	ta="$ta xtensa-dis.lo" ;;
 	bfd_z80_arch)		ta="$ta z80-dis.lo" ;;
 	bfd_z8k_arch)		ta="$ta z8k-dis.lo" ;;
-	bfd_bpf_arch)		ta="$ta bpf-asm.lo bpf-desc.lo bpf-dis.lo bpf-ibld.lo bpf-opc.lo" using_cgen=yes ;;
+	bfd_bpf_arch)		ta="$ta bpf-dis.lo bpf-opc.lo" ;;
 	bfd_loongarch_arch)	ta="$ta loongarch-dis.lo loongarch-opc.lo loongarch-coder.lo" ;;
 
 	"")			;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 7a4a641c2b9..a5cb396badb 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -108,23 +108,6 @@
 #include "m32c-desc.h"
 #endif
 
-#ifdef ARCH_bpf
-/* XXX this should be including bpf-desc.h instead of this hackery,
-   but at the moment it is not possible to include several CGEN
-   generated *-desc.h files simultaneously.  To be fixed in
-   CGEN...  */
-
-# ifdef ARCH_m32c
-enum epbf_isa_attr
-{
-  ISA_EBPFLE, ISA_EBPFBE, ISA_XBPFLE, ISA_XBPFBE, ISA_EBPFMAX
-};
-# else
-#  include "bpf-desc.h"
-#  define ISA_EBPFMAX ISA_MAX
-# endif
-#endif /* ARCH_bpf */
-
 disassembler_ftype
 disassembler (enum bfd_architecture a,
 	      bool big ATTRIBUTE_UNUSED,
@@ -594,7 +577,9 @@ disassembler_usage (FILE *stream ATTRIBUTE_UNUSED)
 #ifdef ARCH_loongarch
   print_loongarch_disassembler_options (stream);
 #endif
-
+#ifdef ARCH_bpf
+  print_bpf_disassembler_options (stream);
+#endif
   return;
 }
 
@@ -695,6 +680,9 @@ disassemble_init_for_target (struct disassemble_info * info)
 #endif
 #ifdef ARCH_bpf
     case bfd_arch_bpf:
+      /* XXX option for dialect  */
+      info->created_styled_output = true;
+#if 0
       info->endian_code = BFD_ENDIAN_LITTLE;
       if (!info->private_data)
 	{
@@ -712,6 +700,7 @@ disassemble_init_for_target (struct disassemble_info * info)
 		cgen_bitset_set (info->private_data, ISA_XBPFLE);
 	    }
 	}
+#endif
       break;
 #endif
 #ifdef ARCH_pru
@@ -768,13 +757,10 @@ disassemble_free_target (struct disassemble_info *info)
     default:
       return;
 
-#ifdef ARCH_bpf
-    case bfd_arch_bpf:
-#endif
 #ifdef ARCH_m32c
     case bfd_arch_m32c:
 #endif
-#if defined ARCH_bpf || defined ARCH_m32c
+#if defined ARCH_m32c
       if (info->private_data)
 	{
 	  CGEN_BITSET *mask = info->private_data;
