diff mbox series

[v6,07/15] RISC-V: Add support for the Zvksh ISA extension

Message ID 20230701052104.4018352-8-christoph.muellner@vrull.eu
State Accepted
Headers
Series RISC-V: Add support for vector crypto extensions |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Christoph Müllner July 1, 2023, 5:20 a.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvksh is part of the vector crypto extensions.

This extension adds the following instructions:
- vsm3me.vv
- vsm3c.vi

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvksh.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvksh.d: New test.
	* testsuite/gas/riscv/zvksh.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VSM3C_VI): New.
	(MASK_VSM3C_VI): New.
	(MATCH_VSM3ME_VV): New.
	(MASK_VSM3ME_VV): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvksh.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvksh instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 bfd/elfxx-riscv.c               |  5 +++++
 gas/testsuite/gas/riscv/zvksh.d | 11 +++++++++++
 gas/testsuite/gas/riscv/zvksh.s |  3 +++
 include/opcode/riscv-opc.h      |  8 ++++++++
 include/opcode/riscv.h          |  1 +
 opcodes/riscv-opc.c             |  4 ++++
 6 files changed, 32 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksh.d
 create mode 100644 gas/testsuite/gas/riscv/zvksh.s
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index f3f8a7401d9..10cdcc2eb84 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1269,6 +1269,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksh",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2451,6 +2452,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zvknhb"));
     case INSN_CLASS_ZVKSED:
       return riscv_subset_supports (rps, "zvksed");
+    case INSN_CLASS_ZVKSH:
+      return riscv_subset_supports (rps, "zvksh");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2653,6 +2656,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvknhb");
     case INSN_CLASS_ZVKSED:
       return _("zvksed");
+    case INSN_CLASS_ZVKSH:
+      return _("zvksh");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksh.d b/gas/testsuite/gas/riscv/zvksh.d
new file mode 100644
index 00000000000..b24d126ed7b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.d
@@ -0,0 +1,11 @@ 
+#as: -march=rv64gc_zvksh
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+ae802277[ 	]+vsm3c.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+ae8fa277[ 	]+vsm3c.vi[ 	]+v4,v8,31
+[ 	]+[0-9a-f]+:[ 	]+82862277[ 	]+vsm3me.vv[ 	]+v4,v8,v12
diff --git a/gas/testsuite/gas/riscv/zvksh.s b/gas/testsuite/gas/riscv/zvksh.s
new file mode 100644
index 00000000000..bde705c5e33
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksh.s
@@ -0,0 +1,3 @@ 
+	vsm3c.vi v4, v8, 0
+	vsm3c.vi v4, v8, 31
+	vsm3me.vv v4, v8, v12
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 39c0cadd686..90f44153750 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2205,6 +2205,11 @@ 
 #define MASK_VSM4R_VS 0xfe0ff07f
 #define MATCH_VSM4R_VV 0xa2082077
 #define MASK_VSM4R_VV 0xfe0ff07f
+/* Zvksh instructions.  */
+#define MATCH_VSM3C_VI 0xae002077
+#define MASK_VSM3C_VI 0xfe00707f
+#define MATCH_VSM3ME_VV 0x82002077
+#define MASK_VSM3ME_VV 0xfe00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3359,6 +3364,9 @@  DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
 DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI)
 DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS)
 DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV)
+/* Zvksh instructions.  */
+DECLARE_INSN(vsm3c_vi, MATCH_VSM3C_VI, MASK_VSM3C_VI)
+DECLARE_INSN(vsm3me_vv, MATCH_VSM3ME_VV, MASK_VSM3ME_VV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c378cce71c7..d859f44fc92 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -422,6 +422,7 @@  enum riscv_insn_class
   INSN_CLASS_ZVKNHB,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
+  INSN_CLASS_ZVKSH,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 095af039040..533e3f4a079 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1935,6 +1935,10 @@  const struct riscv_opcode riscv_opcodes[] =
 {"vsm4r.vv",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R_VV, match_opcode, 0},
 {"vsm4r.vs",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R_VS, match_opcode, 0},
 
+/* Zvksh instructions.  */
+{"vsm3c.vi",     0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3C_VI, MASK_VSM3C_VI, match_opcode, 0},
+{"vsm3me.vv",    0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VSM3ME_VV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },