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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id q7-20020aa7d447000000b005183ce42da9sm7052132edr.18.2023.06.30.14.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 Jun 2023 14:57:33 -0700 (PDT) From: Christoph Muellner To: binutils@sourceware.org, Nathan Huckleberry , nhuck@pmull.org, Jeff Law , Nelson Chu , Andrew Waterman , Palmer Dabbelt , Jim Wilson , Philipp Tomsich Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH v5 03/15] RISC-V: Add support for the Zvkg ISA extension Date: Fri, 30 Jun 2023 23:57:13 +0200 Message-ID: <20230630215725.3725876-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230630215725.3725876-1-christoph.muellner@vrull.eu> References: <20230630215725.3725876-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770166753816073320?= X-GMAIL-MSGID: =?utf-8?q?1770166753816073320?= From: Christoph Müllner Zvkg is part of the vector crypto extensions. This extension adds the following instructions: - vghsh.vv - vgmul.vv bfd/ChangeLog: * elfxx-riscv.c (riscv_multi_subset_supports): Add instruction class support for Zvkg. (riscv_multi_subset_supports_ext): Likewise. gas/ChangeLog: * testsuite/gas/riscv/zvkg.d: New test. * testsuite/gas/riscv/zvkg.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_VGHSH_VV): New. (MASK_VGHSH_VV): New. (MATCH_VGMUL_VV): New. (MASK_VGMUL_VV): New. (DECLARE_INSN): New. * opcode/riscv.h (enum riscv_insn_class): Add instruction class support for Zvkg. opcodes/ChangeLog: * riscv-opc.c: Add Zvkg instructions. Signed-off-by: Nathan Huckleberry Signed-off-by: Christoph Müllner --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvkg.d | 10 ++++++++++ gas/testsuite/gas/riscv/zvkg.s | 2 ++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 6 files changed, 30 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvkg.d create mode 100644 gas/testsuite/gas/riscv/zvkg.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 295e0d2c942..84461490835 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1264,6 +1264,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2433,6 +2434,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVKG: + return riscv_subset_supports (rps, "zvkg"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2625,6 +2628,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbb"); case INSN_CLASS_ZVBC: return _("zvbc"); + case INSN_CLASS_ZVKG: + return _("zvkg"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d new file mode 100644 index 00000000000..7f898d377b2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkg.d @@ -0,0 +1,10 @@ +#as: -march=rv64gc_zvkg +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12 diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s new file mode 100644 index 00000000000..b802d6add39 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkg.s @@ -0,0 +1,2 @@ + vghsh.vv v4, v8, v12 + vgmul.vv v4, v12 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 6102feaa557..8b4b3b2662c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2163,6 +2163,11 @@ #define MASK_VCLMULH_VV 0xfc00707f #define MATCH_VCLMULH_VX 0x34006057 #define MASK_VCLMULH_VX 0xfc00707f +/* Zvkg instructions. */ +#define MATCH_VGHSH_VV 0xb2002077 +#define MASK_VGHSH_VV 0xfe00707f +#define MATCH_VGMUL_VV 0xa208a077 +#define MASK_VGMUL_VV 0xfe0ff07f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3294,6 +3299,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV) DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX) DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV) DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX) +/* Zvkg instructions. */ +DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV) +DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 783b1c01e52..b2098867a19 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -416,6 +416,7 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVKG, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 19a72903510..b2aadb1bc79 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1908,6 +1908,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0}, {"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0}, +/* Zvkg instructions. */ +{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0}, +{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },