diff mbox series

[06/14] Add support for the Zvksed ISA extension.

Message ID 20230629171839.573187-7-nhuck@google.com
State Accepted
Headers
Series Support RISC-V Vector Cryptography Extensions |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Nathan Huckleberry June 29, 2023, 5:18 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvksed is part of the vector crypto extensions.

This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c                |  5 +++++
 gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
 gas/testsuite/gas/riscv/zvksed.s |  4 ++++
 include/opcode/riscv-opc.h       | 11 +++++++++++
 include/opcode/riscv.h           |  1 +
 opcodes/riscv-opc.c              |  5 +++++
 6 files changed, 38 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvksed.d
 create mode 100644 gas/testsuite/gas/riscv/zvksed.s

Comments

Jeff Law June 30, 2023, 8:06 p.m. UTC | #1 
On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Zvksed is part of the vector crypto extensions.
> 
> This extension adds the following instructions:
> - vsm4k.vi
> - vsm4r.[vv,vs]
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> [Updated to newest version of RISC-V spec]
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c                |  5 +++++
>   gas/testsuite/gas/riscv/zvksed.d | 12 ++++++++++++
>   gas/testsuite/gas/riscv/zvksed.s |  4 ++++
>   include/opcode/riscv-opc.h       | 11 +++++++++++
>   include/opcode/riscv.h           |  1 +
>   opcodes/riscv-opc.c              |  5 +++++
>   6 files changed, 38 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvksed.d
>   create mode 100644 gas/testsuite/gas/riscv/zvksed.s
Same as 01-05, OK with ChangeLog and NEWS entries.
jeff
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index adcc606fe7e..0ec2552bfb9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1265,6 +1265,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknha",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvknhb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvksed",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2432,6 +2433,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_ZVKNHA_OR_ZVKNHB:
       return (riscv_subset_supports (rps, "zvknha")
 	      || riscv_subset_supports (rps, "zvknhb"));
+    case INSN_CLASS_ZVKSED:
+      return riscv_subset_supports (rps, "zvksed");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2604,6 +2607,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvknha");
     case INSN_CLASS_ZVKNHB:
       return _("zvknhb");
+    case INSN_CLASS_ZVKSED:
+      return _("zvksed");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvksed.d b/gas/testsuite/gas/riscv/zvksed.d
new file mode 100644
index 00000000000..48b4aafdbb1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.d
@@ -0,0 +1,12 @@ 
+#as: -march=rv64gc_zvksed
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+86802277[ 	]+vsm4k.vi[ 	]+v4,v8,0
+[ 	]+[0-9a-f]+:[ 	]+8683a277[ 	]+vsm4k.vi[ 	]+v4,v8,7
+[ 	]+[0-9a-f]+:[ 	]+a2882277[ 	]+vsm4r.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6882277[ 	]+vsm4r.vs[ 	]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvksed.s b/gas/testsuite/gas/riscv/zvksed.s
new file mode 100644
index 00000000000..754b4646adf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvksed.s
@@ -0,0 +1,4 @@ 
+	vsm4k.vi v4, v8, 0
+	vsm4k.vi v4, v8, 7
+	vsm4r.vv v4, v8
+	vsm4r.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 5590dc3b014..415930d0e3e 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2132,6 +2132,13 @@ 
 #define MASK_VSHA2CL_VV 0xfe00707f
 #define MATCH_VSHA2MS_VV 0xb6002077
 #define MASK_VSHA2MS_VV 0xfe00707f
+/* Zvksed instructions.  */
+#define MATCH_VSM4K_VI 0x86002077
+#define MASK_VSM4K_VI 0xfe00707f
+#define MATCH_VSM4R_VS 0xa6082077
+#define MASK_VSM4R_VS 0xfe0ff07f
+#define MATCH_VSM4R_VV 0xa2082077
+#define MASK_VSM4R_VV 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3241,6 +3248,10 @@  DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
 DECLARE_INSN(vsha2ch_vv, MATCH_VSHA2CH_VV, MASK_VSHA2CH_VV)
 DECLARE_INSN(vsha2cl_vv, MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV)
 DECLARE_INSN(vsha2ms_vv, MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV)
+/* Zvksed instructions.  */
+DECLARE_INSN(vsm4k_vi, MATCH_VSM4K_VI, MASK_VSM4K_VI)
+DECLARE_INSN(vsm4r_vs, MATCH_VSM4R_VS, MASK_VSM4R_VS)
+DECLARE_INSN(vsm4r_vv, MATCH_VSM4R_VV, MASK_VSM4R_VV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 4ceb191ab07..df807fe8f79 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -416,6 +416,7 @@  enum riscv_insn_class
   INSN_CLASS_ZVKNHA,
   INSN_CLASS_ZVKNHB,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
+  INSN_CLASS_ZVKSED,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index d7d3f1c1cd2..cb164169f92 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1861,6 +1861,11 @@  const struct riscv_opcode riscv_opcodes[] =
 {"vsha2cl.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2CL_VV, MASK_VSHA2CL_VV, match_opcode, 0},
 {"vsha2ms.vv",  0, INSN_CLASS_ZVKNHA_OR_ZVKNHB, "Vd,Vt,Vs", MATCH_VSHA2MS_VV, MASK_VSHA2MS_VV, match_opcode, 0},
 
+/* Zvksed instructions.  */
+{"vsm4k.vi",     0, INSN_CLASS_ZVKSED, "Vd,Vt,Vj", MATCH_VSM4K_VI, MASK_VSM4K_VI, match_opcode, 0},
+{"vsm4r.vv",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VV, MASK_VSM4R_VV, match_opcode, 0},
+{"vsm4r.vs",     0, INSN_CLASS_ZVKSED, "Vd,Vt", MATCH_VSM4R_VS, MASK_VSM4R_VS, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },