diff mbox series

[04/14] Add support for the Zvkned ISA extension.

Message ID 20230629171839.573187-5-nhuck@google.com
State Accepted
Headers
Series Support RISC-V Vector Cryptography Extensions |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Nathan Huckleberry June 29, 2023, 5:18 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

Zvkned is part of the vector crypto extensions.

This extension adds the following instructions:
- vaesef.[vv,vs]
- vaesem.[vv,vs]
- vaesdf.[vv,vs]
- vaesdm.[vv,vs]
- vaeskf1.vi
- vaeskf2.vi
- vaesz.vs

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
[Updated to newest version of RISC-V spec]
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c                |  5 +++++
 gas/testsuite/gas/riscv/zvkned.d | 21 +++++++++++++++++++
 gas/testsuite/gas/riscv/zvkned.s | 13 ++++++++++++
 include/opcode/riscv-opc.h       | 35 ++++++++++++++++++++++++++++++++
 include/opcode/riscv.h           |  1 +
 opcodes/riscv-opc.c              | 13 ++++++++++++
 6 files changed, 88 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvkned.d
 create mode 100644 gas/testsuite/gas/riscv/zvkned.s

Comments

Jeff Law June 30, 2023, 7:30 p.m. UTC | #1 
On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> From: Christoph Müllner <christoph.muellner@vrull.eu>
> 
> Zvkned is part of the vector crypto extensions.
> 
> This extension adds the following instructions:
> - vaesef.[vv,vs]
> - vaesem.[vv,vs]
> - vaesdf.[vv,vs]
> - vaesdm.[vv,vs]
> - vaeskf1.vi
> - vaeskf2.vi
> - vaesz.vs
> 
> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
> [Updated to newest version of RISC-V spec]
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c                |  5 +++++
>   gas/testsuite/gas/riscv/zvkned.d | 21 +++++++++++++++++++
>   gas/testsuite/gas/riscv/zvkned.s | 13 ++++++++++++
>   include/opcode/riscv-opc.h       | 35 ++++++++++++++++++++++++++++++++
>   include/opcode/riscv.h           |  1 +
>   opcodes/riscv-opc.c              | 13 ++++++++++++
>   6 files changed, 88 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvkned.d
>   create mode 100644 gas/testsuite/gas/riscv/zvkned.s
Same as 01-03 in this series.  Just needs ChangeLog and NEWS entries and 
it's OK for the trunk.

Thanks,
jeff
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index b51d4f4438f..cb3420540e9 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1262,6 +1262,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvkned",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2420,6 +2421,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbc");
     case INSN_CLASS_ZVKG:
       return riscv_subset_supports (rps, "zvkg");
+    case INSN_CLASS_ZVKNED:
+      return riscv_subset_supports (rps, "zvkned");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2586,6 +2589,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvbc");
     case INSN_CLASS_ZVKG:
       return _("zvkg");
+    case INSN_CLASS_ZVKNED:
+      return _("zvkned");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvkned.d b/gas/testsuite/gas/riscv/zvkned.d
new file mode 100644
index 00000000000..0b09da9dbc2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.d
@@ -0,0 +1,21 @@ 
+#as: -march=rv64gc_zvkned
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+a280a277[ 	]+vaesdf.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a680a277[ 	]+vaesdf.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a2802277[ 	]+vaesdm.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6802277[ 	]+vaesdm.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a281a277[ 	]+vaesef.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a681a277[ 	]+vaesef.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a2812277[ 	]+vaesem.vv[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+a6812277[ 	]+vaesem.vs[ 	]+v4,v8
+[ 	]+[0-9a-f]+:[ 	]+8a812277[ 	]+vaeskf1.vi[ 	]+v4,v8,2
+[ 	]+[0-9a-f]+:[ 	]+8a872277[ 	]+vaeskf1.vi[ 	]+v4,v8,14
+[ 	]+[0-9a-f]+:[ 	]+aa812277[ 	]+vaeskf2.vi[ 	]+v4,v8,2
+[ 	]+[0-9a-f]+:[ 	]+aa872277[ 	]+vaeskf2.vi[ 	]+v4,v8,14
+[ 	]+[0-9a-f]+:[ 	]+a683a277[ 	]+vaesz.vs[ 	]+v4,v8
diff --git a/gas/testsuite/gas/riscv/zvkned.s b/gas/testsuite/gas/riscv/zvkned.s
new file mode 100644
index 00000000000..f0f3811eaec
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkned.s
@@ -0,0 +1,13 @@ 
+	vaesdf.vv v4, v8
+	vaesdf.vs v4, v8
+	vaesdm.vv v4, v8
+	vaesdm.vs v4, v8
+	vaesef.vv v4, v8
+	vaesef.vs v4, v8
+	vaesem.vv v4, v8
+	vaesem.vs v4, v8
+	vaeskf1.vi v4, v8, 2
+	vaeskf1.vi v4, v8, 14
+	vaeskf2.vi v4, v8, 2
+	vaeskf2.vi v4, v8, 14
+	vaesz.vs v4, v8
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9bc75fd0e59..48ba80cda63 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2102,6 +2102,29 @@ 
 #define MASK_VGHSH_VV 0xfe00707f
 #define MATCH_VGMUL_VV 0xa208a077
 #define MASK_VGMUL_VV 0xfe0ff07f
+/* Zvkned instructions.  */
+#define MATCH_VAESDF_VS 0xa600a077
+#define MASK_VAESDF_VS 0xfe0ff07f
+#define MATCH_VAESDF_VV 0xa200a077
+#define MASK_VAESDF_VV 0xfe0ff07f
+#define MATCH_VAESDM_VS 0xa6002077
+#define MASK_VAESDM_VS 0xfe0ff07f
+#define MATCH_VAESDM_VV 0xa2002077
+#define MASK_VAESDM_VV 0xfe0ff07f
+#define MATCH_VAESEF_VS 0xa601a077
+#define MASK_VAESEF_VS 0xfe0ff07f
+#define MATCH_VAESEF_VV 0xa201a077
+#define MASK_VAESEF_VV 0xfe0ff07f
+#define MATCH_VAESEM_VS 0xa6012077
+#define MASK_VAESEM_VS 0xfe0ff07f
+#define MATCH_VAESEM_VV 0xa2012077
+#define MASK_VAESEM_VV 0xfe0ff07f
+#define MATCH_VAESKF1_VI 0x8a002077
+#define MASK_VAESKF1_VI 0xfe00707f
+#define MATCH_VAESKF2_VI 0xaa002077
+#define MASK_VAESKF2_VI 0xfe00707f
+#define MATCH_VAESZ_VS 0xa603a077
+#define MASK_VAESZ_VS 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3195,6 +3218,18 @@  DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
 /* Zvkg instructions.  */
 DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
 DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
+/* Zvkned instructions.  */
+DECLARE_INSN(vaesdf_vs, MATCH_VAESDF_VS, MASK_VAESDF_VS)
+DECLARE_INSN(vaesdf_vv, MATCH_VAESDF_VV, MASK_VAESDF_VV)
+DECLARE_INSN(vaesdm_vs, MATCH_VAESDM_VS, MASK_VAESDM_VS)
+DECLARE_INSN(vaesdm_vv, MATCH_VAESDM_VV, MASK_VAESDM_VV)
+DECLARE_INSN(vaesef_vs, MATCH_VAESEF_VS, MASK_VAESEF_VS)
+DECLARE_INSN(vaesef_vv, MATCH_VAESEF_VV, MASK_VAESEF_VV)
+DECLARE_INSN(vaesem_vs, MATCH_VAESEM_VS, MASK_VAESEM_VS)
+DECLARE_INSN(vaesem_vv, MATCH_VAESEM_VV, MASK_VAESEM_VV)
+DECLARE_INSN(vaeskf1_vi, MATCH_VAESKF1_VI, MASK_VAESKF1_VI)
+DECLARE_INSN(vaeskf2_vi, MATCH_VAESKF2_VI, MASK_VAESKF2_VI)
+DECLARE_INSN(vaesz_vs, MATCH_VAESZ_VS, MASK_VAESZ_VS)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index ae13dc17022..e921e1b8a2a 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -412,6 +412,7 @@  enum riscv_insn_class
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVKG,
+  INSN_CLASS_ZVKNED,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 09c8444ee74..7e73c1a739d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1843,6 +1843,19 @@  const struct riscv_opcode riscv_opcodes[] =
 {"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
 {"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
 
+/* Zvkned instructions.  */
+{"vaesdf.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VV, MASK_VAESDF_VV, match_opcode, 0},
+{"vaesdf.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDF_VS, MASK_VAESDF_VV, match_opcode, 0},
+{"vaesdm.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VV, MASK_VAESDM_VV, match_opcode, 0},
+{"vaesdm.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESDM_VS, MASK_VAESDM_VV, match_opcode, 0},
+{"vaesef.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VV, MASK_VAESEF_VV, match_opcode, 0},
+{"vaesef.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEF_VS, MASK_VAESEF_VV, match_opcode, 0},
+{"vaesem.vv",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VV, MASK_VAESEM_VV, match_opcode, 0},
+{"vaesem.vs",   0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESEM_VS, MASK_VAESEM_VV, match_opcode, 0},
+{"vaeskf1.vi",   0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF1_VI, MASK_VAESKF1_VI, match_opcode, 0},
+{"vaeskf2.vi",   0, INSN_CLASS_ZVKNED, "Vd,Vt,Vj", MATCH_VAESKF2_VI, MASK_VAESKF2_VI, match_opcode, 0},
+{"vaesz.vs",     0, INSN_CLASS_ZVKNED, "Vd,Vt", MATCH_VAESZ_VS, MASK_VAESZ_VS, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },