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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id bx14-20020a170906a1ce00b009889baa6a24si7070384ejb.1032.2023.06.29.10.23.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 10:23:37 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=btcw5bHT; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 982BB3882665 for ; Thu, 29 Jun 2023 17:20:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 982BB3882665 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1688059255; bh=JoOJFbPgte8iTq6t62aORQfj4I7CkYnnmkIxA41lqKc=; h=Date:In-Reply-To:References:Subject:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=btcw5bHTAL9qaY3jPCxxi+JAKExY8prJ0LxVYvls/0S/VZaP0lTlC6ND0Mhv3NucS +dKq+meafCWFnYKh2MWO8S7mI1AVCV9MI7zKKflyc8aDRLyPTtlZbsPuEyMqPbk8pX wz6plIJ5AOsmr82TYPy8AkRkjSm6ktPDHPCLlOCk= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-yb1-xb49.google.com (mail-yb1-xb49.google.com [IPv6:2607:f8b0:4864:20::b49]) by sourceware.org (Postfix) with ESMTPS id 49C033858C33 for ; Thu, 29 Jun 2023 17:18:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 49C033858C33 Received: by mail-yb1-xb49.google.com with SMTP id 3f1490d57ef6-bd69ee0edacso679654276.3 for ; Thu, 29 Jun 2023 10:18:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688059127; x=1690651127; h=content-transfer-encoding:cc:to:from:subject:message-id:references :mime-version:in-reply-to:date:x-gm-message-state:from:to:cc:subject :date:message-id:reply-to; bh=JoOJFbPgte8iTq6t62aORQfj4I7CkYnnmkIxA41lqKc=; b=EM5Hos8rVsLjAtFr/WeFdvjU4AfQdbcKev0xh4NmQ7VOrehQYybeQ0s9uAbObM7IDu W6/mSJ/9A6NMyrbScYlseguszfkcpzRrEenXcPf0kYMK2dZXO8qjXn2Klo/vmgjZ87rY Y0WHTnTbBbTy29mkLs7FbC3yVy7Y9lqOb4ugmszJJESqxKAX5RCNvZXAJfLO58tt0MFK rzsPbIhlbwMiaBFklXkb/pREdxoZjbZR7goxPXl+EuTJPRzDELAdqKid9ctmfo62Qew4 bjuuhrw1Or+NTWIyDBuxr/vScwMaQAYB3z20hJbPP06cyaEA8tfVGOmDjX3ez0NoRcNa zGZw== X-Gm-Message-State: ABy/qLZILq/ikK1rJMDMjNj+52wEEztf0L6Pcxv3M0csa1oUlnrwT0bS IUPuhkPgsoRGQMHpgsDcYD5VMcJqMAhJw+u5HrHCLKeD5pkVM/5/NM9Em4A2KaaZITmdZBBfR53 lBAQWv8BwcsJswjmDC+DRRxe8AMtBo6ohtX2t7oLfEg8U/UOu73NcHcGNV2bX X-Received: from nhuck.c.googlers.com ([fda3:e722:ac3:cc00:14:4d90:c0a8:39cc]) (user=nhuck job=sendgmr) by 2002:a25:c944:0:b0:be4:7214:7aef with SMTP id z65-20020a25c944000000b00be472147aefmr3349ybf.10.1688059127670; Thu, 29 Jun 2023 10:18:47 -0700 (PDT) Date: Thu, 29 Jun 2023 10:18:28 -0700 In-Reply-To: <20230629171839.573187-1-nhuck@google.com> Mime-Version: 1.0 References: <20230629171839.573187-1-nhuck@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230629171839.573187-4-nhuck@google.com> Subject: [PATCH 03/14] Add support for the Zvkg ISA extension. To: binutils@sourceware.org Cc: nhuck@pmull.org, " =?utf-8?q?Christoph_M=C3=BCllner?= " , Nathan Huckleberry X-Spam-Status: No, score=-20.5 required=5.0 tests=BAYES_00, DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Nathan Huckleberry via Binutils From: Nathan Huckleberry Reply-To: Nathan Huckleberry Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770058592016387492?= X-GMAIL-MSGID: =?utf-8?q?1770058592016387492?= From: Christoph Müllner Zvkg is part of the vector crypto extensions. This extension adds the following instructions: - vghsh.vv - vgmul.vv Signed-off-by: Christoph Müllner [Updated to newest version of RISC-V spec] Signed-off-by: Nathan Huckleberry --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvkg.d | 10 ++++++++++ gas/testsuite/gas/riscv/zvkg.s | 2 ++ include/opcode/riscv-opc.h | 8 ++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 4 ++++ 6 files changed, 30 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvkg.d create mode 100644 gas/testsuite/gas/riscv/zvkg.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index a56b2b840b6..b51d4f4438f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1261,6 +1261,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2417,6 +2418,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "zvbb"); case INSN_CLASS_ZVBC: return riscv_subset_supports (rps, "zvbc"); + case INSN_CLASS_ZVKG: + return riscv_subset_supports (rps, "zvkg"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2581,6 +2584,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zvbb"); case INSN_CLASS_ZVBC: return _("zvbc"); + case INSN_CLASS_ZVKG: + return _("zvkg"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d new file mode 100644 index 00000000000..7f898d377b2 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkg.d @@ -0,0 +1,10 @@ +#as: -march=rv64gc_zvkg +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+b2862277[ ]+vghsh.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+a2c8a277[ ]+vgmul.vv[ ]+v4,v12 diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s new file mode 100644 index 00000000000..b802d6add39 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvkg.s @@ -0,0 +1,2 @@ + vghsh.vv v4, v8, v12 + vgmul.vv v4, v12 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e1f2966499a..9bc75fd0e59 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2097,6 +2097,11 @@ #define MASK_VCLMULH_VV 0xfc00707f #define MATCH_VCLMULH_VX 0x34006057 #define MASK_VCLMULH_VX 0xfc00707f +/* Zvkg instructions. */ +#define MATCH_VGHSH_VV 0xb2002077 +#define MASK_VGHSH_VV 0xfe00707f +#define MATCH_VGMUL_VV 0xa208a077 +#define MASK_VGMUL_VV 0xfe0ff07f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3187,6 +3192,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV) DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX) DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV) DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX) +/* Zvkg instructions. */ +DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV) +DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 0f00bc2e6fb..ae13dc17022 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -411,6 +411,7 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVKG, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 79a5e2c694a..09c8444ee74 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1839,6 +1839,10 @@ const struct riscv_opcode riscv_opcodes[] = {"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0}, {"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0}, +/* Zvkg instructions. */ +{"vghsh.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0}, +{"vgmul.vv", 0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },