From patchwork Thu Jun 29 17:18:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nathan Huckleberry X-Patchwork-Id: 114371 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp9792976vqr; Thu, 29 Jun 2023 10:21:16 -0700 (PDT) X-Google-Smtp-Source: APBJJlHaHHqCjme47/PMfysMD02sRn/+VNvbW/zKAtQo/2jWl8YaR46yPgRieqzG7XjoMMYqBGcK X-Received: by 2002:a17:906:74d2:b0:991:eb77:74e with SMTP id z18-20020a17090674d200b00991eb77074emr74980ejl.76.1688059276303; Thu, 29 Jun 2023 10:21:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688059276; cv=none; d=google.com; s=arc-20160816; b=N082x0UeLAcqdAYTJvhX1xNh6rP2sEh/2S+5KPfPZ/77ju8j2SnyjXJYWNNgJ4N2lP KbT2hoV0uvC9p4CXtLVZdAmrxG6/Hd78btCaarXAA5N6E6CMJYAkZegNnw6HmCvXR+u9 QPzFQ5GTXUnJpjzTuVY9ec+oQQFwQBW9uFIokY7H9z+j3dtP+VaYqS1Ofns+I+Mk/4rk LrKxIz+LgKH11ui7dYvlWXj/b8gcGDGcq9ewgKm1PZULDYrAF98/rPROJByLxbF2nF49 R+1ijEwk86Z/QG8UZhlNwxPS3272mcJ8bGGghkjni2r29Bv98DXQkR+Iy2LKAodDnnL6 5K/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence:cc:to:subject :message-id:references:mime-version:in-reply-to:date:dmarc-filter :delivered-to:dkim-signature:dkim-filter; bh=Y44I93U3uQhmFATPIx8QdCU3zWVa2GXdrDa4KirpBr8=; fh=UAQ7TJWJ6TlMgg8W5zyiu6mYFbaY4TYaXWSfeZlVf34=; b=07HsvK3is5F2Va8kY62mlTo9to/SESfvCMGI2ywdTH0IWZu5weFGfsVYrBd0J6Dka0 Az0E4bNRZ+G3pYoDpeqQRnJqnpMFx/bb2UF62MdwK6GSg+nIFhoSwI0xqfqflotdHF3e Qbb6Y0VMhclbDkpgo5+SYfjJ4wFRSy2PlmIP3joYeBPf34mAU2JE5mMnwOpx2EPlFkby 9cBfcAd7snqAcq5xaRsWrlD4DYVcVRVrrq3euTuMqSpM/hiS7Qli2HlnR+ybyA9bNuOW ibNwpKEc4UHrr40YwguCgsKZD0h2/aYdBFHuxXlxozNp/0lATDUvkAnK2uZBlAHSHmXl mw0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ylytM19M; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id u14-20020a170906780e00b00991f96678cesi4404830ejm.615.2023.06.29.10.21.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jun 2023 10:21:16 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=ylytM19M; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F2FE63858408 for ; Thu, 29 Jun 2023 17:19:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F2FE63858408 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1688059195; bh=Y44I93U3uQhmFATPIx8QdCU3zWVa2GXdrDa4KirpBr8=; h=Date:In-Reply-To:References:Subject:To:Cc:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ylytM19MCZDIFLSvXWmVoMAeJDs3Rqc07hOjw0y1iip7IvE45Um7ALFMzLtGpU3r2 6dBOBeZMwn9ABBFUCm1GmqpAUHrzHm88PN7bUjDdfNzzfCJwV8XG5r3i5VWDGovNFE c7doTr7SrTjHy1gE9miQB09/qqvLHVMTVh0InLd8= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-yw1-x114a.google.com (mail-yw1-x114a.google.com [IPv6:2607:f8b0:4864:20::114a]) by sourceware.org (Postfix) with ESMTPS id 728CA3858C2D for ; Thu, 29 Jun 2023 17:18:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 728CA3858C2D Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-56942667393so7121037b3.2 for ; Thu, 29 Jun 2023 10:18:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688059126; x=1690651126; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Y44I93U3uQhmFATPIx8QdCU3zWVa2GXdrDa4KirpBr8=; b=CHkYtqL0HWx5t/mC80VigSxOrBDdGrHp006Hz0uxtKXh7/OGWkP+3Y7uK/IbGQL0Kk vfrVVkCgncgjI8DKP9CJtlkwNMqIIx0RaL4EoKpZeZ2Fht57jEDX//tElcNdCS0jXBnN p5sYWo20q2/UXuyJGfI4pFujiUzcmfrBcNIEsUGbRF0oTvzGyMA6IXJIllWj+igRusae 1sp2zE/wgzCqM/yYmU7nXsA2zUEPErpLNw8vwRpkpS1278Bs+KMI6BKyARktEjSHX46c cVhGM3qnHI05BEtIvuM0cuqwBth0b+KGlHqodmRbHhiQYUZy+POPSfoWqEjUQlYWIDfh iKRA== X-Gm-Message-State: ABy/qLYEEm65N49sRRbFd0dJIJrDPshPRz9oU/vcP4+a/cH9+AUqOMIY /O7ed6XXXg/Q3YxW6ETJh+4VMwn3P3x+D1hpYLoXxEUa2muxnCNMQ48BmgxDpF/HOryyxKgwPVe p6I8X7A8uBM9hNuX1IVtJ8X8L8qP8ZG62wp10SPefp+IFW+ys2wN7MeV07QzK X-Received: from nhuck.c.googlers.com ([fda3:e722:ac3:cc00:14:4d90:c0a8:39cc]) (user=nhuck job=sendgmr) by 2002:a81:c646:0:b0:576:f3ee:4e67 with SMTP id q6-20020a81c646000000b00576f3ee4e67mr28ywj.8.1688059125235; Thu, 29 Jun 2023 10:18:45 -0700 (PDT) Date: Thu, 29 Jun 2023 10:18:27 -0700 In-Reply-To: <20230629171839.573187-1-nhuck@google.com> Mime-Version: 1.0 References: <20230629171839.573187-1-nhuck@google.com> X-Mailer: git-send-email 2.41.0.255.g8b1d071c50-goog Message-ID: <20230629171839.573187-3-nhuck@google.com> Subject: [PATCH 02/14] Add support for the Zvbc ISA extension. To: binutils@sourceware.org Cc: nhuck@pmull.org, Nathan Huckleberry X-Spam-Status: No, score=-20.0 required=5.0 tests=BAYES_00, DKIMWL_WL_MED, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Nathan Huckleberry via Binutils From: Nathan Huckleberry Reply-To: Nathan Huckleberry Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1770058443461870427?= X-GMAIL-MSGID: =?utf-8?q?1770058443461870427?= Zvbc is part of the crypto vector extensions. This extension adds the following instructions: - vclmul.[vv,vx] - vclmulh.[vv,vx] Signed-off-by: Nathan Huckleberry --- bfd/elfxx-riscv.c | 5 +++++ gas/testsuite/gas/riscv/zvbc.d | 16 ++++++++++++++++ gas/testsuite/gas/riscv/zvbc.s | 8 ++++++++ include/opcode/riscv-opc.h | 14 ++++++++++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 6 ++++++ 6 files changed, 50 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zvbc.d create mode 100644 gas/testsuite/gas/riscv/zvbc.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 8342b4fb3cc..a56b2b840b6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1260,6 +1260,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2414,6 +2415,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve32f")); case INSN_CLASS_ZVBB: return riscv_subset_supports (rps, "zvbb"); + case INSN_CLASS_ZVBC: + return riscv_subset_supports (rps, "zvbc"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2576,6 +2579,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("v' or `zve64d' or `zve64f' or `zve32f"); case INSN_CLASS_ZVBB: return _("zvbb"); + case INSN_CLASS_ZVBC: + return _("zvbc"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/gas/testsuite/gas/riscv/zvbc.d b/gas/testsuite/gas/riscv/zvbc.d new file mode 100644 index 00000000000..d9213b25b01 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvbc.d @@ -0,0 +1,16 @@ +#as: -march=rv64gc_zvbc +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+32862257[ ]+vclmul.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+30862257[ ]+vclmul.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+3285e257[ ]+vclmul.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3085e257[ ]+vclmul.vx[ ]+v4,v8,a1,v0.t +[ ]+[0-9a-f]+:[ ]+36862257[ ]+vclmulh.vv[ ]+v4,v8,v12 +[ ]+[0-9a-f]+:[ ]+34862257[ ]+vclmulh.vv[ ]+v4,v8,v12,v0.t +[ ]+[0-9a-f]+:[ ]+3685e257[ ]+vclmulh.vx[ ]+v4,v8,a1 +[ ]+[0-9a-f]+:[ ]+3485e257[ ]+vclmulh.vx[ ]+v4,v8,a1,v0.t diff --git a/gas/testsuite/gas/riscv/zvbc.s b/gas/testsuite/gas/riscv/zvbc.s new file mode 100644 index 00000000000..c302d1eb011 --- /dev/null +++ b/gas/testsuite/gas/riscv/zvbc.s @@ -0,0 +1,8 @@ + vclmul.vv v4, v8, v12 + vclmul.vv v4, v8, v12, v0.t + vclmul.vx v4, v8, a1 + vclmul.vx v4, v8, a1, v0.t + vclmulh.vv v4, v8, v12 + vclmulh.vv v4, v8, v12, v0.t + vclmulh.vx v4, v8, a1 + vclmulh.vx v4, v8, a1, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index cde8c341b6b..e1f2966499a 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2088,6 +2088,15 @@ #define MASK_VWSLL_VV 0xfc00707f #define MATCH_VWSLL_VX 0xd4004057 #define MASK_VWSLL_VX 0xfc00707f +/* Zvbc instructions. */ +#define MATCH_VCLMUL_VV 0x30002057 +#define MASK_VCLMUL_VV 0xfc00707f +#define MATCH_VCLMUL_VX 0x30006057 +#define MASK_VCLMUL_VX 0xfc00707f +#define MATCH_VCLMULH_VV 0x34002057 +#define MASK_VCLMULH_VV 0xfc00707f +#define MATCH_VCLMULH_VX 0x34006057 +#define MASK_VCLMULH_VX 0xfc00707f /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3173,6 +3182,11 @@ DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX) DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI) DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV) DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX) +/* Zvbc instructions. */ +DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV) +DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX) +DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV) +DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 296fbe2640c..0f00bc2e6fb 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -410,6 +410,7 @@ enum riscv_insn_class INSN_CLASS_V, INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, + INSN_CLASS_ZVBC, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 763d42db4d0..79a5e2c694a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1833,6 +1833,12 @@ const struct riscv_opcode riscv_opcodes[] = {"vwsll.vx", 0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0}, {"vwsll.vi", 0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0}, +/* Zvbc instructions. */ +{"vclmul.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0}, +{"vclmul.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0}, +{"vclmulh.vv", 0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0}, +{"vclmulh.vx", 0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0}, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrw", 0, INSN_CLASS_ZICSR, "E,s", MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },