diff mbox series

[02/14] Add support for the Zvbc ISA extension.

Message ID 20230629171839.573187-3-nhuck@google.com
State Accepted
Headers
Series Support RISC-V Vector Cryptography Extensions |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Nathan Huckleberry June 29, 2023, 5:18 p.m. UTC 
  Zvbc is part of the crypto vector extensions.

This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
---
 bfd/elfxx-riscv.c              |  5 +++++
 gas/testsuite/gas/riscv/zvbc.d | 16 ++++++++++++++++
 gas/testsuite/gas/riscv/zvbc.s |  8 ++++++++
 include/opcode/riscv-opc.h     | 14 ++++++++++++++
 include/opcode/riscv.h         |  1 +
 opcodes/riscv-opc.c            |  6 ++++++
 6 files changed, 50 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zvbc.d
 create mode 100644 gas/testsuite/gas/riscv/zvbc.s

Comments

Jeff Law June 30, 2023, 5:56 p.m. UTC | #1 
On 6/29/23 11:18, Nathan Huckleberry via Binutils wrote:
> Zvbc is part of the crypto vector extensions.
> 
> This extension adds the following instructions:
> - vclmul.[vv,vx]
> - vclmulh.[vv,vx]
> 
> Signed-off-by: Nathan Huckleberry <nhuck@google.com>
> ---
>   bfd/elfxx-riscv.c              |  5 +++++
>   gas/testsuite/gas/riscv/zvbc.d | 16 ++++++++++++++++
>   gas/testsuite/gas/riscv/zvbc.s |  8 ++++++++
>   include/opcode/riscv-opc.h     | 14 ++++++++++++++
>   include/opcode/riscv.h         |  1 +
>   opcodes/riscv-opc.c            |  6 ++++++
>   6 files changed, 50 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/zvbc.d
>   create mode 100644 gas/testsuite/gas/riscv/zvbc.s
Same as patch 01/14 in this series.  Needs ChangeLog & NEWS entries.

jeff
diff mbox series

Patch

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 8342b4fb3cc..a56b2b840b6 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1260,6 +1260,7 @@  static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64f",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
+  {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0,  0 },
@@ -2414,6 +2415,8 @@  riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve32f"));
     case INSN_CLASS_ZVBB:
       return riscv_subset_supports (rps, "zvbb");
+    case INSN_CLASS_ZVBC:
+      return riscv_subset_supports (rps, "zvbc");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2576,6 +2579,8 @@  riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64d' or `zve64f' or `zve32f");
     case INSN_CLASS_ZVBB:
       return _("zvbb");
+    case INSN_CLASS_ZVBC:
+      return _("zvbc");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/testsuite/gas/riscv/zvbc.d b/gas/testsuite/gas/riscv/zvbc.d
new file mode 100644
index 00000000000..d9213b25b01
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbc.d
@@ -0,0 +1,16 @@ 
+#as: -march=rv64gc_zvbc
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[ 	]+[0-9a-f]+:[ 	]+32862257[ 	]+vclmul.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+30862257[ 	]+vclmul.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3285e257[ 	]+vclmul.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3085e257[ 	]+vclmul.vx[ 	]+v4,v8,a1,v0.t
+[ 	]+[0-9a-f]+:[ 	]+36862257[ 	]+vclmulh.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+34862257[ 	]+vclmulh.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+3685e257[ 	]+vclmulh.vx[ 	]+v4,v8,a1
+[ 	]+[0-9a-f]+:[ 	]+3485e257[ 	]+vclmulh.vx[ 	]+v4,v8,a1,v0.t
diff --git a/gas/testsuite/gas/riscv/zvbc.s b/gas/testsuite/gas/riscv/zvbc.s
new file mode 100644
index 00000000000..c302d1eb011
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbc.s
@@ -0,0 +1,8 @@ 
+	vclmul.vv v4, v8, v12
+	vclmul.vv v4, v8, v12, v0.t
+	vclmul.vx v4, v8, a1
+	vclmul.vx v4, v8, a1, v0.t
+	vclmulh.vv v4, v8, v12
+	vclmulh.vv v4, v8, v12, v0.t
+	vclmulh.vx v4, v8, a1
+	vclmulh.vx v4, v8, a1, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index cde8c341b6b..e1f2966499a 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2088,6 +2088,15 @@ 
 #define MASK_VWSLL_VV 0xfc00707f
 #define MATCH_VWSLL_VX 0xd4004057
 #define MASK_VWSLL_VX 0xfc00707f
+/* Zvbc instructions. */
+#define MATCH_VCLMUL_VV 0x30002057
+#define MASK_VCLMUL_VV 0xfc00707f
+#define MATCH_VCLMUL_VX 0x30006057
+#define MASK_VCLMUL_VX 0xfc00707f
+#define MATCH_VCLMULH_VV 0x34002057
+#define MASK_VCLMULH_VV 0xfc00707f
+#define MATCH_VCLMULH_VX 0x34006057
+#define MASK_VCLMULH_VX 0xfc00707f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3173,6 +3182,11 @@  DECLARE_INSN(vror_vx, MATCH_VROR_VX, MASK_VROR_VX)
 DECLARE_INSN(vwsll_vi, MATCH_VWSLL_VI, MASK_VWSLL_VI)
 DECLARE_INSN(vwsll_vv, MATCH_VWSLL_VV, MASK_VWSLL_VV)
 DECLARE_INSN(vwsll_vx, MATCH_VWSLL_VX, MASK_VWSLL_VX)
+/* Zvbc instructions.  */
+DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
+DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
+DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
+DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 296fbe2640c..0f00bc2e6fb 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -410,6 +410,7 @@  enum riscv_insn_class
   INSN_CLASS_V,
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
+  INSN_CLASS_ZVBC,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 763d42db4d0..79a5e2c694a 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1833,6 +1833,12 @@  const struct riscv_opcode riscv_opcodes[] =
 {"vwsll.vx",    0, INSN_CLASS_ZVBB, "Vd,Vt,sVm", MATCH_VWSLL_VX, MASK_VWSLL_VX, match_opcode, 0},
 {"vwsll.vi",    0, INSN_CLASS_ZVBB, "Vd,Vt,VjVm", MATCH_VWSLL_VI, MASK_VWSLL_VI, match_opcode, 0},
 
+/* Zvbc instructions.  */
+{"vclmul.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMUL_VV, MASK_VCLMUL_VV, match_opcode, 0},
+{"vclmul.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMUL_VX, MASK_VCLMUL_VX, match_opcode, 0},
+{"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
+{"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },