diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 9375ba3318..5fc996409a 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -976,8 +976,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"flushid",		"",		0xbc030000, 0xffffffff, 0, 			0,		L1,		0,	0 },
 {"wb",			"o(b)",		0xbc040000, 0xfc1f0000, RD_2|SM,		0,		L1,		0,	0 },
 {"cache",		"k,+j(b)",	0x7c000025, 0xfc00007f, RD_3,			0,		I37,		0,	0 },
-{"cache",		"k,o(b)",	0xbc000000, 0xfc000000, RD_3,           	0,		I3_32|T3,	0,	I37 },
-{"cache",		"k,A(b)",	0,    (int) M_CACHE_AB, INSN_MACRO,		0,		I3_32|T3,	0,	0 },
+{"cache",		"k,o(b)",	0xbc000000, 0xfc000000, RD_3,           	0,		I3_32|T3|AL,	0,	I37 },
+{"cache",		"k,A(b)",	0,    (int) M_CACHE_AB, INSN_MACRO,		0,		I3_32|T3|AL,	0,	0 },
 {"ceil.l.d",		"D,S",		0x4620000a, 0xffff003f, WR_1|RD_2|FP_D,		0,		I3_33,		0,	0 },
 {"ceil.l.s",		"D,S",		0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I3_33,		0,	0 },
 {"ceil.w.d",		"D,S",		0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I2,		0,	SF },
@@ -994,8 +994,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cins32",		"t,r,+p,+s",	0x70000033, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
 {"cins",		"t,r,+P,+S",	0x70000033, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 }, /* cins32 */
 {"cins",		"t,r,+p,+S",	0x70000032, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
+{"clo",			"d,s",		0x00000017, 0xfc1f07ff, WR_1|RD_2,		0,		AL,		0,	0 },
 {"clo",			"d,s",		0x00000051, 0xfc1f07ff, WR_1|RD_2,		0,		I37,		0,	0 },
 {"clo",			"U,s",		0x70000021, 0xfc0007ff, WR_1|RD_2,		0,		I32|N55,	0,	I37 },
+{"clz",			"d,s",		0x00000016, 0xfc1f07ff, WR_1|RD_2,		0,		AL,		0,	0 },
 {"clz",			"d,s",		0x00000050, 0xfc1f07ff, WR_1|RD_2,		0,		I37,		0,	0 },
 {"clz",			"U,s",		0x70000020, 0xfc0007ff, WR_1|RD_2,		0,		I32|N55,	0,	I37 },
 /* ctc0 is at the bottom of the table.  */
@@ -1142,7 +1144,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dremu",		"z,s,t",	0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,		I3,		0,	M32|I69 },
 {"dremu",		"d,v,t",	0,    (int) M_DREMU_3,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
 {"dremu",		"d,v,I",	0,    (int) M_DREMU_3I,	INSN_MACRO,		0,		I3,		0,	M32|I69 },
-{"dret",		"",		0x7000003e, 0xffffffff,	0,			0,		N5,		0,	0 },
+{"dret",		"",		0x7000003e, 0xffffffff,	0,			0,		N5|AL,		0,	0 },
 {"drol",		"d,v,t",	0,    (int) M_DROL,	INSN_MACRO,		0,		I3,		0,	0 },
 {"drol",		"d,v,I",	0,    (int) M_DROL_I,	INSN_MACRO,		0,		I3,		0,	0 },
 {"dror",		"d,v,t",	0,    (int) M_DROR,	INSN_MACRO,		0,		I3,		0,	0 },
@@ -1200,7 +1202,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"evpe",		"t",		0x41600021, 0xffe0ffff, WR_1|TRAP,		0,		0,		MT32,	0 },
 {"evp",			"",		0x41600004, 0xffffffff, TRAP,			0,		I37,		0,	0 },
 {"evp",			"t",		0x41600004, 0xffe0ffff, WR_1|TRAP,		0,		I37,		0,	0 },
-{"ext",			"t,r,+A,+C",	0x7c000000, 0xfc00003f, WR_1|RD_2,    		0,		I33,		0,	0 },
+{"ext",			"t,r,+A,+C",	0x7c000000, 0xfc00003f, WR_1|RD_2,    		0,		I33|AL,		0,	0 },
 {"exts32",		"t,r,+p,+s",	0x7000003b, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
 {"exts",		"t,r,+P,+S",	0x7000003b, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 }, /* exts32 */
 {"exts",		"t,r,+p,+S",	0x7000003a, 0xfc00003f, WR_1|RD_2,		0,		IOCT,		0,	0 },
@@ -1211,7 +1213,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"hibernate",		"",		0x42000023, 0xffffffff,	0, 			0,		V1,		0,	0 },
 {"hypcall",		"",		0x42000028, 0xffffffff, TRAP,			0,		0,		IVIRT,	0 },
 {"hypcall",		"+J",		0x42000028, 0xffe007ff, TRAP,			0,		0,		IVIRT,	0 },
-{"ins",			"t,r,+A,+B",	0x7c000004, 0xfc00003f, WR_1|RD_2,    		0,		I33,		0,	0 },
+{"ins",			"t,r,+A,+B",	0x7c000004, 0xfc00003f, WR_1|RD_2,    		0,		I33|AL,		0,	0 },
 {"iret",		"",		0x42000038, 0xffffffff,	NODS,			0,		0,		MC,	0 },
 {"jr",			"s",		0x00000009, 0xfc1fffff,	RD_1|UBD,		INSN2_ALIAS,	I37,		0,	0 }, /* jalr $0 */
 {"jr",			"s",		0x00000008, 0xfc1fffff,	RD_1|UBD,		0,		I1,		0,	I37 },
@@ -1374,7 +1376,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd.ps",		"D,R,S,T",	0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,		I5_33,		0,	I37 },
 {"madd.ps",		"D,S,T",	0x45600018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	     0,		IL2E,		0,	0 },
 {"madd.ps",		"D,S,T",	0x72c00018, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	     0,		IL2F,		0,	0 },
-{"madd",		"s,t",		0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,		L1,		0,	0 },
+{"madd",		"s,t",		0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,		L1|AL,		0,	0 },
 {"madd",		"s,t",		0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,		I32|N55,	0,	I37 },
 {"madd",		"s,t",		0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,		G1,		0,	0 },
 {"madd",		"7,s,t",	0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a,             0,         0,		D32,	0 },
@@ -1383,7 +1385,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd1",		"d,s,t",	0x70000020, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,		EE,		0,	0 },
 {"madda.s",		"S,T",		0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S,		     0,		EE,		0,	0 },
 {"maddp",		"s,t",		0x70000441, 0xfc00ffff,	RD_1|RD_2|MOD_HILO,	     0,		0,		SMT,	0 },
-{"maddu",		"s,t",		0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,		L1,		0,	0 },
+{"maddu",		"s,t",		0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,		L1|AL,		0,	0 },
 {"maddu",		"s,t",		0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,		I32|N55,	0,	I37 },
 {"maddu",		"s,t",		0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,		G1,		0,	0 },
 {"maddu",		"7,s,t",	0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a,             0,         0,		D32,	0 },
@@ -1391,6 +1393,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"maddu1",		"s,t",		0x70000021, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,		EE,		0,	0 },
 {"maddu1",		"d,s,t",	0x70000021, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,		EE,		0,	0 },
 {"madd16",		"s,t",		0x00000028, 0xfc00ffff, RD_1|RD_2|MOD_HILO,	0,		N411,		0,	0 },
+{"max",			"d,v,t",	0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		AL,		0,	0 },
 {"max.ob",		"X,Y,Q",	0x78000007, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"max.ob",		"D,S,Q",	0x48000007, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"max.qh",		"X,Y,Q",	0x78200007, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
@@ -1439,7 +1442,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* mfc2 is at the bottom of the table.  */
 /* mfhc2 is at the bottom of the table.  */
 /* mfc3 is at the bottom of the table.  */
-{"mfdr",		"t,G",		0x7000003d, 0xffe007ff,	WR_1|RD_C0|LC,		0,		N5,		0,	0 },
+{"mfdr",		"t,G",		0x7000003d, 0xffe007ff,	WR_1|RD_C0|LC,		0,		N5|AL,		0,	0 },
 {"mfhi",		"d",		0x00000010, 0xffff07ff,	WR_1|RD_HI,		0,		I1,		0,	I37 },
 {"mfhi",		"d,9",		0x00000010, 0xff9f07ff, WR_1|RD_HI,		0,		0,		D32,	0 },
 {"mfhi1",		"d",		0x70000010, 0xffff07ff,	WR_1|RD_HI,		0,		EE,		0,	0 },
@@ -1449,6 +1452,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mflhxu",		"d",		0x00000052, 0xffff07ff,	WR_1|MOD_HILO,		0,		0,		SMT,	0 },
 {"mfcr",		"t,s",		0x70000018, 0xfc00ffff, WR_1|RD_2,		0,		XLR,		0,	0 },
 {"mfsa",		"d",		0x00000028, 0xffff07ff,	WR_1,			0,		EE,		0,	0 },
+{"min",			"d,v,t",	0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		AL,		0,	0 },
 {"min.ob",		"X,Y,Q",	0x78000006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"min.ob",		"D,S,Q",	0x48000006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
 {"min.qh",		"X,Y,Q",	0x78200006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		0,		MX,	0 },
@@ -1464,7 +1468,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movf.l",		"X,Y,N",	0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		SB1,		MX,	0 },
 {"movf.s",		"D,S,N",	0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,		I4_32,		0,	I37 },
 {"movf.ps",		"D,S,N",	0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		I5_33,		0,	I37 },
-{"movn",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE, 0,	I37 },
+{"movn",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE|AL, 0,	I37 },
 {"movnz",		"d,v,t",	0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		IL2E|IL2F,	LEXT,	0 },
 {"ffc",			"d,v",		0x0000000b, 0xfc1f07ff,	WR_1|RD_2,		0,		L1,		0,	0 },
 {"movn.d",		"D,S,t",	0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I4_32,		0,	I37 },
@@ -1478,7 +1482,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movt.l",		"X,Y,N",	0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,		SB1,		MX,	0 },
 {"movt.s",		"D,S,N",	0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,		I4_32,		0,	I37 },
 {"movt.ps",		"D,S,N",	0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,	0,		I5_33,		0,	I37 },
-{"movz",		"d,v,t",	0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE, 0,	I37 },
+{"movz",		"d,v,t",	0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3, 	0,		I4_32|IL2E|IL2F|EE|AL, 0,	I37 },
 {"ffs",			"d,v",		0x0000000a, 0xfc1f07ff,	WR_1|RD_2,		0,		L1,		0,	0 },
 {"movz.d",		"D,S,t",	0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		I4_32,		0,	I37 },
 {"movz.l",		"D,S,t",	0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,		SB1,		MX,	0 },
@@ -1506,10 +1510,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.ps",		"D,R,S,T",	0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,		I5_33,		0,	I37 },
 {"msub.ps",		"D,S,T",	0x45600019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
 {"msub.ps",		"D,S,T",	0x72c00019, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2F,		0,	0 },
+{"msub",		"s,t",		0x0000002e, 0xfc00ffff, RD_1|RD_2|WR_HILO,	0,		AL,		0,	0 },
 {"msub",		"s,t",		0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO,	0,		L1,		0,	0 },
 {"msub",		"s,t",		0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	I37 },
 {"msub",		"7,s,t",	0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,		D32,	0 },
 {"msuba.s",		"S,T",		0x4600001f, 0xffe007ff,	RD_1|RD_2|FP_S,		0,		EE,		0,	0 },
+{"msubu",		"s,t",		0x0000002f, 0xfc00ffff, RD_1|RD_2|WR_HILO,	0,		AL,		0,	0 },
 {"msubu",		"s,t",		0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO,	0,		L1,		0,	0 },
 {"msubu",		"s,t",		0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	I37 },
 {"msubu",		"7,s,t",	0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,		D32,	0 },
@@ -1537,7 +1543,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* mtc2 is at the bottom of the table.  */
 /* mthc2 is at the bottom of the table.  */
 /* mtc3 is at the bottom of the table.  */
-{"mtdr",		"t,G",		0x7080003d, 0xffe007ff,	RD_1|WR_C0|CM,		0,		N5,		0,	0 },
+{"mtdr",		"t,G",		0x7080003d, 0xffe007ff,	RD_1|WR_C0|CM,		0,		N5|AL,		0,	0 },
 {"mthi",		"s",		0x00000011, 0xfc1fffff,	RD_1|WR_HI,		0,		I1,		0,	I37 },
 {"mthi",		"s,7",		0x00000011, 0xfc1fe7ff, RD_1|WR_HI,		0,		0,		D32,	0 },
 {"mthi1",		"s",		0x70000011, 0xfc1fffff,	RD_1|WR_HI,		0,		EE,		0,	0 },
@@ -1877,8 +1883,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdr",			"t,o(b)",	0xb4000000, 0xfc000000,	RD_1|RD_3|SM,		0,		I3,		0,	I69 },
 {"sdr",			"t,A(b)",	0,    (int) M_SDR_AB,	INSN_MACRO,		0,		I3,		0,	I69 },
 {"sdxc1",		"S,t(b)",	0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D,	0,		I4_33,		0,	I37 },
-{"seb",			"d,w",		0x7c000420, 0xffe007ff,	WR_1|RD_2,		0,		I33,		0,	0 },
-{"seh",			"d,w",		0x7c000620, 0xffe007ff,	WR_1|RD_2,		0,		I33,		0,	0 },
+{"seb",			"d,w",		0x7c000420, 0xffe007ff,	WR_1|RD_2,		0,		I33|AL,		0,	0 },
+{"seh",			"d,w",		0x7c000620, 0xffe007ff,	WR_1|RD_2,		0,		I33|AL,		0,	0 },
 {"selsl",		"d,v,t",	0x00000005, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		L1,		0,	0 },
 {"selsr",		"d,v,t",	0x00000001, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		L1,		0,	0 },
 {"seq",			"d,v,t",	0x7000002a, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		IOCT,		0,	0 },
@@ -2101,7 +2107,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"wait",		"J",		0x42000020, 0xfe00003f, NODS,   		0,		I32|N55,	0,	0 },
 {"waiti",		"",		0x42000020, 0xffffffff,	NODS,			0,		L1,		0,	0 },
 {"wrpgpr",		"d,w",		0x41c00000, 0xffe007ff, RD_2,			0,		I33,		0,	0 },
-{"wsbh",		"d,w",		0x7c0000a0, 0xffe007ff,	WR_1|RD_2,		0,		I33,		0,	0 },
+{"wsbh",		"d,w",		0x7c0000a0, 0xffe007ff,	WR_1|RD_2,		0,		I33|AL,		0,	0 },
+{"wsbw",		"d,w",		0x7c0000e0, 0xffe007ff,	WR_1|RD_2,		0,		AL,		0,	0 },
 {"xor",			"d,v,t",	0x00000026, 0xfc0007ff,	WR_1|RD_2|RD_3,		0,		I1,		0,	0 },
 {"xor",			"t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"xor",			"D,S,T",	0x47800002, 0xffe0003f,	WR_1|RD_2|RD_3|FP_D,	0,		IL2E,		0,	0 },
@@ -2137,6 +2144,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addu_s.ob",		"d,s,t",	0x7c000114, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		0,		D64,	0 },
 {"addu_s.qb",		"d,s,t",	0x7c000110, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		0,		D32,	0 },
 {"addwc",		"d,s,t",	0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		0,		D32,	0 },
+{"bitrev",		"d,w",		0x7c000520, 0xffe007ff, WR_1|RD_2,		0,		AL,		0,	0 },
 {"bitrev",		"d,t",		0x7c0006d2, 0xffe007ff, WR_1|RD_2,		0,		0,		D32,	0 },
 {"bposge32",		"p",		0x041c0000, 0xffff0000, CBD,			0,		0,		D32,	0 },
 {"bposge32c",		"p",		0x04180000, 0xffff0000, NODS,			FS,		0,		D34,	0 },
@@ -3387,11 +3395,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfhc2",		"t,G",		0x48600000, 0xffe007ff,	WR_1|RD_C2|LC,		0,		I33,		0,	IOCT|IOCTP|IOCT2 },
 {"mfhc2",		"t,G,H",	0x48600000, 0xffe007f8,	WR_1|RD_C2|LC,		0,		I33,		0,	IOCT|IOCTP|IOCT2 },
 {"mfhc2",		"t,i",		0x48600000, 0xffe00000,	WR_1|RD_C2|LC,		0,		I33,		0,	IOCT|IOCTP|IOCT2 },
+{"mfic",		"t,G",		0x70000024, 0xffe007ff, WR_1|RD_C0|LC,		0,		AL,		0,	0 },
 {"mtc2",		"t,G",		0x48800000, 0xffe007ff,	RD_1|WR_C2|WR_CC|CM,	0,		I1,		0,	N54|IOCT|IOCTP|IOCT2|EE },
 {"mtc2",		"t,G,H",	0x48800000, 0xffe007f8,	RD_1|WR_C2|WR_CC|CM,	0,		I32,		0,	IOCT|IOCTP|IOCT2 },
 {"mthc2",		"t,G",		0x48e00000, 0xffe007ff,	RD_1|WR_C2|WR_CC|CM,	0,		I33,		0,	IOCT|IOCTP|IOCT2 },
 {"mthc2",		"t,G,H",	0x48e00000, 0xffe007f8,	RD_1|WR_C2|WR_CC|CM,	0,		I33,		0,	IOCT|IOCTP|IOCT2 },
 {"mthc2",		"t,i",		0x48e00000, 0xffe00000,	RD_1|WR_C2|WR_CC|CM,	0,		I33,		0,	IOCT|IOCTP|IOCT2 },
+{"mtic",		"t,G",		0x70000026, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,	0,		AL,		0,	0 },
 {"qmfc2",		"t,+6",		0x48200000, 0xffe007ff, WR_1|RD_C2,		0,		EE,		0,	0 },
 {"qmfc2.i",		"t,+6",		0x48200001, 0xffe007ff,	WR_1|RD_C2,		0,		EE,		0,	0 },
 {"qmfc2.ni",		"t,+6",		0x48200000, 0xffe007ff,	WR_1|RD_C2,		0,		EE,		0,	0 },
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index f4137c5640..ae1620dc35 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1644,6 +1644,8 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "r5900-all-vu0"
     run_list_test "r5900-error-vu0" "-march=r5900"
 
+    run_dump_test "allegrex"
+
     run_list_test_arches "ext-ill"	[mips_arch_list_matching mips64r2]
 
     run_list_test "ase-errors-1" "-mabi=32 -march=mips1" "ASE errors (1)"
diff --git a/gas/testsuite/gas/mips/allegrex.s b/gas/testsuite/gas/mips/allegrex.s
new file mode 100644
index 0000000000..c36745882d
--- /dev/null
+++ b/gas/testsuite/gas/mips/allegrex.s
@@ -0,0 +1,47 @@
+	.text
+	.set noreorder
+
+	ext	$4, $5, 6, 8
+	ins	$4, $5, 6, 8
+	seb	$7
+	seb	$8, $10
+	seh	$7
+	seh	$8, $10
+	movz	$2, $3, $4
+	movn	$2, $3, $4
+	wsbh	$7
+	wsbh	$8, $10
+	wsbw	$7
+	wsbw	$8, $10
+	bitrev	$7
+	bitrev	$8, $10
+	clo	$5, $2
+	clz	$3, $4
+	madd	$8, $9
+	maddu	$8, $9
+	msub	$8, $9
+	msubu	$8, $9
+	min	$7, $8, $9
+	max	$7, $8, $9
+	rotl	$25, $10, 4
+	rotr	$25, $10, 4
+	rotl	$25, $10, $4
+	rotr	$25, $10, $4
+	rotrv	$25, $10, $4
+	mtic	$v0, $0
+	mtic	$zero, $0
+	mfic	$v0, $0
+	mfic	$t0, $0
+	cache	0x18, 4($a0)
+	cache	0x1a, 8($sp)
+	cache	0x8, 32760($sp)
+	cache	0x4, -32760($sp)
+	mtdr	$v0, $0
+	mfdr	$v0, $0
+	mfdr	$v0, $1
+	mtdr	$v1, $1
+	dret
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	4, 0
+	.space	16
diff --git a/gas/testsuite/gas/mips/allegrex.d b/gas/testsuite/gas/mips/allegrex.d
new file mode 100644
index 0000000000..d0f79671de
--- /dev/null
+++ b/gas/testsuite/gas/mips/allegrex.d
@@ -0,0 +1,50 @@
+#as: -march=allegrex -mabi=32
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: Sony Allegrex CPU tests
+
+.*:     file format .*
+
+
+Disassembly of section .text:
+0x00000000 7ca43980 	ext	\$4,\$5,0x6,0x8
+0x00000004 7ca46984 	ins	\$4,\$5,0x6,0x8
+0x00000008 7c073c20 	seb	\$7,\$7
+0x0000000c 7c0a4420 	seb	\$8,\$10
+0x00000010 7c073e20 	seh	\$7,\$7
+0x00000014 7c0a4620 	seh	\$8,\$10
+0x00000018 0064100a 	movz	\$2,\$3,\$4
+0x0000001c 0064100b 	movn	\$2,\$3,\$4
+0x00000020 7c0738a0 	wsbh	\$7,\$7
+0x00000024 7c0a40a0 	wsbh	\$8,\$10
+0x00000028 7c0738e0 	wsbw	\$7,\$7
+0x0000002c 7c0a40e0 	wsbw	\$8,\$10
+0x00000030 7c073d20 	bitrev	\$7,\$7
+0x00000034 7c0a4520 	bitrev	\$8,\$10
+0x00000038 00402817 	clo	\$5,\$2
+0x0000003c 00801816 	clz	\$3,\$4
+0x00000040 0109001c 	madd	\$8,\$9
+0x00000044 0109001d 	maddu	\$8,\$9
+0x00000048 0109002e 	msub	\$8,\$9
+0x0000004c 0109002f 	msubu	\$8,\$9
+0x00000050 0109382d 	min	\$7,\$8,\$9
+0x00000054 0109382c 	max	\$7,\$8,\$9
+0x00000058 002acf02 	ror	\$25,\$10,0x1c
+0x0000005c 002ac902 	ror	\$25,\$10,0x4
+0x00000060 0004c823 	negu	\$25,\$4
+0x00000064 032ac846 	rorv	\$25,\$10,\$25
+0x00000068 008ac846 	rorv	\$25,\$10,\$4
+0x0000006c 008ac846 	rorv	\$25,\$10,\$4
+0x00000070 70020026 	mtic	\$2,\$0
+0x00000074 70000026 	mtic	\$0,\$0
+0x00000078 70020024 	mfic	\$2,\$0
+0x0000007c 70080024 	mfic	\$8,\$0
+0x00000080 bc980004 	cache	0x18,4\(\$4\)
+0x00000084 bfba0008 	cache	0x1a,8\(\$29\)
+0x00000088 bfa87ff8 	cache	0x8,32760\(\$29\)
+0x0000008c bfa48008 	cache	0x4,-32760\(\$29\)
+0x00000090 7082003d 	mtdr	\$2,\$0
+0x00000094 7002003d 	mfdr	\$2,\$0
+0x00000098 7002083d 	mfdr	\$2,\$1
+0x0000009c 7083083d 	mtdr	\$3,\$1
+0x000000a0 7000003e 	dret
+	\.\.\.
