@@ -526,7 +526,7 @@ static int mips_32bitmode = 0;
#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
/* True if CPU has a ror instruction. */
-#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
+#define CPU_HAS_ROR(CPU) (CPU_HAS_DROR (CPU) || (CPU) == CPU_ALLEGREX)
/* True if CPU is in the Octeon family. */
#define CPU_IS_OCTEON(CPU) ((CPU) == CPU_OCTEON || (CPU) == CPU_OCTEONP \
@@ -1810,13 +1810,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 },
{"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1, 0, 0 },
{"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1, 0, 0 },
-{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33, SMT, 0 },
-{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33, SMT, 0 },
-{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33, SMT, 0 },
-{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33, SMT, 0 },
-{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33, SMT, 0 },
-{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33, SMT, 0 },
-{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33, SMT, 0 },
+{"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_1|RD_2, 0, N5|I33|AL, SMT, 0 },
+{"rorv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, N5|I33|AL, SMT, 0 },
+{"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|AL, SMT, 0 },
+{"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|AL, SMT, 0 },
+{"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|AL, SMT, 0 },
+{"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|AL, SMT, 0 },
+{"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I33|AL, SMT, 0 },
{"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 },
{"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I3_33, 0, 0 },
{"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF },
@@ -517,7 +517,7 @@ mips_arch_create r3000 32 mips1 {} \
mips_arch_create r3900 32 mips1 { gpr_ilocks } \
{ -march=r3900 -mtune=r3900 } { -mmips:3900 } \
{ mipstx39-*-* mipstx39el-*-* }
-mips_arch_create allegrex 32 mips2 { oddspreg singlefloat } \
+mips_arch_create allegrex 32 mips2 { oddspreg ror singlefloat } \
{ -march=allegrex -mtune=allegrex } \
{ -mmips:allegrex }
mips_arch_create r4000 64 mips3 {} \