diff mbox series

[2/2] RISC-V: Add Zcb extension testcases.

Message ID 20230613133851.786238-2-jiawei@iscas.ac.cn
State Unresolved
Headers
Series [1/2] RISC-V: Add Zcb extension supports. |

Checks

Context Check Description
snail/binutils-gdb-check warning Git am fail log

Commit Message

Jiawei June 13, 2023, 1:38 p.m. UTC 
  Add all zcb instructions testcases. Fail testcases check missing depend
extensions cases.

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

gas/ChangeLog:

        * testsuite/gas/riscv/zc-zcb-fail-arch-0.d: New test.
        * testsuite/gas/riscv/zc-zcb-fail-arch-0.l: New test.
        * testsuite/gas/riscv/zc-zcb-fail-arch-0.s: New test.
        * testsuite/gas/riscv/zc-zcb-fail-arch-1.d: New test.
        * testsuite/gas/riscv/zc-zcb-fail-arch-1.l: New test.
        * testsuite/gas/riscv/zc-zcb-fail-arch-1.s: New test.
        * testsuite/gas/riscv/zc-zcb-fail-operand-0.d: New test.
        * testsuite/gas/riscv/zc-zcb-fail-operand-0.l: New test.
        * testsuite/gas/riscv/zc-zcb-fail-operand-0.s: New test.
        * testsuite/gas/riscv/zc-zcb-fail-operand-1.d: New test.
        * testsuite/gas/riscv/zc-zcb-fail-operand-1.l: New test.
        * testsuite/gas/riscv/zc-zcb-fail-operand-1.s: New test.
        * testsuite/gas/riscv/zc-zcb-fail-xlen.d: New test.
        * testsuite/gas/riscv/zc-zcb-fail-xlen.l: New test.
        * testsuite/gas/riscv/zc-zcb-fail-xlen.s: New test.
        * testsuite/gas/riscv/zc-zcb-lbu.d: New test.
        * testsuite/gas/riscv/zc-zcb-lbu.s: New test.
        * testsuite/gas/riscv/zc-zcb-lh.d: New test.
        * testsuite/gas/riscv/zc-zcb-lh.s: New test.
        * testsuite/gas/riscv/zc-zcb-lhu.d: New test.
        * testsuite/gas/riscv/zc-zcb-lhu.s: New test.
        * testsuite/gas/riscv/zc-zcb-mul.d: New test.
        * testsuite/gas/riscv/zc-zcb-mul.s: New test.
        * testsuite/gas/riscv/zc-zcb-not.d: New test.
        * testsuite/gas/riscv/zc-zcb-not.s: New test.
        * testsuite/gas/riscv/zc-zcb-sb.d: New test.
        * testsuite/gas/riscv/zc-zcb-sb.s: New test.
        * testsuite/gas/riscv/zc-zcb-sext-b.s: New test.
        * testsuite/gas/riscv/zc-zcb-sext-h.s: New test.
        * testsuite/gas/riscv/zc-zcb-sextw.d: New test.
        * testsuite/gas/riscv/zc-zcb-sextw.s: New test.
        * testsuite/gas/riscv/zc-zcb-sh.d: New test.
        * testsuite/gas/riscv/zc-zcb-sh.s: New test.
        * testsuite/gas/riscv/zc-zcb-test-arch-gc.d: New test.
        * testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d: New test.
        * testsuite/gas/riscv/zc-zcb-test-arch.s: New test.
        * testsuite/gas/riscv/zc-zcb-test-operand-0.d: New test.
        * testsuite/gas/riscv/zc-zcb-test-operand-0.s: New test.
        * testsuite/gas/riscv/zc-zcb-test-operand-1.d: New test.
        * testsuite/gas/riscv/zc-zcb-test-operand-1.s: New test.
        * testsuite/gas/riscv/zc-zcb-test-operand-2.d: New test.
        * testsuite/gas/riscv/zc-zcb-test-operand-2.s: New test.
        * testsuite/gas/riscv/zc-zcb-zext-b.d: New test.
        * testsuite/gas/riscv/zc-zcb-zext-b.s: New test.
        * testsuite/gas/riscv/zc-zcb-zext-h.d: New test.
        * testsuite/gas/riscv/zc-zcb-zext-h.s: New test.
        * testsuite/gas/riscv/zc-zcb-zextw.d: New test.
        * testsuite/gas/riscv/zc-zcb-zextw.s: New test.

---
 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d  |  3 ++
 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l  |  9 +++++
 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s  | 10 ++++++
 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d  |  3 ++
 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l  |  6 ++++
 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s  | 17 +++++++++
 .../gas/riscv/zc-zcb-fail-operand-0.d         |  3 ++
 .../gas/riscv/zc-zcb-fail-operand-0.l         | 13 +++++++
 .../gas/riscv/zc-zcb-fail-operand-0.s         | 17 +++++++++
 .../gas/riscv/zc-zcb-fail-operand-1.d         |  3 ++
 .../gas/riscv/zc-zcb-fail-operand-1.l         | 11 ++++++
 .../gas/riscv/zc-zcb-fail-operand-1.s         | 14 ++++++++
 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d    |  3 ++
 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l    |  4 +++
 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s    |  5 +++
 gas/testsuite/gas/riscv/zc-zcb-lbu.d          | 26 ++++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-lbu.s          | 22 ++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-lh.d           | 26 ++++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-lh.s           | 22 ++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-lhu.d          | 26 ++++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-lhu.s          | 22 ++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-mul.d          | 21 +++++++++++
 gas/testsuite/gas/riscv/zc-zcb-mul.s          | 19 ++++++++++
 gas/testsuite/gas/riscv/zc-zcb-not.d          | 21 +++++++++++
 gas/testsuite/gas/riscv/zc-zcb-not.s          | 19 ++++++++++
 gas/testsuite/gas/riscv/zc-zcb-sb.d           | 26 ++++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-sb.s           | 22 ++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-sext-b.s       | 14 ++++++++
 gas/testsuite/gas/riscv/zc-zcb-sext-h.s       | 14 ++++++++
 gas/testsuite/gas/riscv/zc-zcb-sextw.d        | 18 ++++++++++
 gas/testsuite/gas/riscv/zc-zcb-sextw.s        | 13 +++++++
 gas/testsuite/gas/riscv/zc-zcb-sh.d           | 26 ++++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-sh.s           | 22 ++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d | 28 +++++++++++++++
 .../gas/riscv/zc-zcb-test-arch-no-zcb.d       | 28 +++++++++++++++
 gas/testsuite/gas/riscv/zc-zcb-test-arch.s    | 22 ++++++++++++
 .../gas/riscv/zc-zcb-test-operand-0.d         | 36 +++++++++++++++++++
 .../gas/riscv/zc-zcb-test-operand-0.s         | 32 +++++++++++++++++
 .../gas/riscv/zc-zcb-test-operand-1.d         | 18 ++++++++++
 .../gas/riscv/zc-zcb-test-operand-1.s         | 11 ++++++
 .../gas/riscv/zc-zcb-test-operand-2.d         | 28 +++++++++++++++
 .../gas/riscv/zc-zcb-test-operand-2.s         | 21 +++++++++++
 gas/testsuite/gas/riscv/zc-zcb-zext-b.d       | 20 +++++++++++
 gas/testsuite/gas/riscv/zc-zcb-zext-b.s       | 14 ++++++++
 gas/testsuite/gas/riscv/zc-zcb-zext-h.d       | 20 +++++++++++
 gas/testsuite/gas/riscv/zc-zcb-zext-h.s       | 14 ++++++++
 gas/testsuite/gas/riscv/zc-zcb-zextw.d        | 20 +++++++++++
 gas/testsuite/gas/riscv/zc-zcb-zextw.s        | 16 +++++++++
 48 files changed, 828 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.l
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.l
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lbu.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lbu.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lh.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lh.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lhu.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-lhu.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-mul.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-mul.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-not.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-not.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sb.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sb.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sext-b.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sext-h.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sextw.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sextw.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sh.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-sh.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-arch.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-0.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-0.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-1.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-1.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-2.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-test-operand-2.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zext-b.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zext-b.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zext-h.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zext-h.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zextw.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcb-zextw.s

Comments

Jan Beulich June 13, 2023, 2:28 p.m. UTC | #1 
On 13.06.2023 15:38, Jiawei wrote:
> Add all zcb instructions testcases. Fail testcases check missing depend
> extensions cases.
> 
> Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
> Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
> Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
> Co-Authored by: Simon Cook <simon.cook@embecosm.com>
> Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
> Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
> 
> gas/ChangeLog:
> 
>         * testsuite/gas/riscv/zc-zcb-fail-arch-0.d: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-arch-0.l: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-arch-0.s: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-arch-1.d: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-arch-1.l: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-arch-1.s: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-operand-0.d: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-operand-0.l: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-operand-0.s: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-operand-1.d: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-operand-1.l: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-operand-1.s: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-xlen.d: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-xlen.l: New test.
>         * testsuite/gas/riscv/zc-zcb-fail-xlen.s: New test.
>         * testsuite/gas/riscv/zc-zcb-lbu.d: New test.
>         * testsuite/gas/riscv/zc-zcb-lbu.s: New test.
>         * testsuite/gas/riscv/zc-zcb-lh.d: New test.
>         * testsuite/gas/riscv/zc-zcb-lh.s: New test.
>         * testsuite/gas/riscv/zc-zcb-lhu.d: New test.
>         * testsuite/gas/riscv/zc-zcb-lhu.s: New test.
>         * testsuite/gas/riscv/zc-zcb-mul.d: New test.
>         * testsuite/gas/riscv/zc-zcb-mul.s: New test.
>         * testsuite/gas/riscv/zc-zcb-not.d: New test.
>         * testsuite/gas/riscv/zc-zcb-not.s: New test.
>         * testsuite/gas/riscv/zc-zcb-sb.d: New test.
>         * testsuite/gas/riscv/zc-zcb-sb.s: New test.
>         * testsuite/gas/riscv/zc-zcb-sext-b.s: New test.
>         * testsuite/gas/riscv/zc-zcb-sext-h.s: New test.
>         * testsuite/gas/riscv/zc-zcb-sextw.d: New test.
>         * testsuite/gas/riscv/zc-zcb-sextw.s: New test.
>         * testsuite/gas/riscv/zc-zcb-sh.d: New test.
>         * testsuite/gas/riscv/zc-zcb-sh.s: New test.
>         * testsuite/gas/riscv/zc-zcb-test-arch-gc.d: New test.
>         * testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d: New test.
>         * testsuite/gas/riscv/zc-zcb-test-arch.s: New test.
>         * testsuite/gas/riscv/zc-zcb-test-operand-0.d: New test.
>         * testsuite/gas/riscv/zc-zcb-test-operand-0.s: New test.
>         * testsuite/gas/riscv/zc-zcb-test-operand-1.d: New test.
>         * testsuite/gas/riscv/zc-zcb-test-operand-1.s: New test.
>         * testsuite/gas/riscv/zc-zcb-test-operand-2.d: New test.
>         * testsuite/gas/riscv/zc-zcb-test-operand-2.s: New test.
>         * testsuite/gas/riscv/zc-zcb-zext-b.d: New test.
>         * testsuite/gas/riscv/zc-zcb-zext-b.s: New test.
>         * testsuite/gas/riscv/zc-zcb-zext-h.d: New test.
>         * testsuite/gas/riscv/zc-zcb-zext-h.s: New test.
>         * testsuite/gas/riscv/zc-zcb-zextw.d: New test.
>         * testsuite/gas/riscv/zc-zcb-zextw.s: New test.

While I'm not a RISC-V maintainer, I still wonder about the overhead
of having a single test per insn (rather than e.g. per feature or
relevant combination of features): In my experience many small tests
consume more time (and space) when running the testsuite than fewer
larger ones. (This remark would then also apply to the earlier series
consisting of just testsuite additions.)

Jan
Jiawei June 13, 2023, 2:55 p.m. UTC | #2 
&gt; -----原始邮件-----
&gt; 发件人: "Jan Beulich" <jbeulich@suse.com>
&gt; 发送时间: 2023-06-13 22:28:38 (星期二)
&gt; 收件人: Jiawei <jiawei@iscas.ac.cn>
&gt; 抄送: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com, gaofei@eswincomputing.com, sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, binutils@sourceware.org
&gt; 主题: Re: [PATCH 2/2] RISC-V: Add Zcb extension testcases.
&gt; 
&gt; On 13.06.2023 15:38, Jiawei wrote:
&gt; &gt; Add all zcb instructions testcases. Fail testcases check missing depend
&gt; &gt; extensions cases.
&gt; &gt; 
&gt; &gt; Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
&gt; &gt; Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
&gt; &gt; Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
&gt; &gt; Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
&gt; &gt; Co-Authored by: Simon Cook <simon.cook@embecosm.com>
&gt; &gt; Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
&gt; &gt; Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
&gt; &gt; 
&gt; &gt; gas/ChangeLog:
&gt; &gt; 
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-0.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-0.l: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-0.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-1.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-1.l: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-1.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-0.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-0.l: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-0.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-1.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-1.l: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-1.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-xlen.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-xlen.l: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-xlen.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-lbu.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-lbu.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-lh.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-lh.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-lhu.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-lhu.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-mul.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-mul.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-not.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-not.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-sb.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-sb.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-sext-b.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-sext-h.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-sextw.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-sextw.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-sh.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-sh.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-arch-gc.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-arch.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-0.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-0.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-1.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-1.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-2.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-2.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-zext-b.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-zext-b.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-zext-h.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-zext-h.s: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-zextw.d: New test.
&gt; &gt;         * testsuite/gas/riscv/zc-zcb-zextw.s: New test.
&gt; 
&gt; While I'm not a RISC-V maintainer, I still wonder about the overhead
&gt; of having a single test per insn (rather than e.g. per feature or
&gt; relevant combination of features): In my experience many small tests
&gt; consume more time (and space) when running the testsuite than fewer
&gt; larger ones. (This remark would then also apply to the earlier series
&gt; consisting of just testsuite additions.)
&gt; 
&gt; Jan

We run these tests on dejagnu, they only do some regex matching, and 
used to ensure correct generation of instruction opcode, and to handle
some wrong dependency cases error log.

We not stats yet on their performance overhead yet, but they still run
pretty fast with dejagnu currently. Do we need to stat it?

BR,
Jiawei</yulong@iscas.ac.cn></shihua@iscas.ac.cn></simon.cook@embecosm.com></sinan.lin@linux.alibaba.com></nandni.jamnadas@embecosm.com></mary.bennett@embecosm.com></charlie.keaney@embecosm.com></jiawei@iscas.ac.cn></jbeulich@suse.com>
Jan Beulich June 13, 2023, 2:59 p.m. UTC | #3 
On 13.06.2023 16:55, jiawei@iscas.ac.cn wrote:
> &gt; -----原始邮件-----
> &gt; 发件人: "Jan Beulich" <jbeulich@suse.com>
> &gt; 发送时间: 2023-06-13 22:28:38 (星期二)
> &gt; 收件人: Jiawei <jiawei@iscas.ac.cn>
> &gt; 抄送: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, mary.bennett@embecosm.com, nandni.jamnadas@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, tariq.kurd@codasip.com, ibrahim.abu.kharmeh1@huawei.com, gaofei@eswincomputing.com, sinan.lin@linux.alibaba.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, binutils@sourceware.org
> &gt; 主题: Re: [PATCH 2/2] RISC-V: Add Zcb extension testcases.
> &gt; 
> &gt; On 13.06.2023 15:38, Jiawei wrote:
> &gt; &gt; Add all zcb instructions testcases. Fail testcases check missing depend
> &gt; &gt; extensions cases.
> &gt; &gt; 
> &gt; &gt; Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
> &gt; &gt; Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
> &gt; &gt; Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
> &gt; &gt; Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
> &gt; &gt; Co-Authored by: Simon Cook <simon.cook@embecosm.com>
> &gt; &gt; Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
> &gt; &gt; Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>
> &gt; &gt; 
> &gt; &gt; gas/ChangeLog:
> &gt; &gt; 
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-0.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-0.l: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-0.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-1.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-1.l: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-arch-1.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-0.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-0.l: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-0.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-1.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-1.l: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-operand-1.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-xlen.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-xlen.l: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-fail-xlen.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-lbu.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-lbu.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-lh.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-lh.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-lhu.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-lhu.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-mul.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-mul.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-not.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-not.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-sb.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-sb.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-sext-b.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-sext-h.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-sextw.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-sextw.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-sh.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-sh.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-arch-gc.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-arch.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-0.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-0.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-1.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-1.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-2.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-test-operand-2.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-zext-b.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-zext-b.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-zext-h.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-zext-h.s: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-zextw.d: New test.
> &gt; &gt;         * testsuite/gas/riscv/zc-zcb-zextw.s: New test.
> &gt; 
> &gt; While I'm not a RISC-V maintainer, I still wonder about the overhead
> &gt; of having a single test per insn (rather than e.g. per feature or
> &gt; relevant combination of features): In my experience many small tests
> &gt; consume more time (and space) when running the testsuite than fewer
> &gt; larger ones. (This remark would then also apply to the earlier series
> &gt; consisting of just testsuite additions.)
> &gt; 
> &gt; Jan
> 
> We run these tests on dejagnu, they only do some regex matching, and 
> used to ensure correct generation of instruction opcode, and to handle
> some wrong dependency cases error log.
> 
> We not stats yet on their performance overhead yet, but they still run
> pretty fast with dejagnu currently. Do we need to stat it?

Not sure, but you want to keep the scalability aspect in mind: For the
handful of insns here this is likely fine, but what if every insn now
and in the future had its own testcase(s)?

Jan
diff mbox series

Patch

diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d
new file mode 100644
index 00000000000..a5f6a1eb5cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv64g_zca_zba_zbb
+#source: zc-zcb-fail-arch-0.s
+#error_output: zc-zcb-fail-arch-0.l
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l
new file mode 100644
index 00000000000..010186461c5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.l
@@ -0,0 +1,9 @@ 
+.*: Assembler messages:
+.*: Error: unrecognized opcode `c.mul a0,a1', extension `zcb' and `zmmul', or `zcb' and `m' required
+.*: Error: unrecognized opcode `c.sext.b a0', extension `zcb' and `zbb' required
+.*: Error: unrecognized opcode `c.sext.h a0', extension `zcb' and `zbb' required
+.*: Error: unrecognized opcode `c.zext.h a0', extension `zcb' and `zbb' required
+.*: Error: unrecognized opcode `c.zext.w a0', extension `zcb' and `zba' required
+.*: Error: unrecognized opcode `c.zext.b a0', extension `zcb' required
+.*: Error: unrecognized opcode `c.sext.w a0', extension `zcb' required
+.*: Error: unrecognized opcode `c.not a1', extension `zcb' required
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s
new file mode 100644
index 00000000000..eecb58b9835
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-0.s
@@ -0,0 +1,10 @@ 
+# test cases when zcb arch string is missing
+zcb:
+	c.mul a0,a1
+	c.sext.b a0
+	c.sext.h a0
+	c.zext.h a0
+	c.zext.w a0
+	c.zext.b a0
+	c.sext.w a0
+	c.not a1
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d
new file mode 100644
index 00000000000..47bb55270f5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv64i_zca_zcb
+#source: zc-zcb-fail-operand-1.s
+#error_output: zc-zcb-fail-operand-1.l
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l
new file mode 100644
index 00000000000..2fddd66c362
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.l
@@ -0,0 +1,6 @@ 
+.*: Assembler messages:
+.*: Error: unrecognized opcode `c.mul a0,a1'
+.*: Error: unrecognized opcode `c.sext.b a0'
+.*: Error: unrecognized opcode `c.sext.h a0'
+.*: Error: unrecognized opcode `c.zext.h a0'
+.*: Error: unrecognized opcode `c.zext.w a0'
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s
new file mode 100644
index 00000000000..bbe76c240a8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-arch-1.s
@@ -0,0 +1,17 @@ 
+# test missing prerequisites cases
+zcb:
+	# prerequisites of c.mul: M ext
+	c.mul a0,a1
+
+	# prerequisites of c.sext.b, c.sext.h, c.zext.h: ZBB ext
+	c.sext.b a0
+	c.sext.h a0
+	c.zext.h a0
+
+	# prerequisites of c.zext.w: ZBA ext
+	c.zext.w a0
+
+	# c.zext.b, c.sext.w and c.not have no prerequisites
+	c.zext.b a0
+	c.sext.w a0
+	c.not a1
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.d b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.d
new file mode 100644
index 00000000000..0a473c47590
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-fail-operand-0.s
+#error_output: zc-zcb-fail-operand-0.l
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.l b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.l
new file mode 100644
index 00000000000..dd62dab08ba
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.l
@@ -0,0 +1,13 @@ 
+.*: Assembler messages:
+.*: Error: illegal operands `c.sb x9,5\(x9\)'
+.*: Error: illegal operands `c.lbu x15,-1\(x15\)'
+.*: Error: illegal operands `c.lbu x8,8\(x8\)'
+.*: Error: illegal operands `c.sb x9,-2\(x9\)'
+.*: Error: illegal operands `c.lbu x12,8\(x12\)'
+.*: Error: illegal operands `c.sb x12,x0\(x12\)'
+.*: Error: illegal operands `c.sh x9,4\(x9\)'
+.*: Error: illegal operands `c.sh x15,-4\(x15\)'
+.*: Error: illegal operands `c.lh x8,1\(x8\)'
+.*: Error: illegal operands `c.lh x9,-2\(x9\)'
+.*: Error: illegal operands `c.lhu x12,8\(x12\)'
+.*: Error: illegal operands `c.lhu x12,x2\(x12\)'
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.s b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.s
new file mode 100644
index 00000000000..6831325cccc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-0.s
@@ -0,0 +1,17 @@ 
+# test imm operands of load and save instructions in zcb
+target:
+	# the valid immediate operand of c.sb, c.lbu is 2-bit unsigned immediate from 0 to 3.
+	c.sb x9,5(x9)
+	c.lbu x15,-1(x15)
+	c.lbu x8,8(x8)
+	c.sb x9,-2(x9)
+	c.lbu x12,8(x12)
+	c.sb x12,x0(x12)
+
+	# the valid immediate operand of c.sh, c.lhu and c.lh is 0 or 2.
+	c.sh x9,4(x9)
+	c.sh x15,-4(x15)
+	c.lh x8,1(x8)
+	c.lh x9,-2(x9)
+	c.lhu x12,8(x12)
+	c.lhu x12,x2(x12)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.d b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.d
new file mode 100644
index 00000000000..8a3c482e963
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-fail-operand-1.s
+#error_output: zc-zcb-fail-operand-1.l
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.l b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.l
new file mode 100644
index 00000000000..0a725be1d56
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.l
@@ -0,0 +1,11 @@ 
+.*: Assembler messages:
+.*: Error: illegal operands `c.sb x7,1\(x9\)'
+.*: Error: illegal operands `c.sb x17,1\(x17\)'
+.*: Error: illegal operands `c.sh x7,4\(x7\)'
+.*: Error: illegal operands `c.sh x19,4\(x16\)'
+.*: Error: illegal operands `c.lbu x7,1\(x10\)'
+.*: Error: illegal operands `c.lbu x16,1\(x16\)'
+.*: Error: illegal operands `c.lh x7,4\(x10\)'
+.*: Error: illegal operands `c.lh x16,4\(x16\)'
+.*: Error: illegal operands `c.lhu x7,4\(x15\)'
+.*: Error: illegal operands `c.lhu x15,4\(x16\)'
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.s b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.s
new file mode 100644
index 00000000000..e4d92b7fc8f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-operand-1.s
@@ -0,0 +1,14 @@ 
+# the register operand of load and save instructions in ZCB
+# requires the destination register is the source register and
+# the register is ranged from x8 to x15
+target:
+	c.sb x7,1(x9)
+	c.sb x17,1(x17)
+	c.sh x7,4(x7)
+	c.sh x19,4(x16)
+	c.lbu x7,1(x10)
+	c.lbu x16,1(x16)
+	c.lh x7,4(x10)
+	c.lh x16,4(x16)
+	c.lhu x7,4(x15)
+	c.lhu x15,4(x16)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d
new file mode 100644
index 00000000000..d2c0a2cab0b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-fail-xlen.s
+#error_output: zc-zcb-fail-xlen.l
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l
new file mode 100644
index 00000000000..7cb91231fe1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.l
@@ -0,0 +1,4 @@ 
+.*: Assembler messages:
+.*: Error: unrecognized opcode `c.zext.w x8'
+.*: Error: unrecognized opcode `c.zext.w x11'
+.*: Error: unrecognized opcode `c.sext.w x11'
diff --git a/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s
new file mode 100644
index 00000000000..52cb9628a80
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-fail-xlen.s
@@ -0,0 +1,5 @@ 
+# c.zext.w and c.sext.w are only in rv64
+target:
+	c.zext.w x8
+	c.zext.w x11
+	c.sext.w x11
diff --git a/gas/testsuite/gas/riscv/zc-zcb-lbu.d b/gas/testsuite/gas/riscv/zc-zcb-lbu.d
new file mode 100644
index 00000000000..f65984eb2db
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-lbu.d
@@ -0,0 +1,26 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-lbu.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb_lbu>:
+[	 ]*[0-9a-f]+:[	 ]+8120[	 ]+c.lbu[	 ]+s0,2\(a0\)
+[	 ]*[0-9a-f]+:[	 ]+825c[	 ]+c.lbu[	 ]+a5,1\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+80e0[	 ]+c.lbu[	 ]+s0,3\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+8024[	 ]+c.lbu[	 ]+s1,2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8050[	 ]+c.lbu[	 ]+a2,1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+83f4[	 ]+c.lbu[	 ]+a3,3\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8398[	 ]+c.lbu[	 ]+a4,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8044[	 ]+c.lbu[	 ]+s1,1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+83bc[	 ]+c.lbu[  	 ]+a5,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8060[	 ]+c.lbu[  	 ]+s0,3\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+80dc[	 ]+c.lbu[  	 ]+a5,1\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+823c[	 ]+c.lbu[  	 ]+a5,2\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+83d4[	 ]+c.lbu[  	 ]+a3,1\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8398[	 ]+c.lbu[  	 ]+a4,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8380[	 ]+c.lbu[  	 ]+s0,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8004[	 ]+c.lbu[  	 ]+s1,0\(s0\)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-lbu.s b/gas/testsuite/gas/riscv/zc-zcb-lbu.s
new file mode 100644
index 00000000000..bec4d32fa45
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-lbu.s
@@ -0,0 +1,22 @@ 
+zcb_lbu:
+	# test to compress lbu
+	lbu x8,2(x10)
+	lbu x15,1(x12)
+	lbu x8,3(x9)
+	lbu x9,2(x8)
+	lbu x12,1(x8)
+	lbu x13,3(x15)
+	lbu x14,0(x15)
+
+	# test c.lbu
+	c.lbu x9,1(x8)
+	c.lbu x15,2(x15)
+	c.lbu x8,3(x8)
+	c.lbu x15,1(x9)
+	c.lbu x15,2(x12)
+	c.lbu x13,1(x15)
+	c.lbu x14,0(x15)
+
+	# implicit zero offset
+	c.lbu x8,(x15)
+	lbu x9,(x8)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-lh.d b/gas/testsuite/gas/riscv/zc-zcb-lh.d
new file mode 100644
index 00000000000..66bf0ea1338
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-lh.d
@@ -0,0 +1,26 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-lh.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb_lh>:
+[	 ]*[0-9a-f]+:[	 ]+8460[	 ]+c.lh[	 ]+s0,2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+87dc[	 ]+c.lh[	 ]+a5,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8760[	 ]+c.lh[	 ]+s0,2\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+86fc[	 ]+c.lh[	 ]+a5,2\(a3\)
+[	 ]*[0-9a-f]+:[	 ]+8644[	 ]+c.lh[	 ]+s1,0\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+87e0[	 ]+c.lh[	 ]+s0,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8750[	 ]+c.lh[	 ]+a2,0\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+8764[	 ]+c.lh[	 ]+s1,2\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+87ec[	 ]+c.lh[  	 ]+a1,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8440[	 ]+c.lh[  	 ]+s0,0\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+84c4[	 ]+c.lh[  	 ]+s1,0\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+8660[	 ]+c.lh[  	 ]+s0,2\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+87f4[	 ]+c.lh[  	 ]+a3,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8758[	 ]+c.lh[  	 ]+a4,0\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+844c[	 ]+c.lh[  	 ]+a1,0\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+87c4[	 ]+c.lh[  	 ]+s1,0\(a5\)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-lh.s b/gas/testsuite/gas/riscv/zc-zcb-lh.s
new file mode 100644
index 00000000000..63894cb8f39
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-lh.s
@@ -0,0 +1,22 @@ 
+zcb_lh:
+	# test to compress lh
+	lh x8,2(x8)
+	lh x15,0(x15)
+	lh x8,2(x14)
+	lh x15,2(x13)
+	lh x9,0(x12)
+	lh x8,2(x15)
+	lh x12,0(x14)
+
+	# test c.lh
+	c.lh x9,2(x14)
+	c.lh x11,2(x15)
+	c.lh x8,0(x8)
+	c.lh x9,0(x9)
+	c.lh x8,2(x12)
+	c.lh x13,2(x15)
+	c.lh x14,0(x14)
+
+	# implicit zero offset
+	c.lh x11,(x8)
+	lh x9,(x15)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-lhu.d b/gas/testsuite/gas/riscv/zc-zcb-lhu.d
new file mode 100644
index 00000000000..6716f42599e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-lhu.d
@@ -0,0 +1,26 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-lhu.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb_lhu>:
+[	 ]*[0-9a-f]+:[	 ]+8420[	 ]+c.lhu[	 ]+s0,2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+879c[	 ]+c.lhu[	 ]+a5,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8720[	 ]+c.lhu[	 ]+s0,2\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+86bc[	 ]+c.lhu[	 ]+a5,2\(a3\)
+[	 ]*[0-9a-f]+:[	 ]+8604[	 ]+c.lhu[	 ]+s1,0\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+87a0[	 ]+c.lhu[	 ]+s0,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8710[	 ]+c.lhu[	 ]+a2,0\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+8724[	 ]+c.lhu[	 ]+s1,2\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+87ac[	 ]+c.lhu[  	 ]+a1,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8400[	 ]+c.lhu[  	 ]+s0,0\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8484[	 ]+c.lhu[  	 ]+s1,0\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+8620[	 ]+c.lhu[  	 ]+s0,2\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+87b4[	 ]+c.lhu[  	 ]+a3,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8718[	 ]+c.lhu[  	 ]+a4,0\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+840c[	 ]+c.lhu[  	 ]+a1,0\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8784[	 ]+c.lhu[  	 ]+s1,0\(a5\)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-lhu.s b/gas/testsuite/gas/riscv/zc-zcb-lhu.s
new file mode 100644
index 00000000000..7a6c4e37312
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-lhu.s
@@ -0,0 +1,22 @@ 
+zcb_lhu:
+	# test to compress lhu
+	lhu x8,2(x8)
+	lhu x15,0(x15)
+	lhu x8,2(x14)
+	lhu x15,2(x13)
+	lhu x9,0(x12)
+	lhu x8,2(x15)
+	lhu x12,0(x14)
+
+	# test c.lhu
+	c.lhu x9,2(x14)
+	c.lhu x11,2(x15)
+	c.lhu x8,0(x8)
+	c.lhu x9,0(x9)
+	c.lhu x8,2(x12)
+	c.lhu x13,2(x15)
+	c.lhu x14,0(x14)
+
+	# implicit zero offset
+	c.lhu x11,(x8)
+	lhu x9,(x15)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-mul.d b/gas/testsuite/gas/riscv/zc-zcb-mul.d
new file mode 100644
index 00000000000..b1f1b305e72
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-mul.d
@@ -0,0 +1,21 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-mul.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb>:
+[	 ]*[0-9a-f]+:[	 ]+9fc1[	 ]+c.mul[  	 ]+a5,s0
+[	 ]*[0-9a-f]+:[	 ]+9c5d[	 ]+c.mul[  	 ]+s0,a5
+[	 ]*[0-9a-f]+:[	 ]+9cd1[	 ]+c.mul[  	 ]+s1,a2
+[	 ]*[0-9a-f]+:[	 ]+9d4d[	 ]+c.mul[  	 ]+a0,a1
+[	 ]*[0-9a-f]+:[	 ]+9dcd[	 ]+c.mul[  	 ]+a1,a1
+[	 ]*[0-9a-f]+:[	 ]+9f59[	 ]+c.mul[  	 ]+a4,a4
+[	 ]*[0-9a-f]+:[	 ]+9fdd[	 ]+c.mul[  	 ]+a5,a5
+[	 ]*[0-9a-f]+:[	 ]+9c41[	 ]+c.mul[  	 ]+s0,s0
+[	 ]*[0-9a-f]+:[	 ]+9cd1[	 ]+c.mul[  	 ]+s1,a2
+[	 ]*[0-9a-f]+:[	 ]+9dd5[	 ]+c.mul[  	 ]+a1,a3
+[	 ]*[0-9a-f]+:[	 ]+9e51[	 ]+c.mul[  	 ]+a2,a2
diff --git a/gas/testsuite/gas/riscv/zc-zcb-mul.s b/gas/testsuite/gas/riscv/zc-zcb-mul.s
new file mode 100644
index 00000000000..9299b2a5c16
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-mul.s
@@ -0,0 +1,19 @@ 
+zcb:
+	# test to compress mul insturctions(boundary)
+	mul x15,x15,x8
+	mul x8,x8,x15
+
+	# test to compress mul insturctions
+	mul x9,x9,x12
+	mul x10,x10,x11
+	mul x11,x11,x11
+	mul x14,x14,x14
+
+	# test c.mul(boundary)
+	c.mul x15,x15
+	c.mul x8,x8
+
+	# test c.mul
+	c.mul x9,x12
+	c.mul x11,x13
+    c.mul x12,x12
diff --git a/gas/testsuite/gas/riscv/zc-zcb-not.d b/gas/testsuite/gas/riscv/zc-zcb-not.d
new file mode 100644
index 00000000000..2ea31078b60
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-not.d
@@ -0,0 +1,21 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-not.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb>:
+[	 ]*[0-9a-f]+:[	 ]+9ff5[	 ]+c.not[	 ]+a5
+[	 ]*[0-9a-f]+:[	 ]+9c75[	 ]+c.not[	 ]+s0
+[	 ]*[0-9a-f]+:[	 ]+9cf5[	 ]+c.not[	 ]+s1
+[	 ]*[0-9a-f]+:[	 ]+9d75[	 ]+c.not[	 ]+a0
+[	 ]*[0-9a-f]+:[	 ]+9df5[	 ]+c.not[	 ]+a1
+[	 ]*[0-9a-f]+:[	 ]+9f75[	 ]+c.not[	 ]+a4
+[	 ]*[0-9a-f]+:[	 ]+9ff5[	 ]+c.not[	 ]+a5
+[	 ]*[0-9a-f]+:[	 ]+9c75[	 ]+c.not[	 ]+s0
+[	 ]*[0-9a-f]+:[	 ]+9cf5[	 ]+c.not[  	 ]+s1
+[	 ]*[0-9a-f]+:[	 ]+9df5[	 ]+c.not[  	 ]+a1
+[	 ]*[0-9a-f]+:[	 ]+9e75[	 ]+c.not[  	 ]+a2
diff --git a/gas/testsuite/gas/riscv/zc-zcb-not.s b/gas/testsuite/gas/riscv/zc-zcb-not.s
new file mode 100644
index 00000000000..77f88e70344
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-not.s
@@ -0,0 +1,19 @@ 
+zcb:
+	# test to compress not insturctions(boundary)
+	not x15,x15
+	not x8,x8
+
+	# test to compress not insturctions
+	not x9,x9
+	not x10,x10
+	not x11,x11
+	not x14,x14
+
+	# test c.not(boundary)
+	c.not x15
+	c.not x8
+
+	# test c.not
+	c.not x9
+	c.not x11
+    c.not x12
diff --git a/gas/testsuite/gas/riscv/zc-zcb-sb.d b/gas/testsuite/gas/riscv/zc-zcb-sb.d
new file mode 100644
index 00000000000..a309895c73e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-sb.d
@@ -0,0 +1,26 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-sb.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb_sb>:
+[	 ]*[0-9a-f]+:[	 ]+8920[	 ]+c.sb[	 ]+s0,2\(a0\)
+[	 ]*[0-9a-f]+:[	 ]+8a5c[	 ]+c.sb[	 ]+a5,1\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+88e0[	 ]+c.sb[	 ]+s0,3\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+8824[	 ]+c.sb[	 ]+s1,2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8850[	 ]+c.sb[	 ]+a2,1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8bf4[	 ]+c.sb[	 ]+a3,3\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8b98[	 ]+c.sb[	 ]+a4,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8844[	 ]+c.sb[	 ]+s1,1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8bbc[	 ]+c.sb[  	 ]+a5,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8860[	 ]+c.sb[  	 ]+s0,3\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+88dc[	 ]+c.sb[  	 ]+a5,1\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+8a3c[	 ]+c.sb[  	 ]+a5,2\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+8bd4[	 ]+c.sb[  	 ]+a3,1\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8b98[	 ]+c.sb[  	 ]+a4,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8b80[	 ]+c.sb[  	 ]+s0,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8804[	 ]+c.sb[  	 ]+s1,0\(s0\)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-sb.s b/gas/testsuite/gas/riscv/zc-zcb-sb.s
new file mode 100644
index 00000000000..75a9a9a8227
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-sb.s
@@ -0,0 +1,22 @@ 
+zcb_sb:
+	# test to compress sb
+	sb x8,2(x10)
+	sb x15,1(x12)
+	sb x8,3(x9)
+	sb x9,2(x8)
+	sb x12,1(x8)
+	sb x13,3(x15)
+	sb x14,0(x15)
+
+	# test c.sb
+	c.sb x9,1(x8)
+	c.sb x15,2(x15)
+	c.sb x8,3(x8)
+	c.sb x15,1(x9)
+	c.sb x15,2(x12)
+	c.sb x13,1(x15)
+	c.sb x14,0(x15)
+
+	# implicit zero offset
+	c.sb x8,(x15)
+	sb x9,(x8)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-sext-b.s b/gas/testsuite/gas/riscv/zc-zcb-sext-b.s
new file mode 100644
index 00000000000..9b0c04c0b2d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-sext-b.s
@@ -0,0 +1,14 @@ 
+zcb:
+	# test zcb sign/zero extension insturction
+	c.zext.h x8
+	c.zext.h x15
+	c.zext.h x10
+	c.zext.h x9
+	c.zext.h x12
+
+	# test to compress sign/zero extension insturctions
+	zext.h x8,x8
+	zext.h x15,x15
+	zext.h x9,x9
+	zext.h x12,x12
+	zext.h x14,x14
diff --git a/gas/testsuite/gas/riscv/zc-zcb-sext-h.s b/gas/testsuite/gas/riscv/zc-zcb-sext-h.s
new file mode 100644
index 00000000000..f33a7b673cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-sext-h.s
@@ -0,0 +1,14 @@ 
+zcb:
+	# test zcb sign/zero extension insturction
+	c.zext.b x8
+	c.zext.b x15
+	c.zext.b x10
+	c.zext.b x9
+	c.zext.b x12
+
+	# test to compress sign/zero extension insturctions
+	zext.b x8,x8
+	zext.b x15,x15
+	zext.b x9,x9
+	zext.b x12,x12
+	zext.b x14,x14
diff --git a/gas/testsuite/gas/riscv/zc-zcb-sextw.d b/gas/testsuite/gas/riscv/zc-zcb-sextw.d
new file mode 100644
index 00000000000..fb76ae49b82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-sextw.d
@@ -0,0 +1,18 @@ 
+#as: -march=rv64g_zca_zcb_zbb
+#source: zc-zcb-sextw.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb64>:
+[	 ]*[0-9a-f]+:[	 ]+2481[	 ]+c.addiw[	 ]+s1,0
+[	 ]*[0-9a-f]+:[	 ]+2081[	 ]+c.addiw[	 ]+ra,0
+[	 ]*[0-9a-f]+:[	 ]+2981[	 ]+c.addiw[	 ]+s3,0
+[	 ]*[0-9a-f]+:[	 ]+2701[	 ]+c.addiw[	 ]+a4,0
+[	 ]*[0-9a-f]+:[	 ]+2781[	 ]+c.addiw[	 ]+a5,0
+[	 ]*[0-9a-f]+:[	 ]+2401[	 ]+c.addiw[	 ]+s0,0
+[	 ]*[0-9a-f]+:[	 ]+2481[	 ]+c.addiw[	 ]+s1,0
+[	 ]*[0-9a-f]+:[	 ]+2581[	 ]+c.addiw[	 ]+a1,0
diff --git a/gas/testsuite/gas/riscv/zc-zcb-sextw.s b/gas/testsuite/gas/riscv/zc-zcb-sextw.s
new file mode 100644
index 00000000000..1b76b058fd3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-sextw.s
@@ -0,0 +1,13 @@ 
+# c.sext.w is an alias of c.addiw
+zcb64:
+	# test to compress zext.w insturctions
+	sext.w x9,x9
+	sext.w x1,x1
+	sext.w x19,x19
+	sext.w x14,x14
+
+	# test c.sext.w
+	c.sext.w x15
+	c.sext.w x8
+	c.sext.w x9
+	c.sext.w x11
diff --git a/gas/testsuite/gas/riscv/zc-zcb-sh.d b/gas/testsuite/gas/riscv/zc-zcb-sh.d
new file mode 100644
index 00000000000..5897955357b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-sh.d
@@ -0,0 +1,26 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-sh.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb_sh>:
+[	 ]*[0-9a-f]+:[	 ]+8c20[	 ]+c.sh[	 ]+s0,2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8f9c[	 ]+c.sh[	 ]+a5,0\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8c20[	 ]+c.sh[	 ]+s0,2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8ca4[	 ]+c.sh[	 ]+s1,2\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+8e10[	 ]+c.sh[	 ]+a2,0\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+8eb4[	 ]+c.sh[	 ]+a3,2\(a3\)
+[	 ]*[0-9a-f]+:[	 ]+8f18[	 ]+c.sh[	 ]+a4,0\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+8ca4[	 ]+c.sh[	 ]+s1,2\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+8fbc[	 ]+c.sh[  	 ]+a5,2\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+8c00[	 ]+c.sh[  	 ]+s0,0\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8c84[	 ]+c.sh[  	 ]+s1,0\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+8e30[	 ]+c.sh[  	 ]+a2,2\(a2\)
+[	 ]*[0-9a-f]+:[	 ]+8eb4[	 ]+c.sh[  	 ]+a3,2\(a3\)
+[	 ]*[0-9a-f]+:[	 ]+8f18[	 ]+c.sh[  	 ]+a4,0\(a4\)
+[	 ]*[0-9a-f]+:[	 ]+8c00[	 ]+c.sh[  	 ]+s0,0\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+8c84[	 ]+c.sh[  	 ]+s1,0\(s1\)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-sh.s b/gas/testsuite/gas/riscv/zc-zcb-sh.s
new file mode 100644
index 00000000000..a7ed266c0fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-sh.s
@@ -0,0 +1,22 @@ 
+zcb_sh:
+	# test to compress sh
+	sh x8,2(x8)
+	sh x15,0(x15)
+	sh x8,2(x8)
+	sh x9,2(x9)
+	sh x12,0(x12)
+	sh x13,2(x13)
+	sh x14,0(x14)
+
+	# test c.sh
+	c.sh x9,2(x9)
+	c.sh x15,2(x15)
+	c.sh x8,0(x8)
+	c.sh x9,0(x9)
+	c.sh x12,2(x12)
+	c.sh x13,2(x13)
+	c.sh x14,0(x14)
+
+	# implicit zero offset
+	c.sh x8,(x8)
+	sh x9,(x9)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d b/gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d
new file mode 100644
index 00000000000..3bda7358ab0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-arch-gc.d
@@ -0,0 +1,28 @@ 
+#as: -march=rv64gc_zba_zbb
+#source: zc-zcb-test-arch.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[	 ]*[0-9a-f]+:[	 ]+009480a3+[	 ]+sb[	 ]+s1,1\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+00f780a3+[	 ]+sb[	 ]+a5,1\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+0014c483+[	 ]+lbu[	 ]+s1,1\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+0017c783+[	 ]+lbu[	 ]+a5,1\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+00449483+[	 ]+lh[	 ]+s1,4\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+00479783+[	 ]+lh[	 ]+a5,4\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+0044d483+[	 ]+lhu[	 ]+s1,4\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+0047d783+[	 ]+lhu[	 ]+a5,4\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+00949223+[	 ]+sh[	 ]+s1,4\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+00f79223+[	 ]+sh[	 ]+a5,4\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+02b50533+[	 ]+mul[	 ]+a0,a0,a1
+[	 ]*[0-9a-f]+:[	 ]+60451513+[	 ]+sext.b[	 ]+a0,a0
+[	 ]*[0-9a-f]+:[	 ]+60551513+[	 ]+sext.h[	 ]+a0,a0
+[	 ]*[0-9a-f]+:[	 ]+0805453b+[	 ]+zext.h[	 ]+a0,a0
+[	 ]*[0-9a-f]+:[	 ]+0805053b+[	 ]+add.uw[	 ]+a0,a0,zero
+[	 ]*[0-9a-f]+:[	 ]+0ff57513+[	 ]+andi[	 ]+a0,a0,255
+[	 ]*[0-9a-f]+:[	 ]+fff5c593+[	 ]+xori[	 ]+a1,a1,-1
+[	 ]*[0-9a-f]+:[	 ]+2501+[	 ]+c.addiw[	 ]+a0,0
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d b/gas/testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d
new file mode 100644
index 00000000000..1385503e9f4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-arch-no-zcb.d
@@ -0,0 +1,28 @@ 
+#as: -march=rv64g_zca_zba_zbb
+#source: zc-zcb-test-arch.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[	 ]*[0-9a-f]+:[	 ]+009480a3+[	 ]+sb[	 ]+s1,1\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+00f780a3+[	 ]+sb[	 ]+a5,1\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+0014c483+[	 ]+lbu[	 ]+s1,1\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+0017c783+[	 ]+lbu[	 ]+a5,1\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+00449483+[	 ]+lh[	 ]+s1,4\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+00479783+[	 ]+lh[	 ]+a5,4\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+0044d483+[	 ]+lhu[	 ]+s1,4\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+0047d783+[	 ]+lhu[	 ]+a5,4\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+00949223+[	 ]+sh[	 ]+s1,4\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+00f79223+[	 ]+sh[	 ]+a5,4\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+02b50533+[	 ]+mul[	 ]+a0,a0,a1
+[	 ]*[0-9a-f]+:[	 ]+60451513+[	 ]+sext.b[	 ]+a0,a0
+[	 ]*[0-9a-f]+:[	 ]+60551513+[	 ]+sext.h[	 ]+a0,a0
+[	 ]*[0-9a-f]+:[	 ]+0805453b+[	 ]+zext.h[	 ]+a0,a0
+[	 ]*[0-9a-f]+:[	 ]+0805053b+[	 ]+add.uw[	 ]+a0,a0,zero
+[	 ]*[0-9a-f]+:[	 ]+0ff57513+[	 ]+andi[	 ]+a0,a0,255
+[	 ]*[0-9a-f]+:[	 ]+fff5c593+[	 ]+xori[	 ]+a1,a1,-1
+[	 ]*[0-9a-f]+:[	 ]+2501+[	 ]+c.addiw[	 ]+a0,0
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-arch.s b/gas/testsuite/gas/riscv/zc-zcb-test-arch.s
new file mode 100644
index 00000000000..ae7292af598
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-arch.s
@@ -0,0 +1,22 @@ 
+# except c.sext.w compressed into c.addiw, no compression happens without zcb
+target:
+	sb x9,1(x9)
+	sb x15,1(x15)
+	lbu x9,1(x9)
+	lbu x15,1(x15)
+	lh x9,4(x9)
+	lh x15,4(x15)
+	lhu x9,4(x9)
+	lhu x15,4(x15)
+	sh x9,4(x9)
+	sh x15,4(x15)
+
+	mul a0,a0,a1
+	sext.b a0,a0
+	sext.h a0,a0
+	zext.h a0,a0
+	zext.w a0,a0 # alias of add.uw rd,rd,zero
+
+	zext.b a0,a0 # alias of andi rd,rs,255
+	not a1,a1    # alias of xori rd,rs,-1
+	sext.w a0,a0 # alias of addiw rd,rs,0
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.d b/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.d
new file mode 100644
index 00000000000..5e7d405c024
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.d
@@ -0,0 +1,36 @@ 
+#as: -march=rv64g_zca_zcb_zba_zbb
+#source: zc-zcb-test-operand-0.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[	 ]*[0-9a-f]+:[	 ]+001480a3+[	 ]+sb[	 ]+ra,1\(s1\)
+[	 ]*[0-9a-f]+:[	 ]+00a980a3+[	 ]+sb[	 ]+a0,1\(s3\)
+[	 ]*[0-9a-f]+:[	 ]+00f09123+[	 ]+sh[	 ]+a5,2\(ra\)
+[	 ]*[0-9a-f]+:[	 ]+00f292a3+[	 ]+sh[	 ]+a5,5\(t0\)
+[	 ]*[0-9a-f]+:[	 ]+0017c003+[	 ]+lbu[	 ]+zero,1\(a5\)
+[	 ]*[0-9a-f]+:[	 ]+00114503+[	 ]+lbu[	 ]+a0,1\(sp\)
+[	 ]*[0-9a-f]+:[	 ]+00291483+[	 ]+lh[	 ]+s1,2\(s2\)
+[	 ]*[0-9a-f]+:[	 ]+00259903+[	 ]+lh[	 ]+s2,2\(a1\)
+[	 ]*[0-9a-f]+:[	 ]+00285483+[	 ]+lhu[	 ]+s1,2\(a6\)
+[	 ]*[0-9a-f]+:[	 ]+00255383+[	 ]+lhu[	 ]+t2,2\(a0\)
+[	 ]*[0-9a-f]+:[	 ]+fff84813+[	 ]+xori[	 ]+a6,a6,-1
+[	 ]*[0-9a-f]+:[	 ]+ffffcf93+[	 ]+xori[	 ]+t6,t6,-1
+[	 ]*[0-9a-f]+:[	 ]+02b383b3+[	 ]+mul[	 ]+t2,t2,a1
+[	 ]*[0-9a-f]+:[	 ]+026484b3+[	 ]+mul[	 ]+s1,s1,t1
+[	 ]*[0-9a-f]+:[	 ]+02b80833+[	 ]+mul[	 ]+a6,a6,a1
+[	 ]*[0-9a-f]+:[	 ]+030484b3+[	 ]+mul[	 ]+s1,s1,a6
+[	 ]*[0-9a-f]+:[	 ]+60429293+[	 ]+sext.b[	 ]+t0,t0
+[	 ]*[0-9a-f]+:[	 ]+60401013+[	 ]+sext.b[	 ]+zero,zero
+[	 ]*[0-9a-f]+:[	 ]+60521213+[	 ]+sext.h[	 ]+tp,tp
+[	 ]*[0-9a-f]+:[	 ]+60529293+[	 ]+sext.h[	 ]+t0,t0
+[	 ]*[0-9a-f]+:[	 ]+0ffb7b13+[	 ]+andi[	 ]+s6,s6,255
+[	 ]*[0-9a-f]+:[	 ]+0ffafa93+[	 ]+andi[	 ]+s5,s5,255
+[	 ]*[0-9a-f]+:[	 ]+0808c8bb+[	 ]+zext.h[	 ]+a7,a7
+[	 ]*[0-9a-f]+:[	 ]+0800403b+[	 ]+zext.h[	 ]+zero,zero
+[	 ]*[0-9a-f]+:[	 ]+080284bb+[	 ]+add.uw[	 ]+s1,t0,zero
+[	 ]*[0-9a-f]+:[	 ]+0800003b+[	 ]+add.uw[	 ]+zero,zero,zero
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.s b/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.s
new file mode 100644
index 00000000000..0d0944c7517
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-0.s
@@ -0,0 +1,32 @@ 
+# test if zcb instructions compress instructions with improper operands
+target:
+	# rs' or rd' not in x8-x15
+	sb x1,1(x9)
+	sb x10,1(x19)
+	sh x15,2(x1)
+	sh x15,5(x5)
+	lbu x0,1(x15)
+	lbu x10,1(x2)
+	lh x9,2(x18)
+	lh x18,2(x11)
+	lhu x9,2(x16)
+	lhu x7,2(x10)
+	# not rd,rs is an alias of xori rd,rs,-1
+	not x16,x16
+	not x31,x31
+	mul x7,x7,x11
+	mul x9,x9,x6
+	mul x16,x16,x11
+	mul x9,x9,x16
+	sext.b x5,x5
+	sext.b x0,x0
+	sext.h x4,x4
+	sext.h x5,x5
+	# zext.b rd,rs is an alias of andi rd,rs,255
+	zext.b x22,x22
+	zext.b x21,x21
+	zext.h x17,x17
+	zext.h x0,x0
+	# zext.w rd,rs is an alias of add.uw rd,rs,zero
+	zext.w x9,x5
+	zext.w x0,x0
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.d b/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.d
new file mode 100644
index 00000000000..cd97b94dfa8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.d
@@ -0,0 +1,18 @@ 
+#as: -march=rv64g_zca_zcb_zba_zbb
+#source: zc-zcb-test-operand-1.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[	 ]*[0-9a-f]+:[	 ]+fff54493+[	 ]+xori[	 ]+s1,a0,-1
+[	 ]*[0-9a-f]+:[	 ]+02b48533+[	 ]+mul[	 ]+a0,s1,a1
+[	 ]*[0-9a-f]+:[	 ]+60449413+[	 ]+sext.b[	 ]+s0,s1
+[	 ]*[0-9a-f]+:[	 ]+60549513+[	 ]+sext.h[	 ]+a0,s1
+[	 ]*[0-9a-f]+:[	 ]+0004841b+[	 ]+addiw[	 ]+s0,s1,0
+[	 ]*[0-9a-f]+:[	 ]+0ff4f593+[	 ]+andi[	 ]+a1,s1,255
+[	 ]*[0-9a-f]+:[	 ]+0804c43b+[	 ]+zext.h[	 ]+s0,s1
+[	 ]*[0-9a-f]+:[	 ]+0804863b+[	 ]+add.uw[	 ]+a2,s1,zero
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.s b/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.s
new file mode 100644
index 00000000000..e5c46370f42
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-1.s
@@ -0,0 +1,11 @@ 
+# test if zcb instructions compress instructions with improper operands
+target:
+	# rs' != rd'
+	not x9,x10
+	mul x10,x9,x11
+	sext.b x8,x9
+	sext.h x10,x9
+	sext.w x8,x9
+	zext.b x11,x9
+	zext.h x8,x9
+	zext.w x12,x9
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.d b/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.d
new file mode 100644
index 00000000000..415553f6d4b
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.d
@@ -0,0 +1,28 @@ 
+#as: -march=rv64g_zca_zcb
+#source: zc-zcb-test-operand-2.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[	 ]*[0-9a-f]+:[	 ]+fe840fa3+[	 ]+sb[	 ]+s0,-1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+00840223+[	 ]+sb[	 ]+s0,4\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+fe840f23+[	 ]+sb[	 ]+s0,-2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+fff44403+[	 ]+lbu[	 ]+s0,-1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+00444403+[	 ]+lbu[	 ]+s0,4\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+ffe44403+[	 ]+lbu[	 ]+s0,-2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+00841223+[	 ]+sh[	 ]+s0,4\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+008411a3+[	 ]+sh[	 ]+s0,3\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+fe841fa3+[	 ]+sh[	 ]+s0,-1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+fe841f23+[	 ]+sh[	 ]+s0,-2\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+00441403+[	 ]+lh[	 ]+s0,4\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+00341403+[	 ]+lh[	 ]+s0,3\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+fff41403+[	 ]+lh[	 ]+s0,-1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+ffd41403+[	 ]+lh[	 ]+s0,-3\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+00445403+[	 ]+lhu[	 ]+s0,4\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+00345403+[	 ]+lhu[	 ]+s0,3\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+fff45403+[	 ]+lhu[	 ]+s0,-1\(s0\)
+[	 ]*[0-9a-f]+:[	 ]+00345403+[	 ]+lhu[	 ]+s0,3\(s0\)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.s b/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.s
new file mode 100644
index 00000000000..5de7e2e65c8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-test-operand-2.s
@@ -0,0 +1,21 @@ 
+# test if zcb instructions compress instructions with improper operands
+target:
+	# improper imm operands
+	sb x8,-1(x8)
+	sb x8,4(x8)
+	sb x8,-2(x8)
+	lbu x8,-1(x8)
+	lbu x8,4(x8)
+	lbu x8,-2(x8)
+	sh x8,4(x8)
+	sh x8,3(x8)
+	sh x8,-1(x8)
+	sh x8,-2(x8)
+	lh x8,4(x8)
+	lh x8,3(x8)
+	lh x8,-1(x8)
+	lh x8,-3(x8)
+	lhu x8,4(x8)
+	lhu x8,3(x8)
+	lhu x8,-1(x8)
+	lhu x8,3(x8)
diff --git a/gas/testsuite/gas/riscv/zc-zcb-zext-b.d b/gas/testsuite/gas/riscv/zc-zcb-zext-b.d
new file mode 100644
index 00000000000..16dfad2b620
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-zext-b.d
@@ -0,0 +1,20 @@ 
+#as: -march=rv32g_zca_zcb
+#source: zc-zcb-zext-b.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb>:
+[	 ]*[0-9a-f]+:[	 ]+9c61[	 ]+c.zext.b[	 ]+s0
+[	 ]*[0-9a-f]+:[	 ]+9fe1[	 ]+c.zext.b[	 ]+a5
+[	 ]*[0-9a-f]+:[	 ]+9d61[	 ]+c.zext.b[	 ]+a0
+[	 ]*[0-9a-f]+:[	 ]+9ce1[	 ]+c.zext.b[	 ]+s1
+[	 ]*[0-9a-f]+:[	 ]+9e61[	 ]+c.zext.b[	 ]+a2
+[	 ]*[0-9a-f]+:[	 ]+9c61[	 ]+c.zext.b[	 ]+s0
+[	 ]*[0-9a-f]+:[	 ]+9fe1[	 ]+c.zext.b[	 ]+a5
+[	 ]*[0-9a-f]+:[	 ]+9ce1[	 ]+c.zext.b[	 ]+s1
+[	 ]*[0-9a-f]+:[	 ]+9e61[	 ]+c.zext.b[	 ]+a2
+[	 ]*[0-9a-f]+:[	 ]+9f61[	 ]+c.zext.b[	 ]+a4
diff --git a/gas/testsuite/gas/riscv/zc-zcb-zext-b.s b/gas/testsuite/gas/riscv/zc-zcb-zext-b.s
new file mode 100644
index 00000000000..f33a7b673cb
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-zext-b.s
@@ -0,0 +1,14 @@ 
+zcb:
+	# test zcb sign/zero extension insturction
+	c.zext.b x8
+	c.zext.b x15
+	c.zext.b x10
+	c.zext.b x9
+	c.zext.b x12
+
+	# test to compress sign/zero extension insturctions
+	zext.b x8,x8
+	zext.b x15,x15
+	zext.b x9,x9
+	zext.b x12,x12
+	zext.b x14,x14
diff --git a/gas/testsuite/gas/riscv/zc-zcb-zext-h.d b/gas/testsuite/gas/riscv/zc-zcb-zext-h.d
new file mode 100644
index 00000000000..e060a1eee85
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-zext-h.d
@@ -0,0 +1,20 @@ 
+#as: -march=rv32g_zca_zcb_zbb
+#source: zc-zcb-zext-h.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb>:
+[	 ]*[0-9a-f]+:[	 ]+9c69[	 ]+c.zext.h[	 ]+s0
+[	 ]*[0-9a-f]+:[	 ]+9fe9[	 ]+c.zext.h[	 ]+a5
+[	 ]*[0-9a-f]+:[	 ]+9d69[	 ]+c.zext.h[	 ]+a0
+[	 ]*[0-9a-f]+:[	 ]+9ce9[	 ]+c.zext.h[	 ]+s1
+[	 ]*[0-9a-f]+:[	 ]+9e69[	 ]+c.zext.h[	 ]+a2
+[	 ]*[0-9a-f]+:[	 ]+9c69[	 ]+c.zext.h[	 ]+s0
+[	 ]*[0-9a-f]+:[	 ]+9fe9[	 ]+c.zext.h[	 ]+a5
+[	 ]*[0-9a-f]+:[	 ]+9ce9[	 ]+c.zext.h[	 ]+s1
+[	 ]*[0-9a-f]+:[	 ]+9e69[	 ]+c.zext.h[	 ]+a2
+[	 ]*[0-9a-f]+:[	 ]+9f69[	 ]+c.zext.h[	 ]+a4
diff --git a/gas/testsuite/gas/riscv/zc-zcb-zext-h.s b/gas/testsuite/gas/riscv/zc-zcb-zext-h.s
new file mode 100644
index 00000000000..9b0c04c0b2d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-zext-h.s
@@ -0,0 +1,14 @@ 
+zcb:
+	# test zcb sign/zero extension insturction
+	c.zext.h x8
+	c.zext.h x15
+	c.zext.h x10
+	c.zext.h x9
+	c.zext.h x12
+
+	# test to compress sign/zero extension insturctions
+	zext.h x8,x8
+	zext.h x15,x15
+	zext.h x9,x9
+	zext.h x12,x12
+	zext.h x14,x14
diff --git a/gas/testsuite/gas/riscv/zc-zcb-zextw.d b/gas/testsuite/gas/riscv/zc-zcb-zextw.d
new file mode 100644
index 00000000000..81a9d5c500d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-zextw.d
@@ -0,0 +1,20 @@ 
+#as: -march=rv64g_zca_zcb_zba
+#source: zc-zcb-zextw.s
+#objdump: -dr -Mno-aliases
+
+.*:[	 ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <zcb64>:
+[	 ]*[0-9a-f]+:[	 ]+9cf1[	 ]+c.zext.w[	 ]+s1
+[	 ]*[0-9a-f]+:[	 ]+9d71[	 ]+c.zext.w[	 ]+a0
+[	 ]*[0-9a-f]+:[	 ]+9df1[	 ]+c.zext.w[	 ]+a1
+[	 ]*[0-9a-f]+:[	 ]+9f71[	 ]+c.zext.w[	 ]+a4
+[	 ]*[0-9a-f]+:[	 ]+9ff1[	 ]+c.zext.w[	 ]+a5
+[	 ]*[0-9a-f]+:[	 ]+9c71[	 ]+c.zext.w[	 ]+s0
+[	 ]*[0-9a-f]+:[	 ]+9ff1[	 ]+c.zext.w[	 ]+a5
+[	 ]*[0-9a-f]+:[	 ]+9c71[	 ]+c.zext.w[	 ]+s0
+[	 ]*[0-9a-f]+:[	 ]+9cf1[	 ]+c.zext.w[	 ]+s1
+[	 ]*[0-9a-f]+:[	 ]+9df1[	 ]+c.zext.w[	 ]+a1
diff --git a/gas/testsuite/gas/riscv/zc-zcb-zextw.s b/gas/testsuite/gas/riscv/zc-zcb-zextw.s
new file mode 100644
index 00000000000..9c40f8fa80f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcb-zextw.s
@@ -0,0 +1,16 @@ 
+zcb64:
+	# test to compress zext.w insturctions
+	zext.w x9,x9
+	zext.w x10,x10
+	zext.w x11,x11
+	zext.w x14,x14
+
+	# test to compress sign/zero extension insturctions(boundary)
+	zext.w x15,x15
+	zext.w x8,x8
+
+	# test c.zext.w
+	c.zext.w x15
+	c.zext.w x8
+	c.zext.w x9
+	c.zext.w x11