new file mode 100644
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: zc-zcd-fld-fsd-fail-march.s
+#error_output: zc-zcd-fld-fsd-fail-march.l
new file mode 100644
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `fld fa0,0\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,64\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,128\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,0\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,64\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fld fa0,128\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fa0,0\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fa0,64\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fa0,128\(a0\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fs2,0\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fs2,64\(sp\)', extension `d' required
+.*: Error: unrecognized opcode `fsd fs2,128\(sp\)', extension `d' required
new file mode 100644
@@ -0,0 +1,15 @@
+# Absence of zcd or dc march option disables all zcd
+target:
+ # ZCD only compress double float instructions
+ fld fa0, 0(a0)
+ fld fa0, 64(a0)
+ fld fa0, 128(a0)
+ fld fa0, 0(sp)
+ fld fa0, 64(sp)
+ fld fa0, 128(sp)
+ fsd fa0, 0(a0)
+ fsd fa0, 64(a0)
+ fsd fa0, 128(a0)
+ fsd fs2, 0(sp)
+ fsd fs2, 64(sp)
+ fsd fs2, 128(sp)
new file mode 100644
@@ -0,0 +1,16 @@
+#as: -march=rv64ifd_zcd
+#source: zc-zcd-fld.s
+#objdump: -d -Mno-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+2108[ ]+c.fld[ ]+fa0,0\(a0\)
+[ ]+2:[ ]+2128[ ]+c.fld[ ]+fa0,64\(a0\)
+[ ]+4:[ ]+2148[ ]+c.fld[ ]+fa0,128\(a0\)
+[ ]+6:[ ]+2502[ ]+c.fldsp[ ]+fa0,0\(sp\)
+[ ]+8:[ ]+2506[ ]+c.fldsp[ ]+fa0,64\(sp\)
+[ ]+a:[ ]+250a[ ]+c.fldsp[ ]+fa0,128\(sp\)
new file mode 100644
@@ -0,0 +1,8 @@
+target:
+ # ZCD only compress double float instructions
+ fld fa0, 0(a0) #CM
+ fld fa0, 64(a0) #CM
+ fld fa0, 128(a0) #CM
+ fld fa0, 0(sp) #CK
+ fld fa0, 64(sp) #CK
+ fld fa0, 128(sp) #CK
new file mode 100644
@@ -0,0 +1,16 @@
+#as: -march=rv64ifd_zcd
+#source: zc-zcd-fsd.s
+#objdump: -d -Mno-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+0:[ ]+a108[ ]+c.fsd[ ]+fa0,0\(a0\)
+[ ]+2:[ ]+a128[ ]+c.fsd[ ]+fa0,64\(a0\)
+[ ]+4:[ ]+a148[ ]+c.fsd[ ]+fa0,128\(a0\)
+[ ]+6:[ ]+a04a[ ]+c.fsdsp[ ]+fs2,0\(sp\)
+[ ]+8:[ ]+a0ca[ ]+c.fsdsp[ ]+fs2,64\(sp\)
+[ ]+a:[ ]+a14a[ ]+c.fsdsp[ ]+fs2,128\(sp\)
new file mode 100644
@@ -0,0 +1,8 @@
+target:
+ # ZCD only compress double float instructions
+ fsd fa0, 0(a0)
+ fsd fa0, 64(a0)
+ fsd fa0, 128(a0)
+ fsd fs2, 0(sp)
+ fsd fs2, 64(sp)
+ fsd fs2, 128(sp)