diff mbox series

[3/4] RISC-V: Add Zcf extension testcases.

Message ID 20230613132342.783814-4-jiawei@iscas.ac.cn
State Accepted
Headers
Series RISC-V: Support ZC* extensions. |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Jiawei June 13, 2023, 1:23 p.m. UTC 
  Add Zcf extension testcases, notice that zcf only uses in rv32 with f
extension.

Co-Authored by: Charlie Keaney <charlie.keaney@embecosm.com>
Co-Authored by: Mary Bennett <mary.bennett@embecosm.com>
Co-Authored by: Nandni Jamnadas <nandni.jamnadas@embecosm.com>
Co-Authored by: Sinan Lin <sinan.lin@linux.alibaba.com>
Co-Authored by: Simon Cook <simon.cook@embecosm.com>
Co-Authored by: Shihua Liao <shihua@iscas.ac.cn>
Co-Authored by: Yulong Shi <yulong@iscas.ac.cn>

gas/ChangeLog:

        * testsuite/gas/riscv/zc-zcf-flw-32.d: New test.
        * testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.d: New test.
        * testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.l: New test.
        * testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.s: New test.
        * testsuite/gas/riscv/zc-zcf-flw.s: New test.
        * testsuite/gas/riscv/zc-zcf-fsw-32.d: New test.
        * testsuite/gas/riscv/zc-zcf-fsw.s: New test.

---
 gas/testsuite/gas/riscv/zc-zcf-flw-32.d          | 16 ++++++++++++++++
 .../gas/riscv/zc-zcf-flw-fsw-fail-march.d        |  3 +++
 .../gas/riscv/zc-zcf-flw-fsw-fail-march.l        | 13 +++++++++++++
 .../gas/riscv/zc-zcf-flw-fsw-fail-march.s        | 15 +++++++++++++++
 gas/testsuite/gas/riscv/zc-zcf-flw.s             |  8 ++++++++
 gas/testsuite/gas/riscv/zc-zcf-fsw-32.d          | 16 ++++++++++++++++
 gas/testsuite/gas/riscv/zc-zcf-fsw.s             |  8 ++++++++
 7 files changed, 79 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/zc-zcf-flw-32.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.l
 create mode 100644 gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcf-flw.s
 create mode 100644 gas/testsuite/gas/riscv/zc-zcf-fsw-32.d
 create mode 100644 gas/testsuite/gas/riscv/zc-zcf-fsw.s
diff mbox series

Patch

diff --git a/gas/testsuite/gas/riscv/zc-zcf-flw-32.d b/gas/testsuite/gas/riscv/zc-zcf-flw-32.d
new file mode 100644
index 00000000000..ec2997301f3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcf-flw-32.d
@@ -0,0 +1,16 @@ 
+#as: -march=rv32ifd_zcf
+#source: zc-zcf-flw.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+6108[ 	]+c.flw[ 	]+fa0,0\(a0\)
+[ 	]+2:[ 	]+7d48[ 	]+c.flw[ 	]+fa0,60\(a0\)
+[ 	]+4:[ 	]+7168[ 	]+c.flw[ 	]+fa0,100\(a0\)
+[ 	]+6:[ 	]+6502[ 	]+c.flwsp[ 	]+fa0,0\(sp\)
+[ 	]+8:[ 	]+7572[ 	]+c.flwsp[ 	]+fa0,60\(sp\)
+[ 	]+a:[ 	]+7516[ 	]+c.flwsp[ 	]+fa0,100\(sp\)
diff --git a/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.d b/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.d
new file mode 100644
index 00000000000..4fde8143b4f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.d
@@ -0,0 +1,3 @@ 
+#as: -march=rv32i
+#source: zc-zcf-flw-fsw-fail-march.s
+#error_output: zc-zcf-flw-fsw-fail-march.l
diff --git a/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.l b/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.l
new file mode 100644
index 00000000000..b3c1db2d4c2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.l
@@ -0,0 +1,13 @@ 
+.*: Assembler messages:
+.*: Error: unrecognized opcode `flw fa0,0\(a0\)', extension `f' required
+.*: Error: unrecognized opcode `flw fa0,60\(a0\)', extension `f' required
+.*: Error: unrecognized opcode `flw fa0,100\(a0\)', extension `f' required
+.*: Error: unrecognized opcode `flw fa0,0\(sp\)', extension `f' required
+.*: Error: unrecognized opcode `flw fa0,60\(sp\)', extension `f' required
+.*: Error: unrecognized opcode `flw fa0,100\(sp\)', extension `f' required
+.*: Error: unrecognized opcode `fsw fa0,0\(a0\)', extension `f' required
+.*: Error: unrecognized opcode `fsw fa0,60\(a0\)', extension `f' required
+.*: Error: unrecognized opcode `fsw fa0,100\(a0\)', extension `f' required
+.*: Error: unrecognized opcode `fsw fs2,0\(sp\)', extension `f' required
+.*: Error: unrecognized opcode `fsw fs2,100\(sp\)', extension `f' required
+.*: Error: unrecognized opcode `fsw fs2,248\(sp\)', extension `f' required
diff --git a/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.s b/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.s
new file mode 100644
index 00000000000..569d721bc99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcf-flw-fsw-fail-march.s
@@ -0,0 +1,15 @@ 
+# Absence of zcf or fc march option disables all zcf
+target:
+	# ZCF only compress single float instructions
+        flw fa0, 0(a0)
+        flw fa0, 60(a0)
+        flw fa0, 100(a0)
+        flw fa0, 0(sp)
+        flw fa0, 60(sp)
+        flw fa0, 100(sp)
+        fsw fa0, 0(a0)
+        fsw fa0, 60(a0)
+        fsw fa0, 100(a0)
+        fsw fs2, 0(sp)
+        fsw fs2, 100(sp)
+        fsw fs2, 248(sp)
diff --git a/gas/testsuite/gas/riscv/zc-zcf-flw.s b/gas/testsuite/gas/riscv/zc-zcf-flw.s
new file mode 100644
index 00000000000..c3a110caad1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcf-flw.s
@@ -0,0 +1,8 @@ 
+target:
+	# ZCF only compress single float instructions
+        flw fa0, 0(a0)   #CM
+        flw fa0, 60(a0)   #CM
+        flw fa0, 100(a0) #CM
+        flw fa0, 0(sp)   #CK
+        flw fa0, 60(sp)   #CK
+        flw fa0, 100(sp) #CK
diff --git a/gas/testsuite/gas/riscv/zc-zcf-fsw-32.d b/gas/testsuite/gas/riscv/zc-zcf-fsw-32.d
new file mode 100644
index 00000000000..0907dd9773c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcf-fsw-32.d
@@ -0,0 +1,16 @@ 
+#as: -march=rv32ifd_zcf
+#source: zc-zcf-fsw.s
+#objdump: -d -Mno-aliases
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+e108[ 	]+c.fsw[ 	]+fa0,0\(a0\)
+[ 	]+2:[ 	]+fd48[ 	]+c.fsw[ 	]+fa0,60\(a0\)
+[ 	]+4:[ 	]+f168[ 	]+c.fsw[ 	]+fa0,100\(a0\)
+[ 	]+6:[ 	]+e04a[ 	]+c.fswsp[ 	]+fs2,0\(sp\)
+[ 	]+8:[ 	]+f2ca[ 	]+c.fswsp[ 	]+fs2,100\(sp\)
+[ 	]+a:[ 	]+fdca[ 	]+c.fswsp[ 	]+fs2,248\(sp\)
diff --git a/gas/testsuite/gas/riscv/zc-zcf-fsw.s b/gas/testsuite/gas/riscv/zc-zcf-fsw.s
new file mode 100644
index 00000000000..a4f199ca30f
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zc-zcf-fsw.s
@@ -0,0 +1,8 @@ 
+target:
+	# ZCF only compress single float instructions
+        fsw fa0, 0(a0)
+        fsw fa0, 60(a0)
+        fsw fa0, 100(a0)
+        fsw fs2, 0(sp)
+        fsw fs2, 100(sp)
+        fsw fs2, 248(sp)