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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id y25-20020a17090629d900b0094f335b0660si4650644eje.185.2023.06.12.01.37.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jun 2023 01:37:27 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9F6E33858C5E for ; Mon, 12 Jun 2023 08:37:26 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id E070C3858D32 for ; Mon, 12 Jun 2023 08:37:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E070C3858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [112.20.112.76]) by gateway (Coremail) with SMTP id _____8Bx7eo12YZkspYDAA--.7897S3; Mon, 12 Jun 2023 16:37:09 +0800 (CST) Received: from localhost.localdomain (unknown [112.20.112.76]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxluQz2YZkMmEVAA--.61676S2; Mon, 12 Jun 2023 16:37:08 +0800 (CST) From: Feiyang Chen To: liuzhensong@loongson.cn, xuchenghua@loongson.cn Cc: Feiyang Chen , chris.chenfeiyang@gmail.com, chenhuacai@loongson.cn, binutils@sourceware.org Subject: [PATCH] LoongArch: Add fcsr register names support Date: Mon, 12 Jun 2023 16:36:49 +0800 Message-Id: <20230612083649.907511-1-chenfeiyang@loongson.cn> X-Mailer: git-send-email 2.39.3 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxluQz2YZkMmEVAA--.61676S2 X-CM-SenderInfo: hfkh0wphl1t03j6o00pqjv00gofq/ X-Coremail-Antispam: 1Uk129KBj93XoWxtw4DAryDurWkZr1rtw15Jrc_yoW7Kw48pF 9xur15Kw4kGrnYy39rJ34YgF98JF4xWr12q3W3tr1xur47Xw13Xa18GFy09FnIk3y7WFy2 qF4rWa48WF48JFXCm3ZEXasCq-sJn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r106r15M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVWxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27w Aqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE 14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCF04k20xvY0x 0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E 7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcV C0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF 04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7 CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8czVUUUUUU== X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1768485340314699177?= X-GMAIL-MSGID: =?utf-8?q?1768485340314699177?= Add fcsr register names support for fcsr move instructions. gas/ChangeLog: * config/tc-loongarch.c: (loongarch_fc_normal_name): New definition. (loongarch_single_float_opcodes): Modify `movgr2fcsr` and `movfcsr2gr`. include/ChangeLog: * opcode/loongarch.h (loongarch_fc_normal_name): New extern. opcodes/ChangeLog: * opcodes/loongarch-dis.c (loongarch_after_parse_args): Add fcsr register names support. * opcodes/loongarch-opc.c (loongarch_args_parser_can_match_arg_helper): Likewise. Signed-off-by: Feiyang Chen --- gas/config/tc-loongarch.c | 22 +++++++++++++++++++++- include/opcode/loongarch.h | 1 + opcodes/loongarch-dis.c | 16 +++++++++++++++- opcodes/loongarch-opc.c | 9 +++++++-- 4 files changed, 44 insertions(+), 4 deletions(-) diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index c55d4ee234a..97971d76a57 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -223,6 +223,7 @@ md_parse_option (int c, const char *arg) static struct htab *r_htab = NULL; static struct htab *f_htab = NULL; +static struct htab *fc_htab = NULL; static struct htab *c_htab = NULL; static struct htab *cr_htab = NULL; static struct htab *v_htab = NULL; @@ -286,6 +287,18 @@ loongarch_after_parse_args () str_hash_insert (f_htab, loongarch_f_normal_name[i], (void *) (i + 1), 0); + if (!fc_htab) + fc_htab = str_htab_create (), str_hash_insert (fc_htab, "", 0, 0); + + for (i = 0; i < ARRAY_SIZE (loongarch_fc_normal_name); i++) + str_hash_insert (fc_htab, loongarch_fc_normal_name[i], (void *) (i + 1), + 0); + + /* Add general purpose registers for backward compatibility. */ + for (i = 0; i < ARRAY_SIZE (loongarch_r_normal_name); i++) + str_hash_insert (fc_htab, loongarch_r_normal_name[i], (void *) (i + 1), + 0); + if (!c_htab) c_htab = str_htab_create (), str_hash_insert (c_htab, "", 0, 0); @@ -666,7 +679,14 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, ret = imm - 1; break; case 'f': - imm = (intptr_t) str_hash_find (f_htab, arg); + switch (esc_ch2) + { + case 'c': + imm = (intptr_t) str_hash_find (fc_htab, arg); + break; + default: + imm = (intptr_t) str_hash_find (f_htab, arg); + } ip->match_now = 0 < imm; ret = imm - 1; break; diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h index 004bb6561ef..4ed273182c0 100644 --- a/include/opcode/loongarch.h +++ b/include/opcode/loongarch.h @@ -185,6 +185,7 @@ dec2 : [1-9][0-9]? extern const char *const loongarch_f_normal_name[32]; extern const char *const loongarch_f_lp64_name[32]; extern const char *const loongarch_f_lp64_name1[32]; + extern const char *const loongarch_fc_normal_name[4]; extern const char *const loongarch_c_normal_name[8]; extern const char *const loongarch_cr_normal_name[4]; extern const char *const loongarch_v_normal_name[32]; diff --git a/opcodes/loongarch-dis.c b/opcodes/loongarch-dis.c index d064d30d553..0e7d9a88c25 100644 --- a/opcodes/loongarch-dis.c +++ b/opcodes/loongarch-dis.c @@ -61,6 +61,7 @@ get_loongarch_opcode_by_binfmt (insn_t insn) static const char *const *loongarch_r_disname = NULL; static const char *const *loongarch_f_disname = NULL; +static const char *const *loongarch_fc_disname = NULL; static const char *const *loongarch_c_disname = NULL; static const char *const *loongarch_cr_disname = NULL; static const char *const *loongarch_v_disname = NULL; @@ -78,6 +79,7 @@ set_default_loongarch_dis_options (void) loongarch_r_disname = loongarch_r_lp64_name; loongarch_f_disname = loongarch_f_lp64_name; + loongarch_fc_disname = loongarch_fc_normal_name; loongarch_c_disname = loongarch_c_normal_name; loongarch_cr_disname = loongarch_cr_normal_name; loongarch_v_disname = loongarch_v_normal_name; @@ -142,7 +144,19 @@ dis_one_arg (char esc1, char esc2, const char *bit_field, info->fprintf_func (info->stream, "%s", loongarch_r_disname[u_imm]); break; case 'f': - info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]); + switch (esc2) + { + case 'c': + if (u_imm < 4) + info->fprintf_func (info->stream, "%s", loongarch_fc_disname[u_imm]); + else + /* For backward compatibility. Display using general purpose + register names if out of range. */ + info->fprintf_func (info->stream, "%s", loongarch_r_normal_name[u_imm]); + break; + default: + info->fprintf_func (info->stream, "%s", loongarch_f_disname[u_imm]); + } break; case 'c': switch (esc2) diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 573b691c1fd..99fbe318fd3 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -77,6 +77,11 @@ const char *const loongarch_f_lp64_name1[32] = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", }; +const char *const loongarch_fc_normal_name[4] = +{ + "$fcsr0", "$fcsr1", "$fcsr2", "$fcsr3", +}; + const char *const loongarch_c_normal_name[8] = { "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5", "$fcc6", "$fcc7", @@ -459,8 +464,8 @@ static struct loongarch_opcode loongarch_single_float_opcodes[] = { 0x0114ac00, 0xfffffc00, "movgr2frh.w", "f0:5,r5:5", 0, 0, 0, 0 }, { 0x0114b400, 0xfffffc00, "movfr2gr.s", "r0:5,f5:5", 0, 0, 0, 0 }, { 0x0114bc00, 0xfffffc00, "movfrh2gr.s", "r0:5,f5:5", 0, 0, 0, 0 }, - { 0x0114c000, 0xfffffc00, "movgr2fcsr", "r0:5,r5:5", 0, 0, 0, 0 }, - { 0x0114c800, 0xfffffc00, "movfcsr2gr", "r0:5,r5:5", 0, 0, 0, 0 }, + { 0x0114c000, 0xfffffc00, "movgr2fcsr", "fc0:5,r5:5", 0, 0, 0, 0 }, + { 0x0114c800, 0xfffffc00, "movfcsr2gr", "r0:5,fc5:5", 0, 0, 0, 0 }, { 0x0114d000, 0xfffffc18, "movfr2cf", "c0:3,f5:5", 0, 0, 0, 0 }, { 0x0114d400, 0xffffff00, "movcf2fr", "f0:5,c5:3", 0, 0, 0, 0 }, { 0x0114d800, 0xfffffc18, "movgr2cf", "c0:3,r5:5", 0, 0, 0, 0 },