x86: Add Evw to emit w suffix for several instrctions for word ptr
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Commit Message
Hi Jan,
I am trying to fix the questionable manner with this patch. See if it reaches
all our expectation.
Thx,
Haochen
Currently, for instructions lldt/ltr/verr/verw/lkgs, we are missing
w suffix for memory operands like sldt/str do. Also the Ew usage is
not that precise under this scenario. Add Evw to fix this problem.
gas/ChangeLog:
* testsuite/gas/i386/i386.exp: Add LKGS suffix test.
* testsuite/gas/i386/opcode-intel.d: Add ltr, verr, verw.
* testsuite/gas/i386/opcode-suffix.d: Ditto.
* testsuite/gas/i386/opcode.d: Ditto.
* testsuite/gas/i386/opcode.s: Ditto.
* testsuite/gas/i386/x86-64-lkgs-suffix.d: New test.
* testsuite/gas/i386/x86-64-lkgs-suffix.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c (Evw): New.
(v_w_mode): Ditto.
(lldt, ltr, verr, verw, lkgs): Change from Ew to Evw.
(intel_operand_size): Handle v_w_mode.
(print_register): Ditto.
---
gas/testsuite/gas/i386/i386.exp | 1 +
gas/testsuite/gas/i386/opcode-intel.d | 3 +++
gas/testsuite/gas/i386/opcode-suffix.d | 5 ++++-
gas/testsuite/gas/i386/opcode.d | 3 +++
gas/testsuite/gas/i386/opcode.s | 4 ++++
gas/testsuite/gas/i386/x86-64-lkgs-suffix.d | 15 +++++++++++++++
gas/testsuite/gas/i386/x86-64-lkgs-suffix.s | 7 +++++++
opcodes/i386-dis.c | 20 +++++++++++++++-----
8 files changed, 52 insertions(+), 6 deletions(-)
create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs-suffix.d
create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs-suffix.s
Comments
On 26.05.2023 10:26, Haochen Jiang wrote:
> Currently, for instructions lldt/ltr/verr/verw/lkgs, we are missing
> w suffix for memory operands like sldt/str do. Also the Ew usage is
> not that precise under this scenario. Add Evw to fix this problem.
So why not Sv? It's used solely for segment register moves, sldt, str,
and smsw right now. We're aiming for consistency among all insns
loading / storing segment selector values (and smsw fits that pattern,
but note that lmsw does not), so introducing a new Evw can't be the
solution (or else Sv users would also need switching).
> gas/ChangeLog:
>
> * testsuite/gas/i386/i386.exp: Add LKGS suffix test.
Just as a remark: You'll need to re-base this over what I've committed
half an hour or so ago.
Jan
> On 26.05.2023 10:26, Haochen Jiang wrote:
> > Currently, for instructions lldt/ltr/verr/verw/lkgs, we are missing w
> > suffix for memory operands like sldt/str do. Also the Ew usage is not
> > that precise under this scenario. Add Evw to fix this problem.
>
> So why not Sv? It's used solely for segment register moves, sldt, str, and
> smsw right now. We're aiming for consistency among all insns loading /
> storing segment selector values (and smsw fits that pattern, but note that
> lmsw does not), so introducing a new Evw can't be the solution (or else Sv
> users would also need switching).
There is a little difference between lldt/ltr/lkgs/verr/verw and sldt/str. We need
to fix the register to 16 bit while sldt/str did not. That is why I am not using Sv. Sv
will emit 'lldt %eax' but not 'lldt %ax' for current testcases and I suppose that is not
desired.
Also since lmsw did not fit the pattern so I did not touch that.
>
> > gas/ChangeLog:
> >
> > * testsuite/gas/i386/i386.exp: Add LKGS suffix test.
>
> Just as a remark: You'll need to re-base this over what I've committed half an
> hour or so ago.
Oh I see that, will rebase to that for v2 patch.
Thx,
Haochen
>
> Jan
On 26.05.2023 10:54, Jiang, Haochen wrote:
>> On 26.05.2023 10:26, Haochen Jiang wrote:
>>> Currently, for instructions lldt/ltr/verr/verw/lkgs, we are missing w
>>> suffix for memory operands like sldt/str do. Also the Ew usage is not
>>> that precise under this scenario. Add Evw to fix this problem.
>>
>> So why not Sv? It's used solely for segment register moves, sldt, str, and
>> smsw right now. We're aiming for consistency among all insns loading /
>> storing segment selector values (and smsw fits that pattern, but note that
>> lmsw does not), so introducing a new Evw can't be the solution (or else Sv
>> users would also need switching).
>
> There is a little difference between lldt/ltr/lkgs/verr/verw and sldt/str. We need
> to fix the register to 16 bit while sldt/str did not. That is why I am not using Sv. Sv
> will emit 'lldt %eax' but not 'lldt %ax' for current testcases and I suppose that is not
> desired.
Did you read my reply on one of the "Support Intel FRED LKGS" threads,
which I think I sent before this patch was sent? I do not follow why
you think "we need to fix the register to 16 bit".
Jan
> >>> Currently, for instructions lldt/ltr/verr/verw/lkgs, we are missing
> >>> w suffix for memory operands like sldt/str do. Also the Ew usage is
> >>> not that precise under this scenario. Add Evw to fix this problem.
> >>
> >> So why not Sv? It's used solely for segment register moves, sldt,
> >> str, and smsw right now. We're aiming for consistency among all insns
> >> loading / storing segment selector values (and smsw fits that
> >> pattern, but note that lmsw does not), so introducing a new Evw can't
> >> be the solution (or else Sv users would also need switching).
> >
> > There is a little difference between lldt/ltr/lkgs/verr/verw and
> > sldt/str. We need to fix the register to 16 bit while sldt/str did
> > not. That is why I am not using Sv. Sv will emit 'lldt %eax' but not
> > 'lldt %ax' for current testcases and I suppose that is not desired.
>
> Did you read my reply on one of the "Support Intel FRED LKGS" threads,
> which I think I sent before this patch was sent? I do not follow why you think
> "we need to fix the register to 16 bit".
Maybe I got some wrong understanding on that. It comes from the current testcase.
Trying to clarify that on disassembler.
Let's take lldt as example. Will 0f00d2 emit eax register or ax register for lldt?
If we need a 66 in bytecode to emit ax register as always, Sv+D fits the need. And then
the only thing we might need to do is to adjust the current testcase.
Haochen
>
> Jan
> > >>> Currently, for instructions lldt/ltr/verr/verw/lkgs, we are
> > >>> missing w suffix for memory operands like sldt/str do. Also the Ew
> > >>> usage is not that precise under this scenario. Add Evw to fix this
> problem.
> > >>
> > >> So why not Sv? It's used solely for segment register moves, sldt,
> > >> str, and smsw right now. We're aiming for consistency among all
> > >> insns loading / storing segment selector values (and smsw fits that
> > >> pattern, but note that lmsw does not), so introducing a new Evw
> > >> can't be the solution (or else Sv users would also need switching).
> > >
> > > There is a little difference between lldt/ltr/lkgs/verr/verw and
> > > sldt/str. We need to fix the register to 16 bit while sldt/str did
> > > not. That is why I am not using Sv. Sv will emit 'lldt %eax' but not
> > > 'lldt %ax' for current testcases and I suppose that is not desired.
> >
> > Did you read my reply on one of the "Support Intel FRED LKGS" threads,
> > which I think I sent before this patch was sent? I do not follow why
> > you think "we need to fix the register to 16 bit".
>
> Maybe I got some wrong understanding on that. It comes from the current
> testcase.
> Trying to clarify that on disassembler.
>
> Let's take lldt as example. Will 0f00d2 emit eax register or ax register for lldt?
One thing to add the current behavior for disassembler or trunk is to emit ax
register. Which I mean always is to as always with other instructions.
>
> If we need a 66 in bytecode to emit ax register as always, Sv+D fits the need.
> And then the only thing we might need to do is to adjust the current testcase.
>
> Haochen
>
> >
> > Jan
On 29.05.2023 04:08, Jiang, Haochen wrote:
>>>>>> Currently, for instructions lldt/ltr/verr/verw/lkgs, we are
>>>>>> missing w suffix for memory operands like sldt/str do. Also the Ew
>>>>>> usage is not that precise under this scenario. Add Evw to fix this
>> problem.
>>>>>
>>>>> So why not Sv? It's used solely for segment register moves, sldt,
>>>>> str, and smsw right now. We're aiming for consistency among all
>>>>> insns loading / storing segment selector values (and smsw fits that
>>>>> pattern, but note that lmsw does not), so introducing a new Evw
>>>>> can't be the solution (or else Sv users would also need switching).
>>>>
>>>> There is a little difference between lldt/ltr/lkgs/verr/verw and
>>>> sldt/str. We need to fix the register to 16 bit while sldt/str did
>>>> not. That is why I am not using Sv. Sv will emit 'lldt %eax' but not
>>>> 'lldt %ax' for current testcases and I suppose that is not desired.
>>>
>>> Did you read my reply on one of the "Support Intel FRED LKGS" threads,
>>> which I think I sent before this patch was sent? I do not follow why
>>> you think "we need to fix the register to 16 bit".
>>
>> Maybe I got some wrong understanding on that. It comes from the current
>> testcase.
>> Trying to clarify that on disassembler.
>>
>> Let's take lldt as example. Will 0f00d2 emit eax register or ax register for lldt?
>
> One thing to add the current behavior for disassembler or trunk is to emit ax
> register. Which I mean always is to as always with other instructions.
I'm afraid I don't really get what you concern is. Yes, ...
>> If we need a 66 in bytecode to emit ax register as always, Sv+D fits the need.
>> And then the only thing we might need to do is to adjust the current testcase.
... some existing disassembly testcases will likely need adjusting.
Jan
> >> Maybe I got some wrong understanding on that. It comes from the
> >> current testcase.
> >> Trying to clarify that on disassembler.
> >>
> >> Let's take lldt as example. Will 0f00d2 emit eax register or ax register for
> lldt?
> >
> > One thing to add the current behavior for disassembler or trunk is to
> > emit ax register. Which I mean always is to as always with other instructions.
>
> I'm afraid I don't really get what you concern is. Yes, ...
I mean, for bytecode 0f00d2, should it emit 'lldt %ax' or 'lldt %eax'?
Currently, in the testcase, it emits 'lldt %ax'. I suppose it actually fits documentation
and we should not change it.
BTW, I read SDM today again, for SLDT/STR, they have the exact explanation for
handling of r32/r64.
For STR, we have:
"When the destination operand is a 32-bit register, ..."
"In 64-bit mode, operation is the same. The size of the memory operand is fixed at 16 bits.
In register stores, the 2-byte TR is zero extended if stored to a 64-bit register."
For SLDT, we have:
"Outside IA-32e mode, when the destination operand is a 32-bit register,..."
"In compatibility mode, when the destination operand is a 32-bit register,..."
"In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional
registers (R8-R15). "
But for LLDT/LTR/VERW/VERR, things are different. The operands at least will be fixed at 16 bits
in 64-bit mode.
For LLDT, we have:
"The operand-size attribute has no effect on this instruction.
The LLDT instruction is provided for use in operating-system software; it should not be used
in application programs. This instruction can only be executed in protected mode or 64-bit mode.
In 64-bit mode, the operand size is fixed at 16 bits."
For LTR, we have:
"The operand-size attribute has no effect on this instruction.
In 64-bit mode, the operand size is still fixed at 16 bits."
For VERR/VERW, we have:
"This instruction’s operation is the same in non-64-bit modes and 64-bit mode. The operand size
is fixed at 16 bits."
Therefore, I suppose for VERR/VERW, the 32/64 bit register should never be allowed under any
circumstances. For LLDT/LTR, in 64-bit mode, it should also the same conclusion. In protected mode
and compatibility mode, it is questionable. The current implementation of assembler might need a
fix.
H.J., what is your opinion?
Haochen
>
> >> If we need a 66 in bytecode to emit ax register as always, Sv+D fits the
> need.
> >> And then the only thing we might need to do is to adjust the current
> testcase.
>
> ... some existing disassembly testcases will likely need adjusting.
>
> Jan
On 31.05.2023 07:48, Jiang, Haochen wrote:
>>>> Maybe I got some wrong understanding on that. It comes from the
>>>> current testcase.
>>>> Trying to clarify that on disassembler.
>>>>
>>>> Let's take lldt as example. Will 0f00d2 emit eax register or ax register for
>> lldt?
>>>
>>> One thing to add the current behavior for disassembler or trunk is to
>>> emit ax register. Which I mean always is to as always with other instructions.
>>
>> I'm afraid I don't really get what you concern is. Yes, ...
>
> I mean, for bytecode 0f00d2, should it emit 'lldt %ax' or 'lldt %eax'?
The former in 16-bit code, the latter elsewhere.
> Currently, in the testcase, it emits 'lldt %ax'. I suppose it actually fits documentation
> and we should not change it.
I think we should change it. Expressing operand size by proper GPR
selection is better than emitting (bogus imo) prefixes. Plus, as
said, before, please see the (in principle similar) move to/from
SREG insn handling.
> BTW, I read SDM today again, for SLDT/STR, they have the exact explanation for
> handling of r32/r64.
>
> For STR, we have:
> "When the destination operand is a 32-bit register, ..."
> "In 64-bit mode, operation is the same. The size of the memory operand is fixed at 16 bits.
> In register stores, the 2-byte TR is zero extended if stored to a 64-bit register."
>
> For SLDT, we have:
> "Outside IA-32e mode, when the destination operand is a 32-bit register,..."
> "In compatibility mode, when the destination operand is a 32-bit register,..."
> "In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional
> registers (R8-R15). "
>
> But for LLDT/LTR/VERW/VERR, things are different. The operands at least will be fixed at 16 bits
> in 64-bit mode.
> For LLDT, we have:
> "The operand-size attribute has no effect on this instruction.
> The LLDT instruction is provided for use in operating-system software; it should not be used
> in application programs. This instruction can only be executed in protected mode or 64-bit mode.
> In 64-bit mode, the operand size is fixed at 16 bits."
>
> For LTR, we have:
> "The operand-size attribute has no effect on this instruction.
> In 64-bit mode, the operand size is still fixed at 16 bits."
>
> For VERR/VERW, we have:
> "This instruction’s operation is the same in non-64-bit modes and 64-bit mode. The operand size
> is fixed at 16 bits."
>
> Therefore, I suppose for VERR/VERW, the 32/64 bit register should never be allowed under any
> circumstances. For LLDT/LTR, in 64-bit mode, it should also the same conclusion. In protected mode
> and compatibility mode, it is questionable. The current implementation of assembler might need a
> fix.
Once again, please compare to other insns where we handle things properly.
Moves to/from SREG, as mentioned above, and things like PEXTRW/PINSRW. The
way the SDM puts things isn't always best; the main goal ought to be
consistency within the disassembler (and, just that it's not relevant here,
the assembler as well, of course).
Jan
On Fri, May 26, 2023 at 1:28 AM Haochen Jiang <haochen.jiang@intel.com> wrote:
>
> Hi Jan,
>
> I am trying to fix the questionable manner with this patch. See if it reaches
> all our expectation.
>
> Thx,
> Haochen
>
> Currently, for instructions lldt/ltr/verr/verw/lkgs, we are missing
> w suffix for memory operands like sldt/str do. Also the Ew usage is
> not that precise under this scenario. Add Evw to fix this problem.
>
> gas/ChangeLog:
>
> * testsuite/gas/i386/i386.exp: Add LKGS suffix test.
> * testsuite/gas/i386/opcode-intel.d: Add ltr, verr, verw.
> * testsuite/gas/i386/opcode-suffix.d: Ditto.
> * testsuite/gas/i386/opcode.d: Ditto.
> * testsuite/gas/i386/opcode.s: Ditto.
> * testsuite/gas/i386/x86-64-lkgs-suffix.d: New test.
> * testsuite/gas/i386/x86-64-lkgs-suffix.s: Ditto.
>
> opcodes/ChangeLog:
>
> * i386-dis.c (Evw): New.
> (v_w_mode): Ditto.
> (lldt, ltr, verr, verw, lkgs): Change from Ew to Evw.
> (intel_operand_size): Handle v_w_mode.
> (print_register): Ditto.
The suffix is needed in AT&T syntax when there is an ambiguity.
In these cases, there is no ambiguity. I don't think we should add
the unnecessary 'w' suffix here.
> ---
> gas/testsuite/gas/i386/i386.exp | 1 +
> gas/testsuite/gas/i386/opcode-intel.d | 3 +++
> gas/testsuite/gas/i386/opcode-suffix.d | 5 ++++-
> gas/testsuite/gas/i386/opcode.d | 3 +++
> gas/testsuite/gas/i386/opcode.s | 4 ++++
> gas/testsuite/gas/i386/x86-64-lkgs-suffix.d | 15 +++++++++++++++
> gas/testsuite/gas/i386/x86-64-lkgs-suffix.s | 7 +++++++
> opcodes/i386-dis.c | 20 +++++++++++++++-----
> 8 files changed, 52 insertions(+), 6 deletions(-)
> create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs-suffix.d
> create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs-suffix.s
>
> diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
> index bce865c83d1..58f32401610 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -1194,6 +1194,7 @@ if [gas_64_check] then {
> run_list_test "x86-64-amx-complex-inval"
> run_dump_test "x86-64-fred"
> run_dump_test "x86-64-lkgs"
> + run_dump_test "x86-64-lkgs-suffix"
> run_list_test "x86-64-lkgs-inval"
> run_dump_test "x86-64-clzero"
> run_dump_test "x86-64-mwaitx-bdver4"
> diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d
> index 7f641db2892..3a366757a6a 100644
> --- a/gas/testsuite/gas/i386/opcode-intel.d
> +++ b/gas/testsuite/gas/i386/opcode-intel.d
> @@ -589,6 +589,9 @@ Disassembly of section .text:
> *[0-9a-f]+: 85 d8 [ ]*test[ ]+eax,ebx
> *[0-9a-f]+: 85 18 [ ]*test[ ]+(DWORD PTR )?\[eax\],ebx
> *[0-9a-f]+: f1[ ]+int1
> + *[0-9a-f]+: 0f 00 98 90 90 90 90[ ]+ltr[ ]+(WORD PTR )?\[eax-0x6f6f6f70\]
> + *[0-9a-f]+: 0f 00 a0 90 90 90 90[ ]+verr[ ]+(WORD PTR )?\[eax-0x6f6f6f70\]
> + *[0-9a-f]+: 0f 00 a8 90 90 90 90[ ]+verw[ ]+(WORD PTR )?\[eax-0x6f6f6f70\]
> [ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp edx,DWORD PTR \[eax-0x6f6f6f70\]
> [ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\]
> [ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\]
> diff --git a/gas/testsuite/gas/i386/opcode-suffix.d b/gas/testsuite/gas/i386/opcode-suffix.d
> index 152c3b865a0..fdca16a8a6b 100644
> --- a/gas/testsuite/gas/i386/opcode-suffix.d
> +++ b/gas/testsuite/gas/i386/opcode-suffix.d
> @@ -248,7 +248,7 @@ Disassembly of section .text:
> *[0-9a-f]+: fc[ ]+cld
> *[0-9a-f]+: fd[ ]+std
> *[0-9a-f]+: ff 90 90 90 90 90[ ]+calll[ ]+\*-0x6f6f6f70\(%eax\)
> - *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+-0x6f6f6f70\(%eax\)
> + *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldtw[ ]+-0x6f6f6f70\(%eax\)
> *[0-9a-f]+: 0f 01 90 90 90 90 90[ ]+lgdtl[ ]+-0x6f6f6f70\(%eax\)
> *[0-9a-f]+: 0f 02 90 90 90 90 90[ ]+larl[ ]+-0x6f6f6f70\(%eax\),%edx
> *[0-9a-f]+: 0f 03 90 90 90 90 90[ ]+lsll[ ]+-0x6f6f6f70\(%eax\),%edx
> @@ -589,6 +589,9 @@ Disassembly of section .text:
> *[0-9a-f]+: 85 d8 [ ]*testl[ ]+%ebx,%eax
> *[0-9a-f]+: 85 18 [ ]*testl[ ]+%ebx,\(%eax\)
> *[0-9a-f]+: f1[ ]+int1
> + *[0-9a-f]+: 0f 00 98 90 90 90 90[ ]+ltrw[ ]+-0x6f6f6f70\(%eax\)
> + *[0-9a-f]+: 0f 00 a0 90 90 90 90[ ]+verrw[ ]+-0x6f6f6f70\(%eax\)
> + *[0-9a-f]+: 0f 00 a8 90 90 90 90[ ]+verww[ ]+-0x6f6f6f70\(%eax\)
> [ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovpl -0x6f6f6f70\(%eax\),%edx
> [ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnpl -0x6f6f6f70\(%eax\),%edx
> [ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovpw -0x6f6f6f70\(%eax\),%dx
> diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
> index c6ffb018a19..e792962f3c1 100644
> --- a/gas/testsuite/gas/i386/opcode.d
> +++ b/gas/testsuite/gas/i386/opcode.d
> @@ -588,6 +588,9 @@ Disassembly of section .text:
> 9f7: 85 d8 [ ]*test %ebx,%eax
> 9f9: 85 18 [ ]*test %ebx,\(%eax\)
> 9fb: f1 [ ]*int1
> + +[a-f0-9]+: 0f 00 98 90 90 90 90 ltr -0x6f6f6f70\(%eax\)
> + +[a-f0-9]+: 0f 00 a0 90 90 90 90 verr -0x6f6f6f70\(%eax\)
> + +[a-f0-9]+: 0f 00 a8 90 90 90 90 verw -0x6f6f6f70\(%eax\)
> [ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx
> [ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx
> [ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx
> diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
> index 000fff3e852..800dc465f70 100644
> --- a/gas/testsuite/gas/i386/opcode.s
> +++ b/gas/testsuite/gas/i386/opcode.s
> @@ -587,6 +587,10 @@ foo:
>
> int1
>
> + ltr 0x90909090(%eax)
> + verr 0x90909090(%eax)
> + verw 0x90909090(%eax)
> +
> cmovpe 0x90909090(%eax),%edx
> cmovpo 0x90909090(%eax),%edx
> cmovpe 0x90909090(%eax),%dx
> diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-suffix.d b/gas/testsuite/gas/i386/x86-64-lkgs-suffix.d
> new file mode 100644
> index 00000000000..5433938f54d
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-lkgs-suffix.d
> @@ -0,0 +1,15 @@
> +#as: -J --divide
> +#objdump: -dwMsuffix
> +#name: x86_64 LKGS insns (w/ suffix)
> +#source: x86-64-lkgs.d
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <_start>:
> +\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgsw 0x10000000\(%rbp,%r14,8\)
> +\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgsw \(%r9\)
> +\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgsw 0xfe\(%rcx\)
> +\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgsw -0x100\(%rdx\)
> +#pass
> diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-suffix.s b/gas/testsuite/gas/i386/x86-64-lkgs-suffix.s
> new file mode 100644
> index 00000000000..a8a77e34d0c
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-lkgs-suffix.s
> @@ -0,0 +1,7 @@
> + .allow_index_reg
> + .text
> +_start:
> + lkgs 0x10000000(%rbp, %r14, 8)
> + lkgs (%r9)
> + lkgs 254(%rcx)
> + lkgs -256(%rdx)
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index 07fcf3269f9..1dfa7e2b71c 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -387,6 +387,7 @@ fetch_error (const instr_info *ins)
> #define Eva { OP_E, va_mode }
> #define Ev_bnd { OP_E, v_bnd_mode }
> #define EvS { OP_E, v_swap_mode }
> +#define Evw { OP_E, v_w_mode }
> #define Ed { OP_E, d_mode }
> #define Edq { OP_E, dq_mode }
> #define Edb { OP_E, db_mode }
> @@ -605,6 +606,8 @@ enum
> v_swap_mode,
> /* operand size depends on address prefix */
> va_mode,
> + /* operand size depends on prefixes but ignore DFLAG */
> + v_w_mode,
> /* word operand */
> w_mode,
> /* double word operand */
> @@ -2747,10 +2750,10 @@ static const struct dis386 reg_table[][8] = {
> {
> { "sldtD", { Sv }, 0 },
> { "strD", { Sv }, 0 },
> - { "lldt", { Ew }, 0 },
> - { "ltr", { Ew }, 0 },
> - { "verr", { Ew }, 0 },
> - { "verw", { Ew }, 0 },
> + { "lldtD", { Evw }, 0 },
> + { "ltrD", { Evw }, 0 },
> + { "verrD", { Evw }, 0 },
> + { "verwD", { Evw }, 0 },
> { X86_64_TABLE (X86_64_0F00_REG_6) },
> { Bad_Opcode },
> },
> @@ -2997,7 +3000,7 @@ static const struct dis386 prefix_table[][4] = {
> { Bad_Opcode },
> { Bad_Opcode },
> { Bad_Opcode },
> - { "lkgs", { Ew }, 0 },
> + { "lkgsD", { Evw }, 0 },
> },
>
> /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
> @@ -11420,12 +11423,18 @@ intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
> /* Fall through. */
> case v_mode:
> case v_swap_mode:
> + case v_w_mode:
> case dq_mode:
> USED_REX (REX_W);
> if (ins->rex & REX_W)
> oappend (ins, "QWORD PTR ");
> else if (bytemode == dq_mode)
> oappend (ins, "DWORD PTR ");
> + else if (bytemode == v_w_mode)
> + {
> + oappend (ins, "WORD PTR ");
> + ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
> + }
> else
> {
> if (sizeflag & DFLAG)
> @@ -11648,6 +11657,7 @@ print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
> names = att_names8;
> break;
> case w_mode:
> + case v_w_mode:
> names = att_names16;
> break;
> case d_mode:
> --
> 2.31.1
>
@@ -1194,6 +1194,7 @@ if [gas_64_check] then {
run_list_test "x86-64-amx-complex-inval"
run_dump_test "x86-64-fred"
run_dump_test "x86-64-lkgs"
+ run_dump_test "x86-64-lkgs-suffix"
run_list_test "x86-64-lkgs-inval"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
@@ -589,6 +589,9 @@ Disassembly of section .text:
*[0-9a-f]+: 85 d8 [ ]*test[ ]+eax,ebx
*[0-9a-f]+: 85 18 [ ]*test[ ]+(DWORD PTR )?\[eax\],ebx
*[0-9a-f]+: f1[ ]+int1
+ *[0-9a-f]+: 0f 00 98 90 90 90 90[ ]+ltr[ ]+(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+: 0f 00 a0 90 90 90 90[ ]+verr[ ]+(WORD PTR )?\[eax-0x6f6f6f70\]
+ *[0-9a-f]+: 0f 00 a8 90 90 90 90[ ]+verw[ ]+(WORD PTR )?\[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp edx,DWORD PTR \[eax-0x6f6f6f70\]
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp dx,WORD PTR \[eax-0x6f6f6f70\]
@@ -248,7 +248,7 @@ Disassembly of section .text:
*[0-9a-f]+: fc[ ]+cld
*[0-9a-f]+: fd[ ]+std
*[0-9a-f]+: ff 90 90 90 90 90[ ]+calll[ ]+\*-0x6f6f6f70\(%eax\)
- *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldt[ ]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+: 0f 00 90 90 90 90 90[ ]+lldtw[ ]+-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 0f 01 90 90 90 90 90[ ]+lgdtl[ ]+-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 0f 02 90 90 90 90 90[ ]+larl[ ]+-0x6f6f6f70\(%eax\),%edx
*[0-9a-f]+: 0f 03 90 90 90 90 90[ ]+lsll[ ]+-0x6f6f6f70\(%eax\),%edx
@@ -589,6 +589,9 @@ Disassembly of section .text:
*[0-9a-f]+: 85 d8 [ ]*testl[ ]+%ebx,%eax
*[0-9a-f]+: 85 18 [ ]*testl[ ]+%ebx,\(%eax\)
*[0-9a-f]+: f1[ ]+int1
+ *[0-9a-f]+: 0f 00 98 90 90 90 90[ ]+ltrw[ ]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+: 0f 00 a0 90 90 90 90[ ]+verrw[ ]+-0x6f6f6f70\(%eax\)
+ *[0-9a-f]+: 0f 00 a8 90 90 90 90[ ]+verww[ ]+-0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnpl -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovpw -0x6f6f6f70\(%eax\),%dx
@@ -588,6 +588,9 @@ Disassembly of section .text:
9f7: 85 d8 [ ]*test %ebx,%eax
9f9: 85 18 [ ]*test %ebx,\(%eax\)
9fb: f1 [ ]*int1
+ +[a-f0-9]+: 0f 00 98 90 90 90 90 ltr -0x6f6f6f70\(%eax\)
+ +[a-f0-9]+: 0f 00 a0 90 90 90 90 verr -0x6f6f6f70\(%eax\)
+ +[a-f0-9]+: 0f 00 a8 90 90 90 90 verw -0x6f6f6f70\(%eax\)
[ ]*[a-f0-9]+: 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 0f 4b 90 90 90 90 90 cmovnp -0x6f6f6f70\(%eax\),%edx
[ ]*[a-f0-9]+: 66 0f 4a 90 90 90 90 90 cmovp -0x6f6f6f70\(%eax\),%dx
@@ -587,6 +587,10 @@ foo:
int1
+ ltr 0x90909090(%eax)
+ verr 0x90909090(%eax)
+ verw 0x90909090(%eax)
+
cmovpe 0x90909090(%eax),%edx
cmovpo 0x90909090(%eax),%edx
cmovpe 0x90909090(%eax),%dx
new file mode 100644
@@ -0,0 +1,15 @@
+#as: -J --divide
+#objdump: -dwMsuffix
+#name: x86_64 LKGS insns (w/ suffix)
+#source: x86-64-lkgs.d
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgsw 0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgsw \(%r9\)
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgsw 0xfe\(%rcx\)
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgsw -0x100\(%rdx\)
+#pass
new file mode 100644
@@ -0,0 +1,7 @@
+ .allow_index_reg
+ .text
+_start:
+ lkgs 0x10000000(%rbp, %r14, 8)
+ lkgs (%r9)
+ lkgs 254(%rcx)
+ lkgs -256(%rdx)
@@ -387,6 +387,7 @@ fetch_error (const instr_info *ins)
#define Eva { OP_E, va_mode }
#define Ev_bnd { OP_E, v_bnd_mode }
#define EvS { OP_E, v_swap_mode }
+#define Evw { OP_E, v_w_mode }
#define Ed { OP_E, d_mode }
#define Edq { OP_E, dq_mode }
#define Edb { OP_E, db_mode }
@@ -605,6 +606,8 @@ enum
v_swap_mode,
/* operand size depends on address prefix */
va_mode,
+ /* operand size depends on prefixes but ignore DFLAG */
+ v_w_mode,
/* word operand */
w_mode,
/* double word operand */
@@ -2747,10 +2750,10 @@ static const struct dis386 reg_table[][8] = {
{
{ "sldtD", { Sv }, 0 },
{ "strD", { Sv }, 0 },
- { "lldt", { Ew }, 0 },
- { "ltr", { Ew }, 0 },
- { "verr", { Ew }, 0 },
- { "verw", { Ew }, 0 },
+ { "lldtD", { Evw }, 0 },
+ { "ltrD", { Evw }, 0 },
+ { "verrD", { Evw }, 0 },
+ { "verwD", { Evw }, 0 },
{ X86_64_TABLE (X86_64_0F00_REG_6) },
{ Bad_Opcode },
},
@@ -2997,7 +3000,7 @@ static const struct dis386 prefix_table[][4] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "lkgs", { Ew }, 0 },
+ { "lkgsD", { Evw }, 0 },
},
/* PREFIX_0F01_REG_0_MOD_3_RM_6 */
@@ -11420,12 +11423,18 @@ intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
/* Fall through. */
case v_mode:
case v_swap_mode:
+ case v_w_mode:
case dq_mode:
USED_REX (REX_W);
if (ins->rex & REX_W)
oappend (ins, "QWORD PTR ");
else if (bytemode == dq_mode)
oappend (ins, "DWORD PTR ");
+ else if (bytemode == v_w_mode)
+ {
+ oappend (ins, "WORD PTR ");
+ ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
+ }
else
{
if (sizeflag & DFLAG)
@@ -11648,6 +11657,7 @@ print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
names = att_names8;
break;
case w_mode:
+ case v_w_mode:
names = att_names16;
break;
case d_mode: