From patchwork Mon May 22 06:07:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Frager, Neal via Binutils" X-Patchwork-Id: 97056 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1235152vqo; Sun, 21 May 2023 23:09:19 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7x7tSwYOHJA5yCB5uXNaGA93meAMI3eTaHqRE2neiLz4bxN/ph+fAYkiLL9MZ2VTRaY6ZA X-Received: by 2002:a05:6402:544:b0:50c:646:da42 with SMTP id i4-20020a056402054400b0050c0646da42mr7988591edx.28.1684735759699; Sun, 21 May 2023 23:09:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684735759; cv=none; d=google.com; s=arc-20160816; b=ELsH2C+QGFN1cNwm5elqCkLCXsdZM08C/XDv030lH7XBo4hN2zKpz/ajVdM7YGX2hb GZypkA/DW3w8ld+ivqVN8/sHORGAKEY6dEclIHBr47B06qnzvKNZb/2PRgq3CcLSRsgF flVjU5ZksWzwiXWTSZ+Bclk2vip3xYOo2ZB3VgnAr7Vg9DZzub9GLQ8qImVjNeRsB9Ub sp4K47Jl5r0M+qN2GULx8D7rjrgQGVlrmumt/tRUvLkOmpSLq/sa2y7oIjMUHhFaASP2 560DwMQKFmYsJc9fQ/NvqRVulDFxviyfgD1yk3xEaQ9tyAfv5sihosBz6Vr2fJiFSFjJ y7mg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=55nde36lThZuH8fCYmBUwyaMaHR4HL7gReIQXdYKIQI=; b=rLBqVTuHOpN69IbQRorNbNlT5SyiBG7+nfw8v3X3J9zsJbfdJQz2ZY5M+1rIZBpCOa boL0JM2oO42Z0x7dyDLjaUhnuLjtXU6IKXoHdbqRXHpPcywRNaaRRYw0OBSTbgRnynt6 Im3ygtDhBYJR93VDf4YEyVqEtE0Fe4mEw9rY9YWQuV1qc2gYdpJwS34+GqLSqPFe3ke/ y6ksV6QiLuzI5tCBe29RZKNDYhsj3FRKl6tpHhfsXxTZKHeRXgKyWotnaTfgfQ9wugnZ wLkkMukjurgsTIRAUvt53n960Gb82RTOPnbUtPzOAIlTPtIg1mczTorLodAfMDyANrT4 72Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=CjrAols9; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id c15-20020aa7df0f000000b0050bc2e4ec9fsi3581439edy.368.2023.05.21.23.09.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 May 2023 23:09:19 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=CjrAols9; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 829563858C33 for ; Mon, 22 May 2023 06:09:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 829563858C33 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1684735758; bh=55nde36lThZuH8fCYmBUwyaMaHR4HL7gReIQXdYKIQI=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=CjrAols96FaAeZQQMaKkzYMKQU/yTdX3JFt/EEGqpggQKJIwPH5cvODwsINrxcrGZ Fr3mefkbHJ2b1bjPurUzAChySklpUrPiXguyGn91OwwlXCYbPM1uPbiJqaW7UhbxJ9 vX9/dVxjkq9hsU+2iMY6Av9Fu3R5vfM2kzeXQKGI= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id CE2EC3858D20 for ; Mon, 22 May 2023 06:09:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CE2EC3858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10717"; a="350345138" X-IronPort-AV: E=Sophos;i="6.00,183,1681196400"; d="scan'208";a="350345138" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2023 23:09:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10717"; a="734134565" X-IronPort-AV: E=Sophos;i="6.00,183,1681196400"; d="scan'208";a="734134565" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga008.jf.intel.com with ESMTP; 21 May 2023 23:09:06 -0700 Received: from zhangjun-desktop.sh.intel.com (zhangjun-desktop.sh.intel.com [10.239.152.118]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 7640C100FB05; Mon, 22 May 2023 14:09:05 +0800 (CST) To: binutils@sourceware.org Cc: jbeulich@suse.com, hjl.tools@gmail.com, jun.zhang@intel.com Subject: [PATCH v2] Support Intel FRED LKGS Date: Mon, 22 May 2023 14:07:26 +0800 Message-Id: <20230522060726.101037-1-jun.zhang@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "Zhang, Jun via Binutils" From: "Frager, Neal via Binutils" Reply-To: "Zhang, Jun" Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1766573079471963635?= X-GMAIL-MSGID: =?utf-8?q?1766573484110752151?= This patch is the second version about Intel FRED and LKGS instructions. It has fixed all comments except "Ew", because I don't know how to fix it. Jan, could you help me? please ignore the previous email. BRs, Jun gas/ChangeLog: * NEWS: Support Intel FRED LKGS. * config/tc-i386.c: Add fred lkgs * doc/c-i386.texi: Document .fred, .lkgs. * testsuite/gas/i386/i386.exp: Add FRED LKGS tests * testsuite/gas/i386/x86-64-fred-intel.d: Ditto. * testsuite/gas/i386/x86-64-fred.d: Ditto. * testsuite/gas/i386/x86-64-fred.s: Ditto. * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto. * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto. * testsuite/gas/i386/x86-64-lkgs.d: Ditto. * testsuite/gas/i386/x86-64-lkgs.s: Ditto. opcodes/ChangeLog: * i386-dis.c: New entry for fred, lkgs. * i386-gen.c: Add CPU_FRED CPU_LKGS. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h: Add fred, lkgs. * i386-opc.tbl: Add FRED, LKGS instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 4 ++ gas/config/tc-i386.c | 2 + gas/doc/c-i386.texi | 3 ++ gas/testsuite/gas/i386/i386.exp | 3 ++ gas/testsuite/gas/i386/x86-64-fred-intel.d | 15 ++++++++ gas/testsuite/gas/i386/x86-64-fred.d | 15 ++++++++ gas/testsuite/gas/i386/x86-64-fred.s | 11 ++++++ gas/testsuite/gas/i386/x86-64-lkgs-intel.d | 25 +++++++++++++ gas/testsuite/gas/i386/x86-64-lkgs-inval.l | 9 +++++ gas/testsuite/gas/i386/x86-64-lkgs-inval.s | 14 +++++++ gas/testsuite/gas/i386/x86-64-lkgs.d | 25 +++++++++++++ gas/testsuite/gas/i386/x86-64-lkgs.s | 21 +++++++++++ opcodes/i386-dis.c | 43 +++++++++++++++++++++- opcodes/i386-gen.c | 4 ++ opcodes/i386-opc.h | 6 +++ opcodes/i386-opc.tbl | 14 +++++++ 16 files changed, 212 insertions(+), 2 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-fred-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-fred.d create mode 100644 gas/testsuite/gas/i386/x86-64-fred.s create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs.d create mode 100644 gas/testsuite/gas/i386/x86-64-lkgs.s diff --git a/gas/NEWS b/gas/NEWS index 42a2005d7c9..ea172fe9cdb 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,9 @@ -*- text -*- +* Add support for Intel FRED instructions. + +* Add support for Intel LKGS instructions. + * Add support for Intel AMX-COMPLEX instructions. * Add SME2 support to the AArch64 port. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 29b7734b1ac..f30b28eba87 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1141,6 +1141,8 @@ static const arch_entry cpu_arch[] = SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), SUBARCH (rao_int, RAO_INT, RAO_INT, false), SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false), + SUBARCH (fred, FRED, ANY_FRED, false), + SUBARCH (lkgs, LKGS, ANY_LKGS, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 15d060b2a33..49b6e3b1abb 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -205,6 +205,8 @@ accept various extension mnemonics. For example, @code{msrlist}, @code{avx_ne_convert}, @code{rao_int}, +@code{fred}, +@code{lkgs}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1634,6 +1636,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist} @item @samp{.avx_ne_convert} @tab @samp{.rao_int} +@item @samp{.fred} @tab @samp{.lkgs} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 40e75ac6f88..e2958fd552f 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -1189,6 +1189,9 @@ if [gas_64_check] then { run_dump_test "x86-64-amx-complex-intel" run_dump_test "x86-64-amx-complex-bad" run_list_test "x86-64-amx-complex-inval" + run_dump_test "x86-64-fred" + run_dump_test "x86-64-lkgs" + run_list_test "x86-64-lkgs-inval" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/x86-64-fred-intel.d b/gas/testsuite/gas/i386/x86-64-fred-intel.d new file mode 100644 index 00000000000..aef98af2d81 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-fred-intel.d @@ -0,0 +1,15 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 FRED insns (Intel disassembly) +#source: x86-64-fred.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets +\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu +\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets +\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu +#pass diff --git a/gas/testsuite/gas/i386/x86-64-fred.d b/gas/testsuite/gas/i386/x86-64-fred.d new file mode 100644 index 00000000000..01990f1cec8 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-fred.d @@ -0,0 +1,15 @@ +#as: +#objdump: -dw +#name: x86_64 FRED insns +#source: x86-64-fred.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets +\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu +\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets +\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu +#pass diff --git a/gas/testsuite/gas/i386/x86-64-fred.s b/gas/testsuite/gas/i386/x86-64-fred.s new file mode 100644 index 00000000000..0e5d3d3d469 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-fred.s @@ -0,0 +1,11 @@ +# Check 64bit FRED instructions + + .allow_index_reg + .text +_start: + erets #FRED + eretu #FRED + +.intel_syntax noprefix + erets #FRED + eretu #FRED diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-intel.d b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d new file mode 100644 index 00000000000..0f4a6fba6d3 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d @@ -0,0 +1,25 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 LKGS insns (Intel disassembly) +#source: x86-64-lkgs.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w +\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\] +\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\] +\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs WORD PTR \[rdx-0x100\] +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w +\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\] +\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\] +\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\] +\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs WORD PTR \[rdx-0x100\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-inval.l b/gas/testsuite/gas/i386/x86-64-lkgs-inval.l new file mode 100644 index 00000000000..77ee7d7c8b9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-lkgs-inval.l @@ -0,0 +1,9 @@ +.* Assembler messages: +.*:5: Error: invalid instruction suffix for `lkgs' +.*:6: Error: invalid instruction suffix for `lkgs' +.*:7: Error: invalid instruction suffix for `lkgs' +.*:8: Error: invalid instruction suffix for `lkgs' +.*:11: Error: invalid instruction suffix for `lkgs' +.*:12: Error: invalid instruction suffix for `lkgs' +.*:13: Error: invalid instruction suffix for `lkgs' +.*:14: Error: invalid instruction suffix for `lkgs' diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-inval.s b/gas/testsuite/gas/i386/x86-64-lkgs-inval.s new file mode 100644 index 00000000000..1dbce14bae4 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-lkgs-inval.s @@ -0,0 +1,14 @@ +# Check illegal 64bit suffer usage in LKGS instructions + + .text +_start: + lkgsb %r12 #LKGS + lkgss %r12 #LKGS + lkgsb (%r9) #LKGS + lkgss (%r9) #LKGS + + .intel_syntax noprefix + lkgsb %r12 #LKGS + lkgsb BYTE PTR [r9] #LKGS + lkgsd DWORD PTR [r9] #LKGS + lkgsq QWORD PTR [r9] #LKGS diff --git a/gas/testsuite/gas/i386/x86-64-lkgs.d b/gas/testsuite/gas/i386/x86-64-lkgs.d new file mode 100644 index 00000000000..207143da574 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-lkgs.d @@ -0,0 +1,25 @@ +#as: +#objdump: -dw +#name: x86_64 LKGS insns +#source: x86-64-lkgs.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w +\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\) +\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\) +\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs -0x100\(%rdx\) +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w +\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w +\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\) +\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\) +\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\) +\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs -0x100\(%rdx\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-lkgs.s b/gas/testsuite/gas/i386/x86-64-lkgs.s new file mode 100644 index 00000000000..546bbcc580a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-lkgs.s @@ -0,0 +1,21 @@ +# Check 64bit LKGS instructions + + .allow_index_reg + .text +_start: + lkgs %r12 #LKGS + lkgs %r12w #LKGS + lkgsw %r12w #LKGS + lkgs 0x10000000(%rbp, %r14, 8) #LKGS + lkgs (%r9) #LKGS + lkgs 254(%rcx) #LKGS Disp32(fe000000) + lkgs -256(%rdx) #LKGS Disp32(00ffffff) + +.intel_syntax noprefix + lkgs r12 #LKGS + lkgs r12w #LKGS + lkgsw r12w #LKGS + lkgs WORD PTR [rbp+r14*8+0x10000000] #LKGS + lkgs WORD PTR [r9] #LKGS + lkgs WORD PTR [rcx+254] #LKGS Disp32(fe000000) + lkgs WORD PTR [rdx-256] #LKGS Disp32(00ffffff) diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index b529fe705bc..1a0b5e4fb10 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1025,7 +1025,9 @@ enum enum { PREFIX_90 = 0, + PREFIX_0F00_REG_6_X86_64, PREFIX_0F01_REG_0_MOD_3_RM_6, + PREFIX_0F01_REG_1_RM_2, PREFIX_0F01_REG_1_RM_4, PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, @@ -1310,10 +1312,13 @@ enum X86_64_E8, X86_64_E9, X86_64_EA, + X86_64_0F00_REG_6, X86_64_0F01_REG_0, X86_64_0F01_REG_0_MOD_3_RM_6_P_1, X86_64_0F01_REG_0_MOD_3_RM_6_P_3, X86_64_0F01_REG_1, + X86_64_0F01_REG_1_RM_2_PREFIX_1, + X86_64_0F01_REG_1_RM_2_PREFIX_3, X86_64_0F01_REG_1_RM_5_PREFIX_2, X86_64_0F01_REG_1_RM_6_PREFIX_2, X86_64_0F01_REG_1_RM_7_PREFIX_2, @@ -2755,7 +2760,7 @@ static const struct dis386 reg_table[][8] = { { "ltr", { Ew }, 0 }, { "verr", { Ew }, 0 }, { "verw", { Ew }, 0 }, - { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F00_REG_6) }, { Bad_Opcode }, }, /* REG_0F01 */ @@ -2996,6 +3001,14 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, + /* PREFIX_0F00_REG_6_X86_64 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "lkgs", { Ew }, 0 }, + }, + /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ { { "wrmsrns", { Skip_MODRM }, 0 }, @@ -3004,6 +3017,14 @@ static const struct dis386 prefix_table[][4] = { { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, }, + /* PREFIX_0F01_REG_1_RM_2 */ + { + { "clac", { Skip_MODRM }, 0 }, + { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)}, + }, + /* PREFIX_0F01_REG_1_RM_4 */ { { Bad_Opcode }, @@ -4371,6 +4392,12 @@ static const struct dis386 x86_64_table[][2] = { { "{l|}jmp{P|}", { Ap }, 0 }, }, + /* X86_64_0F00_REG_6 */ + { + { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) }, + }, + /* X86_64_0F01_REG_0 */ { { "sgdt{Q|Q}", { M }, 0 }, @@ -4395,6 +4422,18 @@ static const struct dis386 x86_64_table[][2] = { { "sidt", { M }, 0 }, }, + /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */ + { + { Bad_Opcode }, + { "eretu", { Skip_MODRM }, 0 }, + }, + + /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */ + { + { Bad_Opcode }, + { "erets", { Skip_MODRM }, 0 }, + }, + /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */ { { Bad_Opcode }, @@ -8702,7 +8741,7 @@ static const struct dis386 rm_table[][8] = { /* RM_0F01_REG_1 */ { "monitor", { { OP_Monitor, 0 } }, 0 }, { "mwait", { { OP_Mwait, 0 } }, 0 }, - { "clac", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) }, { "stac", { Skip_MODRM }, 0 }, { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) }, { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index c2ac3c6832d..1db555d8615 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -164,6 +164,8 @@ static const dependency isa_dependencies[] = "AVX2" }, { "AVX_NE_CONVERT", "AVX2" }, + { "FRED", + "LKGS" }, { "AVX512F", "AVX2" }, { "AVX512CD", @@ -362,6 +364,8 @@ static bitfield cpu_flags[] = BITFIELD (MSRLIST), BITFIELD (AVX_NE_CONVERT), BITFIELD (RAO_INT), + BITFIELD (FRED), + BITFIELD (LKGS), BITFIELD (MWAITX), BITFIELD (CLZERO), BITFIELD (OSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index b17e8341aa2..d65392aca8d 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -229,6 +229,10 @@ enum CpuAVX_NE_CONVERT, /* Intel RAO INT Instructions support required. */ CpuRAO_INT, + /* fred instruction required */ + CpuFRED, + /* lkgs instruction required */ + CpuLKGS, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -424,6 +428,8 @@ typedef union i386_cpu_flags unsigned int cpumsrlist:1; unsigned int cpuavx_ne_convert:1; unsigned int cpurao_int:1; + unsigned int cpufred:1; + unsigned int cpulkgs:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 15d48eeb4c7..a4db19c001a 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3351,3 +3351,17 @@ aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64 axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // RAO-INT instructions end. + +// FRED instructions. + +erets, 0xf20f01ca, FRED|x64, NoSuf, {} +eretu, 0xf30f01ca, FRED|x64, NoSuf, {} + +// FRED instructions end. + +// LKGS instructions. + +lkgs, 0xf20f00/6, LKGS|x64, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 } +lkgs, 0xf20f00/6, LKGS|x64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex } + +// LKGS instructions end.